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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Graeme Russd47ab0e2011-12-23 16:51:29 +11002/*
3 * (C) Copyright 2011
4 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russd47ab0e2011-12-23 16:51:29 +11005 */
Bin Mengc17ca6b2015-08-13 00:29:10 -07006
Graeme Russd47ab0e2011-12-23 16:51:29 +11007#include <common.h>
Simon Glass67c4e9f2019-11-14 12:57:45 -07008#include <init.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +09009#include <linux/errno.h>
Simon Glassdb55bd72015-01-01 16:18:11 -070010#include <asm/mtrr.h>
Graeme Russd47ab0e2011-12-23 16:51:29 +110011
12DECLARE_GLOBAL_DATA_PTR;
13
Graeme Russa1d57b72011-12-23 21:14:22 +110014int init_cache_f_r(void)
15{
Simon Glasscc2d27d2019-09-25 08:56:49 -060016 bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) ||
17 IS_ENABLED(CONFIG_FSP_VERSION2);
Simon Glassdb55bd72015-01-01 16:18:11 -070018 int ret;
19
Simon Glasscc2d27d2019-09-25 08:56:49 -060020 do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
21 !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
22
23 if (do_mtrr) {
24 ret = mtrr_commit(false);
25 /*
26 * If MTRR MSR is not implemented by the processor, just ignore
27 * it
28 */
29 if (ret && ret != -ENOSYS)
30 return ret;
31 }
32
Simon Glass526aabe2020-04-26 09:12:55 -060033 if (!ll_boot_init())
34 return 0;
35
Graeme Russa1d57b72011-12-23 21:14:22 +110036 /* Initialise the CPU cache(s) */
37 return init_cache();
38}