wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 2 | * Copyright 2004,2007,2008 Freescale Semiconductor, Inc. |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 3 | * (C) Copyright 2002, 2003 Motorola Inc. |
| 4 | * Xianghua Xiao (X.Xiao@motorola.com) |
| 5 | * |
| 6 | * (C) Copyright 2000 |
| 7 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 28 | #include <config.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 29 | #include <common.h> |
| 30 | #include <watchdog.h> |
| 31 | #include <command.h> |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 32 | #include <tsec.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 33 | #include <asm/cache.h> |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 34 | #include <asm/io.h> |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 35 | |
James Yang | 591933c | 2008-02-08 16:44:53 -0600 | [diff] [blame] | 36 | DECLARE_GLOBAL_DATA_PTR; |
| 37 | |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 38 | struct cpu_type cpu_type_list [] = { |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 39 | CPU_TYPE_ENTRY(8533, 8533), |
| 40 | CPU_TYPE_ENTRY(8533, 8533_E), |
Kumar Gala | ef50d6c | 2008-08-12 11:14:19 -0500 | [diff] [blame] | 41 | CPU_TYPE_ENTRY(8536, 8536), |
| 42 | CPU_TYPE_ENTRY(8536, 8536_E), |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 43 | CPU_TYPE_ENTRY(8540, 8540), |
| 44 | CPU_TYPE_ENTRY(8541, 8541), |
| 45 | CPU_TYPE_ENTRY(8541, 8541_E), |
| 46 | CPU_TYPE_ENTRY(8543, 8543), |
| 47 | CPU_TYPE_ENTRY(8543, 8543_E), |
| 48 | CPU_TYPE_ENTRY(8544, 8544), |
| 49 | CPU_TYPE_ENTRY(8544, 8544_E), |
| 50 | CPU_TYPE_ENTRY(8545, 8545), |
| 51 | CPU_TYPE_ENTRY(8545, 8545_E), |
| 52 | CPU_TYPE_ENTRY(8547, 8547_E), |
| 53 | CPU_TYPE_ENTRY(8548, 8548), |
| 54 | CPU_TYPE_ENTRY(8548, 8548_E), |
| 55 | CPU_TYPE_ENTRY(8555, 8555), |
| 56 | CPU_TYPE_ENTRY(8555, 8555_E), |
| 57 | CPU_TYPE_ENTRY(8560, 8560), |
| 58 | CPU_TYPE_ENTRY(8567, 8567), |
| 59 | CPU_TYPE_ENTRY(8567, 8567_E), |
| 60 | CPU_TYPE_ENTRY(8568, 8568), |
| 61 | CPU_TYPE_ENTRY(8568, 8568_E), |
| 62 | CPU_TYPE_ENTRY(8572, 8572), |
| 63 | CPU_TYPE_ENTRY(8572, 8572_E), |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 64 | }; |
| 65 | |
Anatolij Gustschin | 96026d4 | 2008-06-12 12:40:11 +0200 | [diff] [blame] | 66 | struct cpu_type *identify_cpu(u32 ver) |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 67 | { |
| 68 | int i; |
| 69 | for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) |
| 70 | if (cpu_type_list[i].soc_ver == ver) |
| 71 | return &cpu_type_list[i]; |
| 72 | |
| 73 | return NULL; |
| 74 | } |
| 75 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 76 | int checkcpu (void) |
| 77 | { |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 78 | sys_info_t sysinfo; |
| 79 | uint lcrr; /* local bus clock ratio register */ |
| 80 | uint clkdiv; /* clock divider portion of lcrr */ |
| 81 | uint pvr, svr; |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 82 | uint fam; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 83 | uint ver; |
| 84 | uint major, minor; |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 85 | struct cpu_type *cpu; |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 86 | char buf1[32], buf2[32]; |
Kumar Gala | ee1e35b | 2008-05-29 01:21:24 -0500 | [diff] [blame] | 87 | #ifdef CONFIG_DDR_CLK_FREQ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
Jason Jin | c039111 | 2008-09-27 14:40:57 +0800 | [diff] [blame] | 89 | u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) |
| 90 | >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; |
Kumar Gala | ee1e35b | 2008-05-29 01:21:24 -0500 | [diff] [blame] | 91 | #else |
| 92 | u32 ddr_ratio = 0; |
| 93 | #endif |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 94 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 95 | svr = get_svr(); |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 96 | ver = SVR_SOC_VER(svr); |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 97 | major = SVR_MAJ(svr); |
Kumar Gala | ef50d6c | 2008-08-12 11:14:19 -0500 | [diff] [blame] | 98 | #ifdef CONFIG_MPC8536 |
| 99 | major &= 0x7; /* the msb of this nibble is a mfg code */ |
| 100 | #endif |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 101 | minor = SVR_MIN(svr); |
| 102 | |
Ed Swarthout | 6856b3d | 2008-10-08 23:37:59 -0500 | [diff] [blame] | 103 | #if (CONFIG_NUM_CPUS > 1) |
| 104 | volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); |
| 105 | printf("CPU%d: ", pic->whoami); |
| 106 | #else |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 107 | puts("CPU: "); |
Ed Swarthout | 6856b3d | 2008-10-08 23:37:59 -0500 | [diff] [blame] | 108 | #endif |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 109 | |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 110 | cpu = identify_cpu(ver); |
| 111 | if (cpu) { |
| 112 | puts(cpu->name); |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 113 | |
Kim Phillips | 06b4186 | 2008-06-17 17:45:22 -0500 | [diff] [blame] | 114 | if (IS_E_PROCESSOR(svr)) |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 115 | puts("E"); |
| 116 | } else { |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 117 | puts("Unknown"); |
Kumar Gala | 4dbdb76 | 2008-06-10 16:53:46 -0500 | [diff] [blame] | 118 | } |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 119 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 120 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 121 | |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 122 | pvr = get_pvr(); |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 123 | fam = PVR_FAM(pvr); |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 124 | ver = PVR_VER(pvr); |
| 125 | major = PVR_MAJ(pvr); |
| 126 | minor = PVR_MIN(pvr); |
| 127 | |
| 128 | printf("Core: "); |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 129 | switch (fam) { |
| 130 | case PVR_FAM(PVR_85xx): |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 131 | puts("E500"); |
| 132 | break; |
| 133 | default: |
| 134 | puts("Unknown"); |
| 135 | break; |
| 136 | } |
Kumar Gala | 0f060c3 | 2008-10-23 01:47:38 -0500 | [diff] [blame] | 137 | |
| 138 | if (PVR_MEM(pvr) == 0x03) |
| 139 | puts("MC"); |
| 140 | |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 141 | printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); |
| 142 | |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 143 | get_sys_info(&sysinfo); |
| 144 | |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 145 | puts("Clock Configuration:\n"); |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 146 | printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freqProcessor)); |
| 147 | printf("CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); |
Kumar Gala | ee1e35b | 2008-05-29 01:21:24 -0500 | [diff] [blame] | 148 | |
Kumar Gala | d435793 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 149 | switch (ddr_ratio) { |
| 150 | case 0x0: |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 151 | printf(" DDR:%-4s MHz (%s MT/s data rate), ", |
| 152 | strmhz(buf1, sysinfo.freqDDRBus/2), |
| 153 | strmhz(buf2, sysinfo.freqDDRBus)); |
Kumar Gala | d435793 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 154 | break; |
| 155 | case 0x7: |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 156 | printf(" DDR:%-4s MHz (%s MT/s data rate) (Synchronous), ", |
| 157 | strmhz(buf1, sysinfo.freqDDRBus/2), |
| 158 | strmhz(buf2, sysinfo.freqDDRBus)); |
Kumar Gala | d435793 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 159 | break; |
| 160 | default: |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 161 | printf(" DDR:%-4s MHz (%s MT/s data rate) (Asynchronous), ", |
| 162 | strmhz(buf1, sysinfo.freqDDRBus/2), |
| 163 | strmhz(buf2, sysinfo.freqDDRBus)); |
Kumar Gala | d435793 | 2007-12-07 04:59:26 -0600 | [diff] [blame] | 164 | break; |
| 165 | } |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 166 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 167 | #if defined(CONFIG_SYS_LBC_LCRR) |
| 168 | lcrr = CONFIG_SYS_LBC_LCRR; |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 169 | #else |
| 170 | { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 171 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 172 | |
| 173 | lcrr = lbc->lcrr; |
| 174 | } |
| 175 | #endif |
| 176 | clkdiv = lcrr & 0x0f; |
| 177 | if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { |
Kumar Gala | ef50d6c | 2008-08-12 11:14:19 -0500 | [diff] [blame] | 178 | #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544) || \ |
| 179 | defined(CONFIG_MPC8572) || defined(CONFIG_MPC8536) |
Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 180 | /* |
| 181 | * Yes, the entire PQ38 family use the same |
| 182 | * bit-representation for twice the clock divider values. |
| 183 | */ |
| 184 | clkdiv *= 2; |
| 185 | #endif |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 186 | printf("LBC:%-4s MHz\n", |
| 187 | strmhz(buf1, sysinfo.freqSystemBus / clkdiv)); |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 188 | } else { |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 189 | printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr); |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 190 | } |
| 191 | |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 192 | #ifdef CONFIG_CPM2 |
Wolfgang Denk | 08ef89e | 2008-10-19 02:35:49 +0200 | [diff] [blame] | 193 | printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); |
Andy Fleming | 1ced121 | 2008-02-06 01:19:40 -0600 | [diff] [blame] | 194 | #endif |
wdenk | 97d80fc | 2004-06-09 00:34:46 +0000 | [diff] [blame] | 195 | |
wdenk | 6c9e789 | 2005-03-15 22:56:53 +0000 | [diff] [blame] | 196 | puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 197 | |
| 198 | return 0; |
| 199 | } |
| 200 | |
| 201 | |
| 202 | /* ------------------------------------------------------------------------- */ |
| 203 | |
| 204 | int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) |
| 205 | { |
Zang Roy-r61911 | 96629cb | 2006-12-05 16:42:30 +0800 | [diff] [blame] | 206 | uint pvr; |
| 207 | uint ver; |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 208 | unsigned long val, msr; |
| 209 | |
Zang Roy-r61911 | 96629cb | 2006-12-05 16:42:30 +0800 | [diff] [blame] | 210 | pvr = get_pvr(); |
| 211 | ver = PVR_VER(pvr); |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 212 | |
Zang Roy-r61911 | 96629cb | 2006-12-05 16:42:30 +0800 | [diff] [blame] | 213 | if (ver & 1){ |
| 214 | /* e500 v2 core has reset control register */ |
| 215 | volatile unsigned int * rstcr; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 216 | rstcr = (volatile unsigned int *)(CONFIG_SYS_IMMR + 0xE00B0); |
Wolfgang Denk | 2f15278 | 2007-05-05 18:23:11 +0200 | [diff] [blame] | 217 | *rstcr = 0x2; /* HRESET_REQ */ |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 218 | udelay(100); |
| 219 | } |
| 220 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 221 | /* |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 222 | * Fallthrough if the code above failed |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 223 | * Initiate hard reset in debug control register DBCR0 |
| 224 | * Make sure MSR[DE] = 1 |
| 225 | */ |
urwithsughosh@gmail.com | df90968 | 2007-09-24 13:32:13 -0400 | [diff] [blame] | 226 | |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 227 | msr = mfmsr (); |
| 228 | msr |= MSR_DE; |
| 229 | mtmsr (msr); |
urwithsughosh@gmail.com | df90968 | 2007-09-24 13:32:13 -0400 | [diff] [blame] | 230 | |
Sergei Poselenov | 793670c | 2008-05-08 14:17:08 +0200 | [diff] [blame] | 231 | val = mfspr(DBCR0); |
| 232 | val |= 0x70000000; |
| 233 | mtspr(DBCR0,val); |
| 234 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 235 | return 1; |
| 236 | } |
| 237 | |
| 238 | |
| 239 | /* |
| 240 | * Get timebase clock frequency |
| 241 | */ |
| 242 | unsigned long get_tbclk (void) |
| 243 | { |
James Yang | 591933c | 2008-02-08 16:44:53 -0600 | [diff] [blame] | 244 | return (gd->bus_clk + 4UL)/8UL; |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 245 | } |
| 246 | |
| 247 | |
| 248 | #if defined(CONFIG_WATCHDOG) |
| 249 | void |
| 250 | watchdog_reset(void) |
| 251 | { |
| 252 | int re_enable = disable_interrupts(); |
| 253 | reset_85xx_watchdog(); |
| 254 | if (re_enable) enable_interrupts(); |
| 255 | } |
| 256 | |
| 257 | void |
| 258 | reset_85xx_watchdog(void) |
| 259 | { |
| 260 | /* |
| 261 | * Clear TSR(WIS) bit by writing 1 |
| 262 | */ |
| 263 | unsigned long val; |
Andy Fleming | 03b81b4 | 2007-04-23 01:44:44 -0500 | [diff] [blame] | 264 | val = mfspr(SPRN_TSR); |
| 265 | val |= TSR_WIS; |
| 266 | mtspr(SPRN_TSR, val); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 267 | } |
| 268 | #endif /* CONFIG_WATCHDOG */ |
| 269 | |
| 270 | #if defined(CONFIG_DDR_ECC) |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 271 | void dma_init(void) { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 272 | volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 273 | |
| 274 | dma->satr0 = 0x02c40000; |
| 275 | dma->datr0 = 0x02c40000; |
Andy Fleming | 03b81b4 | 2007-04-23 01:44:44 -0500 | [diff] [blame] | 276 | dma->sr0 = 0xfffffff; /* clear any errors */ |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 277 | asm("sync; isync; msync"); |
| 278 | return; |
| 279 | } |
| 280 | |
| 281 | uint dma_check(void) { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 282 | volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 283 | volatile uint status = dma->sr0; |
| 284 | |
| 285 | /* While the channel is busy, spin */ |
| 286 | while((status & 4) == 4) { |
| 287 | status = dma->sr0; |
| 288 | } |
| 289 | |
Andy Fleming | 03b81b4 | 2007-04-23 01:44:44 -0500 | [diff] [blame] | 290 | /* clear MR0[CS] channel start bit */ |
| 291 | dma->mr0 &= 0x00000001; |
| 292 | asm("sync;isync;msync"); |
| 293 | |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 294 | if (status != 0) { |
| 295 | printf ("DMA Error: status = %x\n", status); |
| 296 | } |
| 297 | return status; |
| 298 | } |
| 299 | |
| 300 | int dma_xfer(void *dest, uint count, void *src) { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 301 | volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); |
wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 302 | |
| 303 | dma->dar0 = (uint) dest; |
| 304 | dma->sar0 = (uint) src; |
| 305 | dma->bcr0 = count; |
| 306 | dma->mr0 = 0xf000004; |
| 307 | asm("sync;isync;msync"); |
| 308 | dma->mr0 = 0xf000005; |
| 309 | asm("sync;isync;msync"); |
| 310 | return dma_check(); |
| 311 | } |
| 312 | #endif |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 313 | |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 314 | /* |
Sergei Poselenov | 59f6305 | 2008-08-15 15:42:11 +0200 | [diff] [blame] | 315 | * Configures a UPM. The function requires the respective MxMR to be set |
| 316 | * before calling this function. "size" is the number or entries, not a sizeof. |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 317 | */ |
| 318 | void upmconfig (uint upm, uint * table, uint size) |
| 319 | { |
| 320 | int i, mdr, mad, old_mad = 0; |
| 321 | volatile u32 *mxmr; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 322 | volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 323 | volatile u32 *brp,*orp; |
| 324 | volatile u8* dummy = NULL; |
| 325 | int upmmask; |
| 326 | |
| 327 | switch (upm) { |
| 328 | case UPMA: |
| 329 | mxmr = &lbc->mamr; |
| 330 | upmmask = BR_MS_UPMA; |
| 331 | break; |
| 332 | case UPMB: |
| 333 | mxmr = &lbc->mbmr; |
| 334 | upmmask = BR_MS_UPMB; |
| 335 | break; |
| 336 | case UPMC: |
| 337 | mxmr = &lbc->mcmr; |
| 338 | upmmask = BR_MS_UPMC; |
| 339 | break; |
| 340 | default: |
| 341 | printf("%s: Bad UPM index %d to configure\n", __FUNCTION__, upm); |
| 342 | hang(); |
| 343 | } |
| 344 | |
| 345 | /* Find the address for the dummy write transaction */ |
| 346 | for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8; |
| 347 | i++, brp += 2, orp += 2) { |
Wolfgang Denk | e093a24 | 2008-06-28 23:34:37 +0200 | [diff] [blame] | 348 | |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 349 | /* Look for a valid BR with selected UPM */ |
Sergei Poselenov | 59f6305 | 2008-08-15 15:42:11 +0200 | [diff] [blame] | 350 | if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) { |
| 351 | dummy = (volatile u8*)(in_be32(brp) & BR_BA); |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 352 | break; |
| 353 | } |
| 354 | } |
| 355 | |
| 356 | if (i == 8) { |
| 357 | printf("Error: %s() could not find matching BR\n", __FUNCTION__); |
| 358 | hang(); |
| 359 | } |
| 360 | |
| 361 | for (i = 0; i < size; i++) { |
| 362 | /* 1 */ |
Sergei Poselenov | 59f6305 | 2008-08-15 15:42:11 +0200 | [diff] [blame] | 363 | out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_WARR | i); |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 364 | /* 2 */ |
| 365 | out_be32(&lbc->mdr, table[i]); |
| 366 | /* 3 */ |
| 367 | mdr = in_be32(&lbc->mdr); |
| 368 | /* 4 */ |
| 369 | *(volatile u8 *)dummy = 0; |
| 370 | /* 5 */ |
| 371 | do { |
Sergei Poselenov | 59f6305 | 2008-08-15 15:42:11 +0200 | [diff] [blame] | 372 | mad = in_be32(mxmr) & MxMR_MAD_MSK; |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 373 | } while (mad <= old_mad && !(!mad && i == (size-1))); |
| 374 | old_mad = mad; |
| 375 | } |
Sergei Poselenov | 59f6305 | 2008-08-15 15:42:11 +0200 | [diff] [blame] | 376 | out_be32(mxmr, (in_be32(mxmr) & 0x4fffffc0) | MxMR_OP_NORM); |
Sergei Poselenov | 740280e | 2008-06-06 15:42:40 +0200 | [diff] [blame] | 377 | } |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 378 | |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 379 | |
| 380 | /* |
| 381 | * Initializes on-chip ethernet controllers. |
| 382 | * to override, implement board_eth_init() |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 383 | */ |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 384 | int cpu_eth_init(bd_t *bis) |
| 385 | { |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 386 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85xx_FEC) |
| 387 | tsec_standard_init(bis); |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 388 | #endif |
Andy Fleming | 75b9d4a | 2008-08-31 16:33:26 -0500 | [diff] [blame] | 389 | |
Ben Warren | dd35479 | 2008-06-23 22:57:27 -0700 | [diff] [blame] | 390 | return 0; |
| 391 | } |