blob: 467fe251d8f7a3776cc1591590e4a738c8ccce86 [file] [log] [blame]
Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "x86 architecture"
2 depends on X86
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "x86"
6
Masahiro Yamada45ccec82014-10-24 01:30:43 +09007config USE_PRIVATE_LIBGCC
8 default y
9
Simon Glass81563452015-03-06 13:19:02 -070010config SYS_VSNPRINTF
11 default y
12
Masahiro Yamadadd840582014-07-30 14:08:14 +090013choice
Bin Meng65c4ac02015-04-27 23:22:24 +080014 prompt "Mainboard vendor"
15 default VENDOR_COREBOOT
Masahiro Yamadadd840582014-07-30 14:08:14 +090016
Bin Meng65c4ac02015-04-27 23:22:24 +080017config VENDOR_COREBOOT
18 bool "coreboot"
Simon Glass8ef07572014-11-12 22:42:07 -070019
Bin Meng65c4ac02015-04-27 23:22:24 +080020config VENDOR_GOOGLE
21 bool "Google"
Masahiro Yamadadd840582014-07-30 14:08:14 +090022
Bin Meng65c4ac02015-04-27 23:22:24 +080023config VENDOR_INTEL
24 bool "Intel"
Bin Mengef46bea2015-02-02 22:35:29 +080025
Masahiro Yamadadd840582014-07-30 14:08:14 +090026endchoice
27
Bin Meng65c4ac02015-04-27 23:22:24 +080028# board-specific options below
29source "board/coreboot/Kconfig"
30source "board/google/Kconfig"
31source "board/intel/Kconfig"
32
Bin Meng029194a2015-04-27 23:22:25 +080033# platform-specific options below
34source "arch/x86/cpu/baytrail/Kconfig"
35source "arch/x86/cpu/coreboot/Kconfig"
36source "arch/x86/cpu/ivybridge/Kconfig"
37source "arch/x86/cpu/quark/Kconfig"
38source "arch/x86/cpu/queensbay/Kconfig"
39
40# architecture-specific options below
41
Simon Glassb724bd72015-02-11 16:32:59 -070042config SYS_MALLOC_F_LEN
43 default 0x800
44
Simon Glass70a09c62014-11-12 22:42:10 -070045config RAMBASE
46 hex
47 default 0x100000
48
Simon Glass70a09c62014-11-12 22:42:10 -070049config XIP_ROM_SIZE
50 hex
Bin Meng7698d362015-01-06 22:14:16 +080051 depends on X86_RESET_VECTOR
Simon Glassbbd43d62015-01-01 16:17:54 -070052 default ROM_SIZE
Simon Glass70a09c62014-11-12 22:42:10 -070053
54config CPU_ADDR_BITS
55 int
56 default 36
57
Simon Glass65dd74a2014-11-12 22:42:28 -070058config HPET_ADDRESS
59 hex
60 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
61
62config SMM_TSEG
63 bool
64 default n
65
66config SMM_TSEG_SIZE
67 hex
68
Bin Meng8cb20cc2015-01-06 22:14:15 +080069config X86_RESET_VECTOR
70 bool
71 default n
72
73config SYS_X86_START16
74 hex
75 depends on X86_RESET_VECTOR
76 default 0xfffff800
77
Bin Meng64542f42014-12-12 21:05:19 +080078config BOARD_ROMSIZE_KB_512
79 bool
80config BOARD_ROMSIZE_KB_1024
81 bool
82config BOARD_ROMSIZE_KB_2048
83 bool
84config BOARD_ROMSIZE_KB_4096
85 bool
86config BOARD_ROMSIZE_KB_8192
87 bool
88config BOARD_ROMSIZE_KB_16384
89 bool
90
91choice
92 prompt "ROM chip size"
Bin Meng7698d362015-01-06 22:14:16 +080093 depends on X86_RESET_VECTOR
Bin Meng64542f42014-12-12 21:05:19 +080094 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
95 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
96 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
97 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
98 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
99 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
100 help
101 Select the size of the ROM chip you intend to flash U-Boot on.
102
103 The build system will take care of creating a u-boot.rom file
104 of the matching size.
105
106config UBOOT_ROMSIZE_KB_512
107 bool "512 KB"
108 help
109 Choose this option if you have a 512 KB ROM chip.
110
111config UBOOT_ROMSIZE_KB_1024
112 bool "1024 KB (1 MB)"
113 help
114 Choose this option if you have a 1024 KB (1 MB) ROM chip.
115
116config UBOOT_ROMSIZE_KB_2048
117 bool "2048 KB (2 MB)"
118 help
119 Choose this option if you have a 2048 KB (2 MB) ROM chip.
120
121config UBOOT_ROMSIZE_KB_4096
122 bool "4096 KB (4 MB)"
123 help
124 Choose this option if you have a 4096 KB (4 MB) ROM chip.
125
126config UBOOT_ROMSIZE_KB_8192
127 bool "8192 KB (8 MB)"
128 help
129 Choose this option if you have a 8192 KB (8 MB) ROM chip.
130
131config UBOOT_ROMSIZE_KB_16384
132 bool "16384 KB (16 MB)"
133 help
134 Choose this option if you have a 16384 KB (16 MB) ROM chip.
135
136endchoice
137
138# Map the config names to an integer (KB).
139config UBOOT_ROMSIZE_KB
140 int
141 default 512 if UBOOT_ROMSIZE_KB_512
142 default 1024 if UBOOT_ROMSIZE_KB_1024
143 default 2048 if UBOOT_ROMSIZE_KB_2048
144 default 4096 if UBOOT_ROMSIZE_KB_4096
145 default 8192 if UBOOT_ROMSIZE_KB_8192
146 default 16384 if UBOOT_ROMSIZE_KB_16384
147
148# Map the config names to a hex value (bytes).
Simon Glassfce7b272014-11-12 22:42:08 -0700149config ROM_SIZE
150 hex
Bin Meng64542f42014-12-12 21:05:19 +0800151 default 0x80000 if UBOOT_ROMSIZE_KB_512
152 default 0x100000 if UBOOT_ROMSIZE_KB_1024
153 default 0x200000 if UBOOT_ROMSIZE_KB_2048
154 default 0x400000 if UBOOT_ROMSIZE_KB_4096
155 default 0x800000 if UBOOT_ROMSIZE_KB_8192
156 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
157 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
Simon Glassfce7b272014-11-12 22:42:08 -0700158
159config HAVE_INTEL_ME
160 bool "Platform requires Intel Management Engine"
161 help
162 Newer higher-end devices have an Intel Management Engine (ME)
163 which is a very large binary blob (typically 1.5MB) which is
164 required for the platform to work. This enforces a particular
165 SPI flash format. You will need to supply the me.bin file in
166 your board directory.
167
Simon Glass65dd74a2014-11-12 22:42:28 -0700168config X86_RAMTEST
169 bool "Perform a simple RAM test after SDRAM initialisation"
170 help
171 If there is something wrong with SDRAM then the platform will
172 often crash within U-Boot or the kernel. This option enables a
173 very simple RAM test that quickly checks whether the SDRAM seems
174 to work correctly. It is not exhaustive but can save time by
175 detecting obvious failures.
176
Simon Glass22465fc2014-11-14 20:56:30 -0700177config MARK_GRAPHICS_MEM_WRCOMB
Bin Mengd99b9012015-04-27 23:22:26 +0800178 bool "Mark graphics memory as write-combining"
Simon Glass22465fc2014-11-14 20:56:30 -0700179 default n
180 help
Bin Mengd99b9012015-04-27 23:22:26 +0800181 The graphics performance may increase if the graphics
182 memory is set as write-combining cache type. This option
183 enables marking the graphics memory as write-combining.
Simon Glass22465fc2014-11-14 20:56:30 -0700184
185menu "Display"
186
187config FRAMEBUFFER_SET_VESA_MODE
188 prompt "Set framebuffer graphics resolution"
189 bool
190 help
191 Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
192
193choice
194 prompt "framebuffer graphics resolution"
195 default FRAMEBUFFER_VESA_MODE_117
196 depends on FRAMEBUFFER_SET_VESA_MODE
197 help
198 This option sets the resolution used for the coreboot framebuffer (and
199 bootsplash screen).
200
201config FRAMEBUFFER_VESA_MODE_100
202 bool "640x400 256-color"
203
204config FRAMEBUFFER_VESA_MODE_101
205 bool "640x480 256-color"
206
207config FRAMEBUFFER_VESA_MODE_102
208 bool "800x600 16-color"
209
210config FRAMEBUFFER_VESA_MODE_103
211 bool "800x600 256-color"
212
213config FRAMEBUFFER_VESA_MODE_104
214 bool "1024x768 16-color"
215
216config FRAMEBUFFER_VESA_MODE_105
217 bool "1024x7686 256-color"
218
219config FRAMEBUFFER_VESA_MODE_106
220 bool "1280x1024 16-color"
221
222config FRAMEBUFFER_VESA_MODE_107
223 bool "1280x1024 256-color"
224
225config FRAMEBUFFER_VESA_MODE_108
226 bool "80x60 text"
227
228config FRAMEBUFFER_VESA_MODE_109
229 bool "132x25 text"
230
231config FRAMEBUFFER_VESA_MODE_10A
232 bool "132x43 text"
233
234config FRAMEBUFFER_VESA_MODE_10B
235 bool "132x50 text"
236
237config FRAMEBUFFER_VESA_MODE_10C
238 bool "132x60 text"
239
240config FRAMEBUFFER_VESA_MODE_10D
241 bool "320x200 32k-color (1:5:5:5)"
242
243config FRAMEBUFFER_VESA_MODE_10E
244 bool "320x200 64k-color (5:6:5)"
245
246config FRAMEBUFFER_VESA_MODE_10F
247 bool "320x200 16.8M-color (8:8:8)"
248
249config FRAMEBUFFER_VESA_MODE_110
250 bool "640x480 32k-color (1:5:5:5)"
251
252config FRAMEBUFFER_VESA_MODE_111
253 bool "640x480 64k-color (5:6:5)"
254
255config FRAMEBUFFER_VESA_MODE_112
256 bool "640x480 16.8M-color (8:8:8)"
257
258config FRAMEBUFFER_VESA_MODE_113
259 bool "800x600 32k-color (1:5:5:5)"
260
261config FRAMEBUFFER_VESA_MODE_114
262 bool "800x600 64k-color (5:6:5)"
263
264config FRAMEBUFFER_VESA_MODE_115
265 bool "800x600 16.8M-color (8:8:8)"
266
267config FRAMEBUFFER_VESA_MODE_116
268 bool "1024x768 32k-color (1:5:5:5)"
269
270config FRAMEBUFFER_VESA_MODE_117
271 bool "1024x768 64k-color (5:6:5)"
272
273config FRAMEBUFFER_VESA_MODE_118
274 bool "1024x768 16.8M-color (8:8:8)"
275
276config FRAMEBUFFER_VESA_MODE_119
277 bool "1280x1024 32k-color (1:5:5:5)"
278
279config FRAMEBUFFER_VESA_MODE_11A
280 bool "1280x1024 64k-color (5:6:5)"
281
282config FRAMEBUFFER_VESA_MODE_11B
283 bool "1280x1024 16.8M-color (8:8:8)"
284
285config FRAMEBUFFER_VESA_MODE_USER
286 bool "Manually select VESA mode"
287
288endchoice
289
290# Map the config names to an integer (KB).
291config FRAMEBUFFER_VESA_MODE
292 prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
293 hex
294 default 0x100 if FRAMEBUFFER_VESA_MODE_100
295 default 0x101 if FRAMEBUFFER_VESA_MODE_101
296 default 0x102 if FRAMEBUFFER_VESA_MODE_102
297 default 0x103 if FRAMEBUFFER_VESA_MODE_103
298 default 0x104 if FRAMEBUFFER_VESA_MODE_104
299 default 0x105 if FRAMEBUFFER_VESA_MODE_105
300 default 0x106 if FRAMEBUFFER_VESA_MODE_106
301 default 0x107 if FRAMEBUFFER_VESA_MODE_107
302 default 0x108 if FRAMEBUFFER_VESA_MODE_108
303 default 0x109 if FRAMEBUFFER_VESA_MODE_109
304 default 0x10A if FRAMEBUFFER_VESA_MODE_10A
305 default 0x10B if FRAMEBUFFER_VESA_MODE_10B
306 default 0x10C if FRAMEBUFFER_VESA_MODE_10C
307 default 0x10D if FRAMEBUFFER_VESA_MODE_10D
308 default 0x10E if FRAMEBUFFER_VESA_MODE_10E
309 default 0x10F if FRAMEBUFFER_VESA_MODE_10F
310 default 0x110 if FRAMEBUFFER_VESA_MODE_110
311 default 0x111 if FRAMEBUFFER_VESA_MODE_111
312 default 0x112 if FRAMEBUFFER_VESA_MODE_112
313 default 0x113 if FRAMEBUFFER_VESA_MODE_113
314 default 0x114 if FRAMEBUFFER_VESA_MODE_114
315 default 0x115 if FRAMEBUFFER_VESA_MODE_115
316 default 0x116 if FRAMEBUFFER_VESA_MODE_116
317 default 0x117 if FRAMEBUFFER_VESA_MODE_117
318 default 0x118 if FRAMEBUFFER_VESA_MODE_118
319 default 0x119 if FRAMEBUFFER_VESA_MODE_119
320 default 0x11A if FRAMEBUFFER_VESA_MODE_11A
321 default 0x11B if FRAMEBUFFER_VESA_MODE_11B
322 default 0x117 if FRAMEBUFFER_VESA_MODE_USER
323
324endmenu
325
Simon Glass8ce24cd2015-01-27 22:13:41 -0700326config HAVE_FSP
327 bool "Add an Firmware Support Package binary"
328 help
329 Select this option to add an Firmware Support Package binary to
330 the resulting U-Boot image. It is a binary blob which U-Boot uses
331 to set up SDRAM and other chipset specific initialization.
332
333 Note: Without this binary U-Boot will not be able to set up its
334 SDRAM so will not boot.
335
336config FSP_FILE
337 string "Firmware Support Package binary filename"
338 depends on HAVE_FSP
339 default "fsp.bin"
340 help
341 The filename of the file to use as Firmware Support Package binary
342 in the board directory.
343
344config FSP_ADDR
345 hex "Firmware Support Package binary location"
346 depends on HAVE_FSP
347 default 0xfffc0000
348 help
349 FSP is not Position Independent Code (PIC) and the whole FSP has to
350 be rebased if it is placed at a location which is different from the
351 perferred base address specified during the FSP build. Use Intel's
352 Binary Configuration Tool (BCT) to do the rebase.
353
354 The default base address of 0xfffc0000 indicates that the binary must
355 be located at offset 0xc0000 from the beginning of a 1MB flash device.
356
357config FSP_TEMP_RAM_ADDR
358 hex
359 default 0x2000000
360 help
361 Stack top address which is used in FspInit after DRAM is ready and
362 CAR is disabled.
363
Bin Mengf56aeaa2015-02-05 23:42:20 +0800364config TSC_CALIBRATION_BYPASS
365 bool "Bypass Time-Stamp Counter (TSC) calibration"
366 default n
367 help
368 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
369 running frequency via Model-Specific Register (MSR) and Programmable
370 Interval Timer (PIT). If the calibration does not work on your board,
371 select this option and provide a hardcoded TSC running frequency with
372 CONFIG_TSC_FREQ_IN_MHZ below.
373
374 Normally this option should be turned on in a simulation environment
375 like qemu.
376
377config TSC_FREQ_IN_MHZ
378 int "Time-Stamp Counter (TSC) running frequency in MHz"
379 depends on TSC_CALIBRATION_BYPASS
380 default 1000
381 help
382 The running frequency in MHz of Time-Stamp Counter (TSC).
383
Bin Mengb5b6b012015-04-24 18:10:05 +0800384menu "System tables"
385
386config GENERATE_PIRQ_TABLE
387 bool "Generate a PIRQ table"
388 default n
389 help
390 Generate a PIRQ routing table for this board. The PIRQ routing table
391 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
392 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
393 It specifies the interrupt router information as well how all the PCI
394 devices' interrupt pins are wired to PIRQs.
395
Simon Glass6388e352015-04-28 20:25:10 -0600396config GENERATE_SFI_TABLE
397 bool "Generate a SFI (Simple Firmware Interface) table"
398 help
399 The Simple Firmware Interface (SFI) provides a lightweight method
400 for platform firmware to pass information to the operating system
401 via static tables in memory. Kernel SFI support is required to
402 boot on SFI-only platforms. If you have ACPI tables then these are
403 used instead.
404
405 U-Boot writes this table in write_sfi_table() just before booting
406 the OS.
407
408 For more information, see http://simplefirmware.org
409
Bin Mengb5b6b012015-04-24 18:10:05 +0800410endmenu
411
412config MAX_PIRQ_LINKS
413 int
414 default 8
415 help
416 This variable specifies the number of PIRQ interrupt links which are
417 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
418 Some newer chipsets offer more than four links, commonly up to PIRQH.
419
420config IRQ_SLOT_COUNT
421 int
422 default 128
423 help
424 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
425 which in turns forms a table of exact 4KiB. The default value 128
426 should be enough for most boards. If this does not fit your board,
427 change it according to your needs.
428
Simon Glass2d934e52015-01-27 22:13:33 -0700429config PCIE_ECAM_BASE
430 hex
Bin Mengba877ef2015-02-02 21:25:09 +0800431 default 0xe0000000
Simon Glass2d934e52015-01-27 22:13:33 -0700432 help
433 This is the memory-mapped address of PCI configuration space, which
434 is only available through the Enhanced Configuration Access
435 Mechanism (ECAM) with PCI Express. It can be set up almost
436 anywhere. Before it is set up, it is possible to access PCI
437 configuration space through I/O access, but memory access is more
438 convenient. Using this, PCI can be scanned and configured. This
439 should be set to a region that does not conflict with memory
440 assigned to PCI devices - i.e. the memory and prefetch regions, as
441 passed to pci_set_region().
442
Simon Glassee2b2432015-03-02 17:04:37 -0700443config BOOTSTAGE
444 default y
445
446config BOOTSTAGE_REPORT
447 default y
448
449config CMD_BOOTSTAGE
450 default y
451
Masahiro Yamadadd840582014-07-30 14:08:14 +0900452endmenu