Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 644a3cd77e840d1be6a714b8ce284d6ef3ad2f06 / . / arch / riscv / Kconfig
blob: f513f52672bae0ce08ff9385a7db156078cbee0a [file] [log] [blame]
Bin Meng117a4332018-09-26 06:55:06 -0700[diff] [blame]1menu "RISC-V architecture"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]2 depends on RISCV
3
4config SYS_ARCH
5 default "riscv"
6
7choice
8 prompt "Target select"
9 optional
10
Rick Chen6f4dd622018-05-29 09:54:40 +0800[diff] [blame]11config TARGET_AX25_AE350
12 bool "Support ax25-ae350"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]13
Bin Meng510e3792018-09-26 06:55:21 -0700[diff] [blame]14config TARGET_QEMU_VIRT
15 bool "Support QEMU Virt Board"
16
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]17endchoice
18
Rick Chen52923c62018-11-07 09:34:06 +0800[diff] [blame]19# board-specific options below
Rick Chen6f4dd622018-05-29 09:54:40 +0800[diff] [blame]20source "board/AndesTech/ax25-ae350/Kconfig"
Bin Meng510e3792018-09-26 06:55:21 -0700[diff] [blame]21source "board/emulation/qemu-riscv/Kconfig"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]22
Rick Chen52923c62018-11-07 09:34:06 +0800[diff] [blame]23# platform-specific options below
24source "arch/riscv/cpu/ax25/Kconfig"
25
26# architecture-specific options below
27
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]28choice
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]29 prompt "Base ISA"
30 default ARCH_RV32I
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]31
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]32config ARCH_RV32I
33 bool "RV32I"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]34 select 32BIT
35 help
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]36 Choose this option to target the RV32I base integer instruction set.
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]37
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]38config ARCH_RV64I
39 bool "RV64I"
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]40 select 64BIT
Lukas Auer71158562018-11-22 11:26:13 +0100[diff] [blame]41 select PHYS_64BIT
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]42 help
Lukas Auer862e2e72018-11-22 11:26:12 +0100[diff] [blame]43 Choose this option to target the RV64I base integer instruction set.
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]44
45endchoice
46
Lukas Auer8176ea42018-12-12 06:12:23 -0800[diff] [blame]47choice
48 prompt "Code Model"
49 default CMODEL_MEDLOW
50
51config CMODEL_MEDLOW
52 bool "medium low code model"
53 help
54 U-Boot and its statically defined symbols must lie within a single 2 GiB
55 address range and must lie between absolute addresses -2 GiB and +2 GiB.
56
57config CMODEL_MEDANY
58 bool "medium any code model"
59 help
60 U-Boot and its statically defined symbols must be within any single 2 GiB
61 address range.
62
63endchoice
64
Anup Patel3cfc8252018-12-12 06:12:29 -0800[diff] [blame]65choice
66 prompt "Run Mode"
67 default RISCV_MMODE
68
69config RISCV_MMODE
70 bool "Machine"
71 help
72 Choose this option to build U-Boot for RISC-V M-Mode.
73
74config RISCV_SMODE
75 bool "Supervisor"
76 help
77 Choose this option to build U-Boot for RISC-V S-Mode.
78
79endchoice
80
Lukas Auerd57ffa62018-11-22 11:26:14 +0100[diff] [blame]81config RISCV_ISA_C
82 bool "Emit compressed instructions"
83 default y
84 help
85 Adds "C" to the ISA subsets that the toolchain is allowed to emit
86 when building U-Boot, which results in compressed instructions in the
87 U-Boot binary.
88
89config RISCV_ISA_A
90 def_bool y
91
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]92config 32BIT
93 bool
94
95config 64BIT
96 bool
97
Bin Meng644a3cd2018-12-12 06:12:30 -0800[diff] [blame^]98config SIFIVE_CLINT
99 bool
100 depends on RISCV_MMODE
101 select REGMAP
102 select SYSCON
103 help
104 The SiFive CLINT block holds memory-mapped control and status registers
105 associated with software and timer interrupts.
106
Rick Chenf94c44e2017-12-26 13:55:52 +0800[diff] [blame]107endmenu