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Stefan Roesed96f41e2005-11-30 13:06:40 +01001/*
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +02002 * (C) Copyright 2007
3 * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
4 *
Stefan Roesed96f41e2005-11-30 13:06:40 +01005 * (C) Copyright 2005
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
8 * Wolfgang Denk <wd@denx.de>
9 * Copyright 2004 Freescale Semiconductor.
10 * (C) Copyright 2002,2003 Motorola,Inc.
11 * Xianghua Xiao <X.Xiao@motorola.com>
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32/*
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +020033 * TQM85xx (8560/40/55/41/48) board configuration file
Stefan Roesed96f41e2005-11-30 13:06:40 +010034 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/* High Level Configuration Options */
40#define CONFIG_BOOKE 1 /* BOOKE */
41#define CONFIG_E500 1 /* BOOKE e500 family */
42#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
43
Wolfgang Denk2ae18242010-10-06 09:05:45 +020044#if defined(CONFIG_TQM8548_BE)
45#define CONFIG_SYS_TEXT_BASE 0xfff80000
46#else
47#define CONFIG_SYS_TEXT_BASE 0xfffc0000
48#endif
49
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +010050#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
Wolfgang Grandeggerad7ee5d2009-02-11 18:38:21 +010051#define CONFIG_TQM8548
52#endif
53
Stefan Roesed96f41e2005-11-30 13:06:40 +010054#define CONFIG_PCI
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +010055#ifndef CONFIG_TQM8548_AG
Wolfgang Grandeggera3182342009-02-11 18:38:20 +010056#define CONFIG_PCI1 /* PCI/PCI-X controller */
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +010057#endif
Wolfgang Grandeggera3182342009-02-11 18:38:20 +010058#ifdef CONFIG_TQM8548
59#define CONFIG_PCIE1 /* PCI Express interface */
60#endif
61
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +020062#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
63#define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +020064#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +020065
Stefan Roesed96f41e2005-11-30 13:06:40 +010066#define CONFIG_TSEC_ENET /* tsec ethernet support */
67
68#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
69
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +020070 /*
71 * Configuration for big NOR Flashes
72 *
73 * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
74 * Please be aware, that this changes the whole memory map (new CCSRBAR
75 * address, etc). You have to use an adapted Linux kernel or FDT blob
76 * if this option is set.
77 */
78#undef CONFIG_TQM_BIGFLASH
79
Stefan Roesed96f41e2005-11-30 13:06:40 +010080/*
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +020081 * NAND flash support (disabled by default)
82 *
83 * Warning: NAND support will likely increase the U-Boot image size
Wolfgang Denk14d0a022010-10-07 21:51:12 +020084 * to more than 256 KB. Please adjust CONFIG_SYS_TEXT_BASE if necessary.
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +020085 */
Wolfgang Grandeggerad7ee5d2009-02-11 18:38:21 +010086#ifdef CONFIG_TQM8548_BE
87#define CONFIG_NAND
88#endif
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +020089
90/*
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +020091 * MPC8540 and MPC8548 don't have CPM module
Stefan Roesed96f41e2005-11-30 13:06:40 +010092 */
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +020093#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
Stefan Roesed96f41e2005-11-30 13:06:40 +010094#define CONFIG_CPM2 1 /* has CPM2 */
95#endif
96
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +020097#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Kumar Gala4d3521c2008-01-16 09:15:29 -060098
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +010099#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
Wolfgang Grandeggerad7ee5d2009-02-11 18:38:21 +0100100#define CONFIG_CAN_DRIVER /* CAN Driver support */
101#endif
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +0200102
Stefan Roesed96f41e2005-11-30 13:06:40 +0100103/*
104 * sysclk for MPC85xx
105 *
106 * Two valid values are:
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200107 * 33333333
108 * 66666666
Stefan Roesed96f41e2005-11-30 13:06:40 +0100109 *
110 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
111 * is likely the desired value here, so that is now the default.
112 * The board, however, can run at 66MHz. In any event, this value
113 * must match the settings of some switches. Details can be found
114 * in the README.mpc85xxads.
115 */
116
117#ifndef CONFIG_SYS_CLK_FREQ
118#define CONFIG_SYS_CLK_FREQ 33333333
119#endif
120
121/*
122 * These can be toggled for performance analysis, otherwise use default.
123 */
124#define CONFIG_L2_CACHE /* toggle L2 cache */
125#define CONFIG_BTB /* toggle branch predition */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
130#define CONFIG_SYS_MEMTEST_START 0x00000000
131#define CONFIG_SYS_MEMTEST_END 0x10000000
Stefan Roesed96f41e2005-11-30 13:06:40 +0100132
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200133#ifdef CONFIG_TQM_BIGFLASH
Timur Tabie46fedf2011-08-04 18:03:41 -0500134#define CONFIG_SYS_CCSRBAR 0xA0000000
135#else
136#define CONFIG_SYS_CCSRBAR 0xE0000000
137#endif
138#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Stefan Roesed96f41e2005-11-30 13:06:40 +0100139
140/*
141 * DDR Setup
142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
Becky Bruce51f924e2011-07-18 18:49:16 -0500144
Becky Bruce38dba0c2010-12-17 17:17:56 -0600145#if defined(CONFIG_TQM_BIGFLASH) || \
146 (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE))
147#define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G)
Becky Bruce51f924e2011-07-18 18:49:16 -0500148#define CONFIG_SYS_DDR_EARLY_SIZE_MB (512)
149#else
150#define CONFIG_SYS_PPC_DDR_WIMGE (0)
151#define CONFIG_SYS_DDR_EARLY_SIZE_MB (2 * 1024)
Becky Bruce38dba0c2010-12-17 17:17:56 -0600152#endif
Becky Bruce51f924e2011-07-18 18:49:16 -0500153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +0100155#ifdef CONFIG_TQM8548_AG
156#define CONFIG_VERY_BIG_RAM
157#endif
Stefan Roesed96f41e2005-11-30 13:06:40 +0100158
Kumar Gala457caec2008-08-27 01:05:35 -0500159#define CONFIG_NUM_DDR_CONTROLLERS 1
160#define CONFIG_DIMM_SLOTS_PER_CTLR 1
161#define CONFIG_CHIP_SELECTS_PER_CTRL 2
162
Stefan Roesed96f41e2005-11-30 13:06:40 +0100163#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
164/* TQM8540 & 8560 need DLL-override */
Becky Bruce810c4422010-12-17 17:17:58 -0600165#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100166#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200167#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100168
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200169#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
170 defined(CONFIG_TQM8548)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100171#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200172#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100173
174/*
175 * Flash on the Local Bus
176 */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200177#ifdef CONFIG_TQM_BIGFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_FLASH0 0xE0000000
179#define CONFIG_SYS_FLASH1 0xC0000000
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200180#else /* !CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_FLASH0 0xFC000000
182#define CONFIG_SYS_FLASH1 0xF8000000
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200183#endif /* CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
Stefan Roesed96f41e2005-11-30 13:06:40 +0100185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
187#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100188
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200189/* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
190 *
191 * Note: According to timing specifications external addr latch delay
192 * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
193 *
194 * For other Local Bus Clocks see following table:
195 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196 * Clock/MHz CONFIG_SYS_ORx_PRELIM
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200197 * 166 0x.....CA5
198 * 133 0x.....C85
199 * 100 0x.....C65
200 * 83 0x.....FA2
201 * 66 0x.....C82
202 * 50 0x.....C60
203 * 42 0x.....040
204 * 33 0x.....030
205 * 25 0x.....020
206 *
207 */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200208#ifdef CONFIG_TQM_BIGFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_BR0_PRELIM 0xE0001801 /* port size 32bit */
210#define CONFIG_SYS_OR0_PRELIM 0xE0000040 /* 512MB Flash */
211#define CONFIG_SYS_BR1_PRELIM 0xC0001801 /* port size 32bit */
212#define CONFIG_SYS_OR1_PRELIM 0xE0000040 /* 512MB Flash */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200213#else /* !CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_BR0_PRELIM 0xfc001801 /* port size 32bit */
215#define CONFIG_SYS_OR0_PRELIM 0xfc000040 /* 64MB Flash */
216#define CONFIG_SYS_BR1_PRELIM 0xf8001801 /* port size 32bit */
217#define CONFIG_SYS_OR1_PRELIM 0xfc000040 /* 64MB Flash */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200218#endif /* CONFIG_TQM_BIGFLASH */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200221#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
223#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
224#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
227#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
228#undef CONFIG_SYS_FLASH_CHECKSUM
229#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
230#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100231
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200232#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100233
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200234/*
235 * Note: when changing the Local Bus clock divider you have to
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236 * change the timing values in CONFIG_SYS_ORx_PRELIM.
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200237 *
238 * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
239 * LCRR[16:17] EADC : External address delay cycles. It should be set to 2
240 * for Local Bus Clock > 83.3 MHz.
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_LBC_LCRR 0x00030008 /* LB clock ratio reg */
243#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
244#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
245#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
Stefan Roesed96f41e2005-11-30 13:06:40 +0100246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_INIT_RAM_LOCK 1
248#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_CCSRBAR \
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200249 + 0x04010000) /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200250#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100251
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200252#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roesed96f41e2005-11-30 13:06:40 +0100254
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200255#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)/* Reserved for Monitor */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_MALLOC_LEN (384 * 1024) /* Reserved for malloc */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100257
258/* Serial Port */
259#if defined(CONFIG_TQM8560)
260
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200261#define CONFIG_CONS_ON_SCC /* define if console on SCC */
262#undef CONFIG_CONS_NONE /* define if console on something else */
263#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100264
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200265#else /* !CONFIG_TQM8560 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100266
267#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_NS16550
269#define CONFIG_SYS_NS16550_SERIAL
270#define CONFIG_SYS_NS16550_REG_SIZE 1
271#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
274#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100275
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200276/* PS/2 Keyboard */
277#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
278#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
279#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200281#define CONFIG_BOARD_EARLY_INIT_R 1
282
Wolfgang Denk966083e2006-07-21 15:24:56 +0200283#endif /* CONFIG_TQM8560 */
284
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200285#define CONFIG_BAUDRATE 115200
Wolfgang Denk966083e2006-07-21 15:24:56 +0200286
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_BAUDRATE_TABLE \
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200288 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Wolfgang Denk966083e2006-07-21 15:24:56 +0200289
Wolfgang Denk2751a952006-10-28 02:29:14 +0200290#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips5be58f52010-07-14 19:47:18 -0500291#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100293
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200294/* pass open firmware flat tree */
295#define CONFIG_OF_LIBFDT 1
296#define CONFIG_OF_BOARD_SETUP 1
297#define CONFIG_OF_STDOUT_VIA_ALIAS 1
298
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +0200299/* CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_CAN_BASE (CONFIG_SYS_CCSRBAR \
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200301 + 0x03000000) /* CAN base address */
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200302#ifdef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */
304#define CONFIG_SYS_OR2_CAN (CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
305#define CONFIG_SYS_BR2_CAN ((CONFIG_SYS_CAN_BASE & BR_BA) | \
Wolfgang Grandeggerd9ee8432008-06-05 13:12:05 +0200306 BR_PS_8 | BR_MS_UPMC | BR_V)
307#endif /* CONFIG_CAN_DRIVER */
308
Jon Loeliger20476722006-10-20 15:50:15 -0500309/*
310 * I2C
311 */
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200312#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100313#define CONFIG_HARD_I2C /* I2C with hardware support */
314#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
316#define CONFIG_SYS_I2C_SLAVE 0x7F
317#define CONFIG_SYS_I2C_NOPROBES {0x48} /* Don't probe these addrs */
318#define CONFIG_SYS_I2C_OFFSET 0x3000
Stefan Roesed96f41e2005-11-30 13:06:40 +0100319
320/* I2C RTC */
321#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100323
324/* I2C EEPROM */
325/*
326 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
327 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
329#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
330#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
331#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
332#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100333
334/* I2C SYSMON (LM75) */
335#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
336#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_DTT_MAX_TEMP 70
338#define CONFIG_SYS_DTT_LOW_TEMP -30
339#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roesed96f41e2005-11-30 13:06:40 +0100340
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200341#ifndef CONFIG_PCIE1
Stefan Roesed96f41e2005-11-30 13:06:40 +0100342/* RapidIO MMU */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200343#ifdef CONFIG_TQM_BIGFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_RIO_MEM_BASE 0xb0000000 /* base address */
345#define CONFIG_SYS_RIO_MEM_SIZE 0x10000000 /* 256M */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200346#else /* !CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */
348#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200349#endif /* CONFIG_TQM_BIGFLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200351#endif /* CONFIG_PCIE1 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100352
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200353/* NAND FLASH */
354#ifdef CONFIG_NAND
355
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200356#define CONFIG_NAND_FSL_UPM 1
357
358#define CONFIG_MTD_NAND_ECC_JFFS2 1 /* use JFFS2 ECC */
359
360/* address distance between chip selects */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_NAND_SELECT_DEVICE 1
362#define CONFIG_SYS_NAND_CS_DIST 0x200
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200363
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_NAND_SIZE 0x8000
Wolfgang Grandegger16f2f5a2009-02-11 18:38:24 +0100365#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_CCSRBAR + 0x03010000)
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200366
Wolfgang Grandegger16f2f5a2009-02-11 18:38:24 +0100367#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
368#define CONFIG_SYS_NAND_MAX_CHIPS 2 /* Number of chips per device */
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200369
370/* CS3 for NAND Flash */
Wolfgang Grandegger16f2f5a2009-02-11 18:38:24 +0100371#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_NAND_BASE & BR_BA) | \
372 BR_PS_8 | BR_MS_UPMB | BR_V)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200374
Wolfgang Grandegger16f2f5a2009-02-11 18:38:24 +0100375#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200376
377#endif /* CONFIG_NAND */
378
Stefan Roesed96f41e2005-11-30 13:06:40 +0100379/*
380 * General PCI
381 * Addresses are mapped 1-1.
382 */
Peter Tyser06412752010-09-29 13:37:28 -0500383#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
384#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Peter Tyser06412752010-09-29 13:37:28 -0500386#define CONFIG_SYS_PCI1_IO_BUS (CONFIG_SYS_CCSRBAR + 0x02000000)
387#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100389
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200390#ifdef CONFIG_PCIE1
391/*
392 * General PCI express
393 * Addresses are mapped 1-1.
394 */
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200395#ifdef CONFIG_TQM_BIGFLASH
Peter Tyser06412752010-09-29 13:37:28 -0500396#define CONFIG_SYS_PCIE1_MEM_BUS 0xb0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 512M */
Peter Tyser06412752010-09-29 13:37:28 -0500398#define CONFIG_SYS_PCIE1_IO_BUS 0xaf000000
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200399#else /* !CONFIG_TQM_BIGFLASH */
Peter Tyser06412752010-09-29 13:37:28 -0500400#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Peter Tyser06412752010-09-29 13:37:28 -0500402#define CONFIG_SYS_PCIE1_IO_BUS 0xef000000
Wolfgang Grandeggere8cc3f02008-06-05 13:12:10 +0200403#endif /* CONFIG_TQM_BIGFLASH */
Peter Tyser06412752010-09-29 13:37:28 -0500404#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
405#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */
Wolfgang Grandeggerb9e80782008-06-05 13:12:08 +0200407#endif /* CONFIG_PCIE1 */
408
Stefan Roesed96f41e2005-11-30 13:06:40 +0100409#if defined(CONFIG_PCI)
410
411#define CONFIG_PCI_PNP /* do pci plug-and-play */
412
413#define CONFIG_EEPRO100
414#undef CONFIG_TULIP
415
416#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200417#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100418
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200419#endif /* CONFIG_PCI */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100420
Stefan Roesed96f41e2005-11-30 13:06:40 +0100421
422#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500423#define CONFIG_TSEC1 1
424#define CONFIG_TSEC1_NAME "TSEC0"
425#define CONFIG_TSEC2 1
426#define CONFIG_TSEC2_NAME "TSEC1"
Stefan Roesed96f41e2005-11-30 13:06:40 +0100427#define TSEC1_PHY_ADDR 2
428#define TSEC2_PHY_ADDR 1
429#define TSEC1_PHYIDX 0
430#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500431#define TSEC1_FLAGS TSEC_GIGABIT
432#define TSEC2_FLAGS TSEC_GIGABIT
Stefan Roesed96f41e2005-11-30 13:06:40 +0100433#define FEC_PHY_ADDR 3
434#define FEC_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500435#define FEC_FLAGS 0
Andy Fleming10327dc2007-08-16 16:35:02 -0500436#define CONFIG_HAS_ETH0
Stefan Roesed96f41e2005-11-30 13:06:40 +0100437#define CONFIG_HAS_ETH1
438#define CONFIG_HAS_ETH2
439
Wolfgang Grandegger1287e0c2008-06-05 13:12:07 +0200440#ifdef CONFIG_TQM8548
441/*
442 * TQM8548 has 4 ethernet ports. 4 ETSEC's.
443 *
444 * On the STK85xx Starterkit the ETSEC3/4 ports are on an
445 * additional adapter (AIO) between module and Starterkit.
446 */
447#define CONFIG_TSEC3 1
448#define CONFIG_TSEC3_NAME "TSEC2"
449#define CONFIG_TSEC4 1
450#define CONFIG_TSEC4_NAME "TSEC3"
451#define TSEC3_PHY_ADDR 4
452#define TSEC4_PHY_ADDR 5
453#define TSEC3_PHYIDX 0
454#define TSEC4_PHYIDX 0
455#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
456#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
457#define CONFIG_HAS_ETH3
458#define CONFIG_HAS_ETH4
459#endif /* CONFIG_TQM8548 */
460
Stefan Roesed96f41e2005-11-30 13:06:40 +0100461/* Options are TSEC[0-1], FEC */
462#define CONFIG_ETHPRIME "TSEC0"
463
464#if defined(CONFIG_TQM8540)
465/*
466 * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
467 * The FEC port is connected on the same signals as the FCC3 port
468 * of the TQM8560 to the baseboard (STK85xx Starterkit).
469 *
470 * On the STK85xx Starterkit the X47/X50 jumper has to be set to
471 * a - d (X50.2 - 3) to enable the FEC port.
472 */
473#define CONFIG_MPC85XX_FEC 1
474#define CONFIG_MPC85XX_FEC_NAME "FEC"
475#endif
476
477#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
478/*
479 * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
480 * can be used at once, since only one FCC port is available on the STK85xx
481 * Starterkit.
482 *
483 * To use this port you have to configure U-Boot to use the FCC port 1...2
484 * and set the X47/X50 jumper to:
485 * FCC1: a - b (X47.2 - X50.2)
486 * FCC2: a - c (X50.2 - 1)
487 */
488#define CONFIG_ETHER_ON_FCC
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200489#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100490#endif
491
492#if defined(CONFIG_TQM8560)
493/*
494 * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
495 * can be used at once, since only one FCC port is available on the STK85xx
496 * Starterkit.
497 *
498 * To use this port you have to configure U-Boot to use the FCC port 1...3
499 * and set the X47/X50 jumper to:
500 * FCC1: a - b (X47.2 - X50.2)
501 * FCC2: a - c (X50.2 - 1)
502 * FCC3: a - d (X50.2 - 3)
503 */
504#define CONFIG_ETHER_ON_FCC
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200505#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100506#endif
507
508#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
509#define CONFIG_ETHER_ON_FCC1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200511 CMXFCR_TF1CS_MSK)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
513#define CONFIG_SYS_CPMFCR_RAMTYPE 0
514#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100515#endif
516
517#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
518#define CONFIG_ETHER_ON_FCC2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200519#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200520 CMXFCR_TF2CS_MSK)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
522#define CONFIG_SYS_CPMFCR_RAMTYPE 0
523#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100524#endif
525
526#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
527#define CONFIG_ETHER_ON_FCC3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200528#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200529 CMXFCR_TF3CS_MSK)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200530#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
531#define CONFIG_SYS_CPMFCR_RAMTYPE 0
532#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100533#endif
534
535/*
536 * Environment
537 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200538#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Grandegger46346f22008-06-05 13:12:02 +0200539
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200540#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200542#define CONFIG_ENV_SIZE 0x2000
543#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
544#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100545
546#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200547#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100548
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200549#define CONFIG_TIMESTAMP /* Print image info with ts */
Jon Loeliger2835e512007-06-13 13:22:08 -0500550
551/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500552 * BOOTP options
553 */
554#define CONFIG_BOOTP_BOOTFILESIZE
555#define CONFIG_BOOTP_BOOTPATH
556#define CONFIG_BOOTP_GATEWAY
557#define CONFIG_BOOTP_HOSTNAME
558
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200559#ifdef CONFIG_NAND
560/*
561 * Use NAND-FLash as JFFS2 device
562 */
563#define CONFIG_CMD_NAND
564#define CONFIG_CMD_JFFS2
565
566#define CONFIG_JFFS2_NAND 1
567
Stefan Roese68d7d652009-03-19 13:30:36 +0100568#ifdef CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200569#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
570#define CONFIG_FLASH_CFI_MTD
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200571#define MTDIDS_DEFAULT "nand0=TQM85xx-nand"
572#define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-"
573#else
574#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */
575#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
576#define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */
Stefan Roese68d7d652009-03-19 13:30:36 +0100577#endif /* CONFIG_CMD_MTDPARTS */
Wolfgang Grandegger1c2deff2008-06-05 13:12:09 +0200578
579#endif /* CONFIG_NAND */
580
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500581/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500582 * Command line configuration.
583 */
584#include <config_cmd_default.h>
585
586#define CONFIG_CMD_PING
587#define CONFIG_CMD_I2C
588#define CONFIG_CMD_DHCP
589#define CONFIG_CMD_NFS
590#define CONFIG_CMD_SNTP
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +0100591#ifndef CONFIG_TQM8548_AG
Jon Loeliger2835e512007-06-13 13:22:08 -0500592#define CONFIG_CMD_DATE
Wolfgang Grandeggera865bcd2009-02-11 18:38:22 +0100593#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500594#define CONFIG_CMD_EEPROM
595#define CONFIG_CMD_DTT
596#define CONFIG_CMD_MII
Becky Bruce199e2622010-06-17 11:37:25 -0500597#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500598
Stefan Roesed96f41e2005-11-30 13:06:40 +0100599#if defined(CONFIG_PCI)
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200600#define CONFIG_CMD_PCI
Stefan Roesed96f41e2005-11-30 13:06:40 +0100601#endif
602
Stefan Roesed96f41e2005-11-30 13:06:40 +0100603#undef CONFIG_WATCHDOG /* watchdog disabled */
604
605/*
606 * Miscellaneous configurable options
607 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200608#define CONFIG_SYS_LONGHELP /* undef to save memory */
609#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
610#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100611
Jon Loeliger2835e512007-06-13 13:22:08 -0500612#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200613#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100614#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200615#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100616#endif
617
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
619 sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buf Size */
620#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
621#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
622#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100623
624/*
625 * For booting Linux, the board info and command line data
626 * have to be in the first 8 MB of memory, since this is
627 * the maximum mapped by the Linux kernel during initialization.
628 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200629#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100630
Jon Loeliger2835e512007-06-13 13:22:08 -0500631#if defined(CONFIG_CMD_KGDB)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100632#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
633#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
634#endif
635
Stefan Roesed96f41e2005-11-30 13:06:40 +0100636#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
637
638#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
639
640#define CONFIG_PREBOOT "echo;" \
Wolfgang Denkd8519dc2006-08-11 17:33:42 +0200641 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100642 "echo"
643
644#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
645
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200646
647/*
648 * Setup some board specific values for the default environment variables
649 */
650#ifdef CONFIG_CPM2
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200651#define CONFIG_ENV_CONSDEV "consdev=ttyCPM0\0"
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200652#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200653#define CONFIG_ENV_CONSDEV "consdev=ttyS0\0"
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200654#endif
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200655#define CONFIG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200656 MK_STR(CONFIG_HOSTNAME)".dtb\0"
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200657#define CONFIG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
658#define CONFIG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200659 "uboot_addr="MK_STR(CONFIG_SYS_TEXT_BASE)"\0"
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200660
Stefan Roesed96f41e2005-11-30 13:06:40 +0100661#define CONFIG_EXTRA_ENV_SETTINGS \
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200662 CONFIG_ENV_BOOTFILE \
663 CONFIG_ENV_FDT_FILE \
Wolfgang Denk7a2063b2009-05-15 00:16:02 +0200664 CONFIG_ENV_CONSDEV \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100665 "netdev=eth0\0" \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100666 "nfsargs=setenv bootargs root=/dev/nfs rw " \
667 "nfsroot=$serverip:$rootpath\0" \
668 "ramargs=setenv bootargs root=/dev/ram rw\0" \
669 "addip=setenv bootargs $bootargs " \
670 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
671 ":$hostname:$netdev:off panic=1\0" \
672 "addcons=setenv bootargs $bootargs " \
673 "console=$consdev,$baudrate\0" \
674 "flash_nfs=run nfsargs addip addcons;" \
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200675 "bootm $kernel_addr - $fdt_addr\0" \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100676 "flash_self=run ramargs addip addcons;" \
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200677 "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \
678 "net_nfs=tftp $kernel_addr_r $bootfile;" \
679 "tftp $fdt_addr_r $fdt_file;" \
680 "run nfsargs addip addcons;" \
681 "bootm $kernel_addr_r - $fdt_addr_r\0" \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100682 "rootpath=/opt/eldk/ppc_85xx\0" \
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200683 "fdt_addr_r=900000\0" \
684 "kernel_addr_r=1000000\0" \
685 "fdt_addr=ffec0000\0" \
686 "kernel_addr=ffd00000\0" \
687 "ramdisk_addr=ff800000\0" \
Wolfgang Denk7a2063b2009-05-15 00:16:02 +0200688 CONFIG_ENV_UBOOT \
Wolfgang Grandegger25991352008-06-05 13:12:06 +0200689 "load=tftp 100000 $uboot\0" \
690 "update=protect off $uboot_addr +$filesize;" \
691 "erase $uboot_addr +$filesize;" \
Wolfgang Denk7a2063b2009-05-15 00:16:02 +0200692 "cp.b 100000 $uboot_addr $filesize" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100693 "upd=run load update\0" \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100694 ""
695#define CONFIG_BOOTCOMMAND "run flash_self"
696
Wolfgang Grandeggerb99ba162008-06-05 13:12:00 +0200697#endif /* __CONFIG_H */