Simon Glass | 6710b5b | 2012-02-27 10:52:39 +0000 | [diff] [blame] | 1 | /dts-v1/; |
| 2 | |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 3 | #include <dt-bindings/input/input.h> |
Tom Warren | 6c5be64 | 2013-02-21 12:31:27 +0000 | [diff] [blame] | 4 | #include "tegra20.dtsi" |
Simon Glass | 6710b5b | 2012-02-27 10:52:39 +0000 | [diff] [blame] | 5 | |
| 6 | / { |
| 7 | model = "NVIDIA Seaboard"; |
| 8 | compatible = "nvidia,seaboard", "nvidia,tegra20"; |
| 9 | |
Simon Glass | 1920172 | 2012-02-27 10:52:46 +0000 | [diff] [blame] | 10 | aliases { |
Tom Warren | 126685a | 2013-02-21 12:31:29 +0000 | [diff] [blame] | 11 | /* This defines the order of our ports */ |
Simon Glass | 1920172 | 2012-02-27 10:52:46 +0000 | [diff] [blame] | 12 | usb0 = "/usb@c5008000"; |
| 13 | usb1 = "/usb@c5000000"; |
Simon Glass | 3682cc3 | 2012-02-29 07:31:27 +0000 | [diff] [blame] | 14 | i2c0 = "/i2c@7000d000"; |
| 15 | i2c1 = "/i2c@7000c000"; |
| 16 | i2c2 = "/i2c@7000c400"; |
| 17 | i2c3 = "/i2c@7000c500"; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 18 | rtc0 = "/i2c@7000d000/tps6586x@34"; |
| 19 | rtc1 = "/rtc@7000e000"; |
| 20 | serial0 = &uartd; |
Stephen Warren | 67748a7 | 2016-09-13 10:45:43 -0600 | [diff] [blame^] | 21 | mmc0 = "/sdhci@c8000600"; |
| 22 | mmc1 = "/sdhci@c8000400"; |
Simon Glass | 1920172 | 2012-02-27 10:52:46 +0000 | [diff] [blame] | 23 | }; |
| 24 | |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 25 | chosen { |
| 26 | bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; |
| 27 | }; |
| 28 | |
| 29 | chosen { |
| 30 | stdout-path = &uartd; |
| 31 | }; |
| 32 | |
Simon Glass | 6710b5b | 2012-02-27 10:52:39 +0000 | [diff] [blame] | 33 | memory { |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 34 | reg = <0x00000000 0x40000000>; |
Simon Glass | 6710b5b | 2012-02-27 10:52:39 +0000 | [diff] [blame] | 35 | }; |
| 36 | |
Simon Glass | ee7d755 | 2016-01-30 16:37:52 -0700 | [diff] [blame] | 37 | host1x@50000000 { |
Allen Martin | 36068ae | 2013-01-25 08:46:47 +0000 | [diff] [blame] | 38 | status = "okay"; |
| 39 | dc@54200000 { |
| 40 | status = "okay"; |
| 41 | rgb { |
| 42 | status = "okay"; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 43 | |
| 44 | nvidia,panel = <&panel>; |
Simon Glass | ec55077 | 2016-05-08 16:55:20 -0600 | [diff] [blame] | 45 | |
| 46 | display-timings { |
| 47 | timing@0 { |
| 48 | /* Seaboard has 1366x768 */ |
| 49 | clock-frequency = <70600000>; |
| 50 | hactive = <1366>; |
| 51 | vactive = <768>; |
| 52 | hback-porch = <58>; |
| 53 | hfront-porch = <58>; |
| 54 | hsync-len = <58>; |
| 55 | vback-porch = <4>; |
| 56 | vfront-porch = <4>; |
| 57 | vsync-len = <4>; |
| 58 | hsync-active = <1>; |
| 59 | }; |
| 60 | }; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 61 | }; |
| 62 | }; |
| 63 | |
| 64 | hdmi@54280000 { |
| 65 | status = "okay"; |
| 66 | |
| 67 | vdd-supply = <&hdmi_vdd_reg>; |
| 68 | pll-supply = <&hdmi_pll_reg>; |
| 69 | hdmi-supply = <&vdd_hdmi>; |
| 70 | |
| 71 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| 72 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
| 73 | GPIO_ACTIVE_HIGH>; |
| 74 | }; |
| 75 | }; |
| 76 | |
| 77 | pinmux@70000014 { |
| 78 | pinctrl-names = "default"; |
| 79 | pinctrl-0 = <&state_default>; |
| 80 | |
| 81 | state_default: pinmux { |
| 82 | ata { |
| 83 | nvidia,pins = "ata"; |
| 84 | nvidia,function = "ide"; |
| 85 | }; |
| 86 | atb { |
| 87 | nvidia,pins = "atb", "gma", "gme"; |
| 88 | nvidia,function = "sdio4"; |
| 89 | }; |
| 90 | atc { |
| 91 | nvidia,pins = "atc"; |
| 92 | nvidia,function = "nand"; |
| 93 | }; |
| 94 | atd { |
| 95 | nvidia,pins = "atd", "ate", "gmb", "spia", |
| 96 | "spib", "spic"; |
| 97 | nvidia,function = "gmi"; |
| 98 | }; |
| 99 | cdev1 { |
| 100 | nvidia,pins = "cdev1"; |
| 101 | nvidia,function = "plla_out"; |
| 102 | }; |
| 103 | cdev2 { |
| 104 | nvidia,pins = "cdev2"; |
| 105 | nvidia,function = "pllp_out4"; |
| 106 | }; |
| 107 | crtp { |
| 108 | nvidia,pins = "crtp", "lm1"; |
| 109 | nvidia,function = "crt"; |
| 110 | }; |
| 111 | csus { |
| 112 | nvidia,pins = "csus"; |
| 113 | nvidia,function = "vi_sensor_clk"; |
| 114 | }; |
| 115 | dap1 { |
| 116 | nvidia,pins = "dap1"; |
| 117 | nvidia,function = "dap1"; |
| 118 | }; |
| 119 | dap2 { |
| 120 | nvidia,pins = "dap2"; |
| 121 | nvidia,function = "dap2"; |
| 122 | }; |
| 123 | dap3 { |
| 124 | nvidia,pins = "dap3"; |
| 125 | nvidia,function = "dap3"; |
| 126 | }; |
| 127 | dap4 { |
| 128 | nvidia,pins = "dap4"; |
| 129 | nvidia,function = "dap4"; |
| 130 | }; |
| 131 | dta { |
| 132 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; |
| 133 | nvidia,function = "vi"; |
| 134 | }; |
| 135 | dtf { |
| 136 | nvidia,pins = "dtf"; |
| 137 | nvidia,function = "i2c3"; |
| 138 | }; |
| 139 | gmc { |
| 140 | nvidia,pins = "gmc"; |
| 141 | nvidia,function = "uartd"; |
| 142 | }; |
| 143 | gmd { |
| 144 | nvidia,pins = "gmd"; |
| 145 | nvidia,function = "sflash"; |
| 146 | }; |
| 147 | gpu { |
| 148 | nvidia,pins = "gpu"; |
| 149 | nvidia,function = "pwm"; |
| 150 | }; |
| 151 | gpu7 { |
| 152 | nvidia,pins = "gpu7"; |
| 153 | nvidia,function = "rtck"; |
| 154 | }; |
| 155 | gpv { |
| 156 | nvidia,pins = "gpv", "slxa", "slxk"; |
| 157 | nvidia,function = "pcie"; |
| 158 | }; |
| 159 | hdint { |
| 160 | nvidia,pins = "hdint", "lpw0", "lpw2", "lsc1", |
| 161 | "lsck", "lsda"; |
| 162 | nvidia,function = "hdmi"; |
| 163 | }; |
| 164 | i2cp { |
| 165 | nvidia,pins = "i2cp"; |
| 166 | nvidia,function = "i2cp"; |
| 167 | }; |
| 168 | irrx { |
| 169 | nvidia,pins = "irrx", "irtx"; |
| 170 | nvidia,function = "uartb"; |
| 171 | }; |
| 172 | kbca { |
| 173 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 174 | "kbce", "kbcf"; |
| 175 | nvidia,function = "kbc"; |
| 176 | }; |
| 177 | lcsn { |
| 178 | nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", |
| 179 | "lsdi", "lvp0"; |
| 180 | nvidia,function = "rsvd4"; |
| 181 | }; |
| 182 | ld0 { |
| 183 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 184 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 185 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 186 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 187 | "lhp1", "lhp2", "lhs", "lpp", "lsc0", |
| 188 | "lspi", "lvp1", "lvs"; |
| 189 | nvidia,function = "displaya"; |
| 190 | }; |
| 191 | owc { |
| 192 | nvidia,pins = "owc", "spdi", "spdo", "uac"; |
| 193 | nvidia,function = "rsvd2"; |
| 194 | }; |
| 195 | pmc { |
| 196 | nvidia,pins = "pmc"; |
| 197 | nvidia,function = "pwr_on"; |
| 198 | }; |
| 199 | rm { |
| 200 | nvidia,pins = "rm"; |
| 201 | nvidia,function = "i2c1"; |
| 202 | }; |
| 203 | sdb { |
| 204 | nvidia,pins = "sdb", "sdc", "sdd"; |
| 205 | nvidia,function = "sdio3"; |
| 206 | }; |
| 207 | sdio1 { |
| 208 | nvidia,pins = "sdio1"; |
| 209 | nvidia,function = "sdio1"; |
| 210 | }; |
| 211 | slxc { |
| 212 | nvidia,pins = "slxc", "slxd"; |
| 213 | nvidia,function = "spdif"; |
| 214 | }; |
| 215 | spid { |
| 216 | nvidia,pins = "spid", "spie", "spif"; |
| 217 | nvidia,function = "spi1"; |
| 218 | }; |
| 219 | spig { |
| 220 | nvidia,pins = "spig", "spih"; |
| 221 | nvidia,function = "spi2_alt"; |
| 222 | }; |
| 223 | uaa { |
| 224 | nvidia,pins = "uaa", "uab", "uda"; |
| 225 | nvidia,function = "ulpi"; |
| 226 | }; |
| 227 | uad { |
| 228 | nvidia,pins = "uad"; |
| 229 | nvidia,function = "irda"; |
| 230 | }; |
| 231 | uca { |
| 232 | nvidia,pins = "uca", "ucb"; |
| 233 | nvidia,function = "uartc"; |
| 234 | }; |
| 235 | conf_ata { |
| 236 | nvidia,pins = "ata", "atb", "atc", "atd", |
| 237 | "cdev1", "cdev2", "dap1", "dap2", |
| 238 | "dap4", "ddc", "dtf", "gma", "gmc", "gmd", |
| 239 | "gme", "gpu", "gpu7", "i2cp", "irrx", |
| 240 | "irtx", "pta", "rm", "sdc", "sdd", |
| 241 | "slxd", "slxk", "spdi", "spdo", "uac", |
| 242 | "uad", "uca", "ucb", "uda"; |
| 243 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 244 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 245 | }; |
| 246 | conf_ate { |
| 247 | nvidia,pins = "ate", "csus", "dap3", |
| 248 | "gpv", "owc", "slxc", "spib", "spid", |
| 249 | "spie"; |
| 250 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 251 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 252 | }; |
| 253 | conf_ck32 { |
| 254 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", |
| 255 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; |
| 256 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| 257 | }; |
| 258 | conf_crtp { |
| 259 | nvidia,pins = "crtp", "gmb", "slxa", "spia", |
| 260 | "spig", "spih"; |
| 261 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 262 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 263 | }; |
| 264 | conf_dta { |
| 265 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; |
| 266 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 267 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 268 | }; |
| 269 | conf_dte { |
| 270 | nvidia,pins = "dte", "spif"; |
| 271 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 272 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 273 | }; |
| 274 | conf_hdint { |
| 275 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", |
| 276 | "lpw1", "lsc1", "lsck", "lsda", "lsdi", |
| 277 | "lvp0"; |
| 278 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| 279 | }; |
| 280 | conf_kbca { |
| 281 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", |
| 282 | "kbce", "kbcf", "sdio1", "spic", "uaa", |
| 283 | "uab"; |
| 284 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 285 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 286 | }; |
| 287 | conf_lc { |
| 288 | nvidia,pins = "lc", "ls"; |
| 289 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| 290 | }; |
| 291 | conf_ld0 { |
| 292 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", |
| 293 | "ld5", "ld6", "ld7", "ld8", "ld9", |
| 294 | "ld10", "ld11", "ld12", "ld13", "ld14", |
| 295 | "ld15", "ld16", "ld17", "ldi", "lhp0", |
| 296 | "lhp1", "lhp2", "lhs", "lm0", "lpp", |
| 297 | "lpw0", "lpw2", "lsc0", "lspi", "lvp1", |
| 298 | "lvs", "pmc", "sdb"; |
| 299 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| 300 | }; |
| 301 | conf_ld17_0 { |
| 302 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", |
| 303 | "ld23_22"; |
| 304 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| 305 | }; |
| 306 | drive_sdio1 { |
| 307 | nvidia,pins = "drive_sdio1"; |
| 308 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
| 309 | nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| 310 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
| 311 | nvidia,pull-down-strength = <31>; |
| 312 | nvidia,pull-up-strength = <31>; |
| 313 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 314 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
| 315 | }; |
| 316 | }; |
| 317 | |
| 318 | state_i2cmux_ddc: pinmux_i2cmux_ddc { |
| 319 | ddc { |
| 320 | nvidia,pins = "ddc"; |
| 321 | nvidia,function = "i2c2"; |
| 322 | }; |
| 323 | pta { |
| 324 | nvidia,pins = "pta"; |
| 325 | nvidia,function = "rsvd4"; |
| 326 | }; |
| 327 | }; |
| 328 | |
| 329 | state_i2cmux_pta: pinmux_i2cmux_pta { |
| 330 | ddc { |
| 331 | nvidia,pins = "ddc"; |
| 332 | nvidia,function = "rsvd4"; |
| 333 | }; |
| 334 | pta { |
| 335 | nvidia,pins = "pta"; |
| 336 | nvidia,function = "i2c2"; |
| 337 | }; |
| 338 | }; |
| 339 | |
| 340 | state_i2cmux_idle: pinmux_i2cmux_idle { |
| 341 | ddc { |
| 342 | nvidia,pins = "ddc"; |
| 343 | nvidia,function = "rsvd4"; |
| 344 | }; |
| 345 | pta { |
| 346 | nvidia,pins = "pta"; |
| 347 | nvidia,function = "rsvd4"; |
Allen Martin | 36068ae | 2013-01-25 08:46:47 +0000 | [diff] [blame] | 348 | }; |
| 349 | }; |
| 350 | }; |
| 351 | |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 352 | i2s@70002800 { |
Simon Glass | ee7d755 | 2016-01-30 16:37:52 -0700 | [diff] [blame] | 353 | status = "okay"; |
Simon Glass | cd474cb | 2012-02-28 08:07:49 +0000 | [diff] [blame] | 354 | }; |
| 355 | |
Simon Glass | 6710b5b | 2012-02-27 10:52:39 +0000 | [diff] [blame] | 356 | serial@70006300 { |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 357 | status = "okay"; |
Simon Glass | 6710b5b | 2012-02-27 10:52:39 +0000 | [diff] [blame] | 358 | clock-frequency = < 216000000 >; |
| 359 | }; |
| 360 | |
Allen Martin | b7723f3 | 2013-01-16 13:12:24 +0000 | [diff] [blame] | 361 | nand-controller@70008000 { |
Simon Glass | 2b2b50b | 2015-01-05 20:05:41 -0700 | [diff] [blame] | 362 | nvidia,wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; |
Allen Martin | b7723f3 | 2013-01-16 13:12:24 +0000 | [diff] [blame] | 363 | nvidia,width = <8>; |
| 364 | nvidia,timing = <26 100 20 80 20 10 12 10 70>; |
| 365 | nand@0 { |
| 366 | reg = <0>; |
| 367 | compatible = "hynix,hy27uf4g2b", "nand-flash"; |
| 368 | }; |
Simon Glass | 6710b5b | 2012-02-27 10:52:39 +0000 | [diff] [blame] | 369 | }; |
Simon Glass | 3682cc3 | 2012-02-29 07:31:27 +0000 | [diff] [blame] | 370 | |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 371 | pwm: pwm@7000a000 { |
| 372 | status = "okay"; |
| 373 | }; |
| 374 | |
Simon Glass | 3682cc3 | 2012-02-29 07:31:27 +0000 | [diff] [blame] | 375 | i2c@7000c000 { |
Simon Glass | ee7d755 | 2016-01-30 16:37:52 -0700 | [diff] [blame] | 376 | status = "okay"; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 377 | clock-frequency = <400000>; |
| 378 | |
| 379 | wm8903: wm8903@1a { |
| 380 | compatible = "wlf,wm8903"; |
| 381 | reg = <0x1a>; |
| 382 | interrupt-parent = <&gpio>; |
| 383 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
| 384 | |
| 385 | gpio-controller; |
| 386 | #gpio-cells = <2>; |
| 387 | |
| 388 | micdet-cfg = <0>; |
| 389 | micdet-delay = <100>; |
| 390 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; |
| 391 | }; |
| 392 | |
| 393 | /* ALS and proximity sensor */ |
| 394 | isl29018@44 { |
| 395 | compatible = "isil,isl29018"; |
| 396 | reg = <0x44>; |
| 397 | interrupt-parent = <&gpio>; |
| 398 | interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; |
| 399 | }; |
| 400 | |
| 401 | gyrometer@68 { |
| 402 | compatible = "invn,mpu3050"; |
| 403 | reg = <0x68>; |
| 404 | interrupt-parent = <&gpio>; |
| 405 | interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_LEVEL_HIGH>; |
| 406 | }; |
Simon Glass | 3682cc3 | 2012-02-29 07:31:27 +0000 | [diff] [blame] | 407 | }; |
| 408 | |
| 409 | i2c@7000c400 { |
Simon Glass | ee7d755 | 2016-01-30 16:37:52 -0700 | [diff] [blame] | 410 | status = "okay"; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 411 | clock-frequency = <100000>; |
| 412 | }; |
| 413 | |
| 414 | i2cmux { |
| 415 | compatible = "i2c-mux-pinctrl"; |
| 416 | #address-cells = <1>; |
| 417 | #size-cells = <0>; |
| 418 | |
| 419 | i2c-parent = <&{/i2c@7000c400}>; |
| 420 | |
| 421 | pinctrl-names = "ddc", "pta", "idle"; |
| 422 | pinctrl-0 = <&state_i2cmux_ddc>; |
| 423 | pinctrl-1 = <&state_i2cmux_pta>; |
| 424 | pinctrl-2 = <&state_i2cmux_idle>; |
| 425 | |
| 426 | hdmi_ddc: i2c@0 { |
| 427 | reg = <0>; |
| 428 | #address-cells = <1>; |
| 429 | #size-cells = <0>; |
| 430 | }; |
| 431 | |
| 432 | lvds_ddc: i2c@1 { |
| 433 | reg = <1>; |
| 434 | #address-cells = <1>; |
| 435 | #size-cells = <0>; |
| 436 | |
| 437 | smart-battery@b { |
| 438 | compatible = "ti,bq20z75", "smart-battery-1.1"; |
| 439 | reg = <0xb>; |
| 440 | ti,i2c-retry-count = <2>; |
| 441 | ti,poll-retry-count = <10>; |
| 442 | }; |
| 443 | }; |
Simon Glass | 3682cc3 | 2012-02-29 07:31:27 +0000 | [diff] [blame] | 444 | }; |
| 445 | |
| 446 | i2c@7000c500 { |
Simon Glass | ee7d755 | 2016-01-30 16:37:52 -0700 | [diff] [blame] | 447 | status = "okay"; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 448 | clock-frequency = <400000>; |
| 449 | }; |
| 450 | |
| 451 | i2c@7000d000 { |
| 452 | status = "okay"; |
| 453 | clock-frequency = <400000>; |
| 454 | |
| 455 | magnetometer@c { |
| 456 | compatible = "asahi-kasei,ak8975"; |
| 457 | reg = <0xc>; |
| 458 | interrupt-parent = <&gpio>; |
| 459 | interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_LEVEL_HIGH>; |
| 460 | }; |
| 461 | |
| 462 | pmic: tps6586x@34 { |
| 463 | compatible = "ti,tps6586x"; |
| 464 | reg = <0x34>; |
| 465 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 466 | |
| 467 | ti,system-power-controller; |
| 468 | |
| 469 | #gpio-cells = <2>; |
| 470 | gpio-controller; |
| 471 | |
| 472 | sys-supply = <&vdd_5v0_reg>; |
| 473 | vin-sm0-supply = <&sys_reg>; |
| 474 | vin-sm1-supply = <&sys_reg>; |
| 475 | vin-sm2-supply = <&sys_reg>; |
| 476 | vinldo01-supply = <&sm2_reg>; |
| 477 | vinldo23-supply = <&sm2_reg>; |
| 478 | vinldo4-supply = <&sm2_reg>; |
| 479 | vinldo678-supply = <&sm2_reg>; |
| 480 | vinldo9-supply = <&sm2_reg>; |
| 481 | |
| 482 | regulators { |
| 483 | sys_reg: sys { |
| 484 | regulator-name = "vdd_sys"; |
| 485 | regulator-always-on; |
| 486 | }; |
| 487 | |
| 488 | sm0 { |
| 489 | regulator-name = "vdd_sm0,vdd_core"; |
| 490 | regulator-min-microvolt = <1300000>; |
| 491 | regulator-max-microvolt = <1300000>; |
| 492 | regulator-always-on; |
| 493 | }; |
| 494 | |
| 495 | sm1 { |
| 496 | regulator-name = "vdd_sm1,vdd_cpu"; |
| 497 | regulator-min-microvolt = <1125000>; |
| 498 | regulator-max-microvolt = <1125000>; |
| 499 | regulator-always-on; |
| 500 | }; |
| 501 | |
| 502 | sm2_reg: sm2 { |
| 503 | regulator-name = "vdd_sm2,vin_ldo*"; |
| 504 | regulator-min-microvolt = <3700000>; |
| 505 | regulator-max-microvolt = <3700000>; |
| 506 | regulator-always-on; |
| 507 | }; |
| 508 | |
| 509 | /* LDO0 is not connected to anything */ |
| 510 | |
| 511 | ldo1 { |
| 512 | regulator-name = "vdd_ldo1,avdd_pll*"; |
| 513 | regulator-min-microvolt = <1100000>; |
| 514 | regulator-max-microvolt = <1100000>; |
| 515 | regulator-always-on; |
| 516 | }; |
| 517 | |
| 518 | ldo2 { |
| 519 | regulator-name = "vdd_ldo2,vdd_rtc"; |
| 520 | regulator-min-microvolt = <1200000>; |
| 521 | regulator-max-microvolt = <1200000>; |
| 522 | }; |
| 523 | |
| 524 | ldo3 { |
| 525 | regulator-name = "vdd_ldo3,avdd_usb*"; |
| 526 | regulator-min-microvolt = <3300000>; |
| 527 | regulator-max-microvolt = <3300000>; |
| 528 | regulator-always-on; |
| 529 | }; |
| 530 | |
| 531 | ldo4 { |
| 532 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
| 533 | regulator-min-microvolt = <1800000>; |
| 534 | regulator-max-microvolt = <1800000>; |
| 535 | regulator-always-on; |
| 536 | }; |
| 537 | |
| 538 | ldo5 { |
| 539 | regulator-name = "vdd_ldo5,vcore_mmc"; |
| 540 | regulator-min-microvolt = <2850000>; |
| 541 | regulator-max-microvolt = <2850000>; |
| 542 | regulator-always-on; |
| 543 | }; |
| 544 | |
| 545 | ldo6 { |
| 546 | regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam"; |
| 547 | regulator-min-microvolt = <1800000>; |
| 548 | regulator-max-microvolt = <1800000>; |
| 549 | }; |
| 550 | |
| 551 | hdmi_vdd_reg: ldo7 { |
| 552 | regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; |
| 553 | regulator-min-microvolt = <3300000>; |
| 554 | regulator-max-microvolt = <3300000>; |
| 555 | }; |
| 556 | |
| 557 | hdmi_pll_reg: ldo8 { |
| 558 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
| 559 | regulator-min-microvolt = <1800000>; |
| 560 | regulator-max-microvolt = <1800000>; |
| 561 | }; |
| 562 | |
| 563 | ldo9 { |
| 564 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; |
| 565 | regulator-min-microvolt = <2850000>; |
| 566 | regulator-max-microvolt = <2850000>; |
| 567 | regulator-always-on; |
| 568 | }; |
| 569 | |
| 570 | ldo_rtc { |
| 571 | regulator-name = "vdd_rtc_out,vdd_cell"; |
| 572 | regulator-min-microvolt = <3300000>; |
| 573 | regulator-max-microvolt = <3300000>; |
| 574 | regulator-always-on; |
| 575 | }; |
| 576 | }; |
| 577 | }; |
| 578 | |
| 579 | temperature-sensor@4c { |
| 580 | compatible = "onnn,nct1008"; |
| 581 | reg = <0x4c>; |
| 582 | }; |
Simon Glass | 3682cc3 | 2012-02-29 07:31:27 +0000 | [diff] [blame] | 583 | }; |
Simon Glass | d376e8d | 2012-04-05 11:55:15 +0000 | [diff] [blame] | 584 | |
Allen Martin | b7723f3 | 2013-01-16 13:12:24 +0000 | [diff] [blame] | 585 | kbc@7000e200 { |
Simon Glass | ee7d755 | 2016-01-30 16:37:52 -0700 | [diff] [blame] | 586 | status = "okay"; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 587 | nvidia,debounce-delay-ms = <32>; |
| 588 | nvidia,repeat-delay-ms = <160>; |
| 589 | nvidia,ghost-filter; |
| 590 | nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; |
| 591 | nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>; |
| 592 | linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W) |
| 593 | MATRIX_KEY(0x00, 0x03, KEY_S) |
| 594 | MATRIX_KEY(0x00, 0x04, KEY_A) |
| 595 | MATRIX_KEY(0x00, 0x05, KEY_Z) |
| 596 | MATRIX_KEY(0x00, 0x07, KEY_FN) |
| 597 | |
| 598 | MATRIX_KEY(0x01, 0x07, KEY_LEFTMETA) |
| 599 | MATRIX_KEY(0x02, 0x06, KEY_RIGHTALT) |
| 600 | MATRIX_KEY(0x02, 0x07, KEY_LEFTALT) |
| 601 | |
| 602 | MATRIX_KEY(0x03, 0x00, KEY_5) |
| 603 | MATRIX_KEY(0x03, 0x01, KEY_4) |
| 604 | MATRIX_KEY(0x03, 0x02, KEY_R) |
| 605 | MATRIX_KEY(0x03, 0x03, KEY_E) |
| 606 | MATRIX_KEY(0x03, 0x04, KEY_F) |
| 607 | MATRIX_KEY(0x03, 0x05, KEY_D) |
| 608 | MATRIX_KEY(0x03, 0x06, KEY_X) |
| 609 | |
| 610 | MATRIX_KEY(0x04, 0x00, KEY_7) |
| 611 | MATRIX_KEY(0x04, 0x01, KEY_6) |
| 612 | MATRIX_KEY(0x04, 0x02, KEY_T) |
| 613 | MATRIX_KEY(0x04, 0x03, KEY_H) |
| 614 | MATRIX_KEY(0x04, 0x04, KEY_G) |
| 615 | MATRIX_KEY(0x04, 0x05, KEY_V) |
| 616 | MATRIX_KEY(0x04, 0x06, KEY_C) |
| 617 | MATRIX_KEY(0x04, 0x07, KEY_SPACE) |
| 618 | |
| 619 | MATRIX_KEY(0x05, 0x00, KEY_9) |
| 620 | MATRIX_KEY(0x05, 0x01, KEY_8) |
| 621 | MATRIX_KEY(0x05, 0x02, KEY_U) |
| 622 | MATRIX_KEY(0x05, 0x03, KEY_Y) |
| 623 | MATRIX_KEY(0x05, 0x04, KEY_J) |
| 624 | MATRIX_KEY(0x05, 0x05, KEY_N) |
| 625 | MATRIX_KEY(0x05, 0x06, KEY_B) |
| 626 | MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH) |
| 627 | |
| 628 | MATRIX_KEY(0x06, 0x00, KEY_MINUS) |
| 629 | MATRIX_KEY(0x06, 0x01, KEY_0) |
| 630 | MATRIX_KEY(0x06, 0x02, KEY_O) |
| 631 | MATRIX_KEY(0x06, 0x03, KEY_I) |
| 632 | MATRIX_KEY(0x06, 0x04, KEY_L) |
| 633 | MATRIX_KEY(0x06, 0x05, KEY_K) |
| 634 | MATRIX_KEY(0x06, 0x06, KEY_COMMA) |
| 635 | MATRIX_KEY(0x06, 0x07, KEY_M) |
| 636 | |
| 637 | MATRIX_KEY(0x07, 0x01, KEY_EQUAL) |
| 638 | MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE) |
| 639 | MATRIX_KEY(0x07, 0x03, KEY_ENTER) |
| 640 | MATRIX_KEY(0x07, 0x07, KEY_MENU) |
| 641 | |
| 642 | MATRIX_KEY(0x08, 0x04, KEY_RIGHTSHIFT) |
| 643 | MATRIX_KEY(0x08, 0x05, KEY_LEFTSHIFT) |
| 644 | |
| 645 | MATRIX_KEY(0x09, 0x05, KEY_RIGHTCTRL) |
| 646 | MATRIX_KEY(0x09, 0x07, KEY_LEFTCTRL) |
| 647 | |
| 648 | MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE) |
| 649 | MATRIX_KEY(0x0B, 0x01, KEY_P) |
| 650 | MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE) |
| 651 | MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON) |
| 652 | MATRIX_KEY(0x0B, 0x04, KEY_SLASH) |
| 653 | MATRIX_KEY(0x0B, 0x05, KEY_DOT) |
| 654 | |
| 655 | MATRIX_KEY(0x0C, 0x00, KEY_F10) |
| 656 | MATRIX_KEY(0x0C, 0x01, KEY_F9) |
| 657 | MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE) |
| 658 | MATRIX_KEY(0x0C, 0x03, KEY_3) |
| 659 | MATRIX_KEY(0x0C, 0x04, KEY_2) |
| 660 | MATRIX_KEY(0x0C, 0x05, KEY_UP) |
| 661 | MATRIX_KEY(0x0C, 0x06, KEY_PRINT) |
| 662 | MATRIX_KEY(0x0C, 0x07, KEY_PAUSE) |
| 663 | |
| 664 | MATRIX_KEY(0x0D, 0x00, KEY_INSERT) |
| 665 | MATRIX_KEY(0x0D, 0x01, KEY_DELETE) |
| 666 | MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP ) |
| 667 | MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN) |
| 668 | MATRIX_KEY(0x0D, 0x05, KEY_RIGHT) |
| 669 | MATRIX_KEY(0x0D, 0x06, KEY_DOWN) |
| 670 | MATRIX_KEY(0x0D, 0x07, KEY_LEFT) |
| 671 | |
| 672 | MATRIX_KEY(0x0E, 0x00, KEY_F11) |
| 673 | MATRIX_KEY(0x0E, 0x01, KEY_F12) |
| 674 | MATRIX_KEY(0x0E, 0x02, KEY_F8) |
| 675 | MATRIX_KEY(0x0E, 0x03, KEY_Q) |
| 676 | MATRIX_KEY(0x0E, 0x04, KEY_F4) |
| 677 | MATRIX_KEY(0x0E, 0x05, KEY_F3) |
| 678 | MATRIX_KEY(0x0E, 0x06, KEY_1) |
| 679 | MATRIX_KEY(0x0E, 0x07, KEY_F7) |
| 680 | |
| 681 | MATRIX_KEY(0x0F, 0x00, KEY_ESC) |
| 682 | MATRIX_KEY(0x0F, 0x01, KEY_GRAVE) |
| 683 | MATRIX_KEY(0x0F, 0x02, KEY_F5) |
| 684 | MATRIX_KEY(0x0F, 0x03, KEY_TAB) |
| 685 | MATRIX_KEY(0x0F, 0x04, KEY_F1) |
| 686 | MATRIX_KEY(0x0F, 0x05, KEY_F2) |
| 687 | MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK) |
| 688 | MATRIX_KEY(0x0F, 0x07, KEY_F6) |
| 689 | |
| 690 | /* Software Handled Function Keys */ |
| 691 | MATRIX_KEY(0x14, 0x00, KEY_KP7) |
| 692 | |
| 693 | MATRIX_KEY(0x15, 0x00, KEY_KP9) |
| 694 | MATRIX_KEY(0x15, 0x01, KEY_KP8) |
| 695 | MATRIX_KEY(0x15, 0x02, KEY_KP4) |
| 696 | MATRIX_KEY(0x15, 0x04, KEY_KP1) |
| 697 | |
| 698 | MATRIX_KEY(0x16, 0x01, KEY_KPSLASH) |
| 699 | MATRIX_KEY(0x16, 0x02, KEY_KP6) |
| 700 | MATRIX_KEY(0x16, 0x03, KEY_KP5) |
| 701 | MATRIX_KEY(0x16, 0x04, KEY_KP3) |
| 702 | MATRIX_KEY(0x16, 0x05, KEY_KP2) |
| 703 | MATRIX_KEY(0x16, 0x07, KEY_KP0) |
| 704 | |
| 705 | MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK) |
| 706 | MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS) |
| 707 | MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS) |
| 708 | MATRIX_KEY(0x1B, 0x05, KEY_KPDOT) |
| 709 | |
| 710 | MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP) |
| 711 | |
| 712 | MATRIX_KEY(0x1D, 0x03, KEY_HOME) |
| 713 | MATRIX_KEY(0x1D, 0x04, KEY_END) |
| 714 | MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSDOWN) |
| 715 | MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN) |
| 716 | MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSUP) |
| 717 | |
| 718 | MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK) |
| 719 | MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK) |
| 720 | MATRIX_KEY(0x1E, 0x02, KEY_MUTE) |
| 721 | |
| 722 | MATRIX_KEY(0x1F, 0x04, KEY_HELP)>; |
Allen Martin | b7723f3 | 2013-01-16 13:12:24 +0000 | [diff] [blame] | 723 | }; |
| 724 | |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 725 | pmc@7000e400 { |
| 726 | nvidia,invert-interrupt; |
| 727 | nvidia,suspend-mode = <1>; |
| 728 | nvidia,cpu-pwr-good-time = <5000>; |
| 729 | nvidia,cpu-pwr-off-time = <5000>; |
| 730 | nvidia,core-pwr-good-time = <3845 3845>; |
| 731 | nvidia,core-pwr-off-time = <3875>; |
| 732 | nvidia,sys-clock-req-active-high; |
| 733 | }; |
| 734 | |
| 735 | memory-controller@7000f400 { |
Simon Glass | d376e8d | 2012-04-05 11:55:15 +0000 | [diff] [blame] | 736 | emc-table@190000 { |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 737 | reg = <190000>; |
Simon Glass | d376e8d | 2012-04-05 11:55:15 +0000 | [diff] [blame] | 738 | compatible = "nvidia,tegra20-emc-table"; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 739 | clock-frequency = <190000>; |
| 740 | nvidia,emc-registers = <0x0000000c 0x00000026 |
Simon Glass | d376e8d | 2012-04-05 11:55:15 +0000 | [diff] [blame] | 741 | 0x00000009 0x00000003 0x00000004 0x00000004 |
| 742 | 0x00000002 0x0000000c 0x00000003 0x00000003 |
| 743 | 0x00000002 0x00000001 0x00000004 0x00000005 |
| 744 | 0x00000004 0x00000009 0x0000000d 0x0000059f |
| 745 | 0x00000000 0x00000003 0x00000003 0x00000003 |
| 746 | 0x00000003 0x00000001 0x0000000b 0x000000c8 |
| 747 | 0x00000003 0x00000007 0x00000004 0x0000000f |
| 748 | 0x00000002 0x00000000 0x00000000 0x00000002 |
| 749 | 0x00000000 0x00000000 0x00000083 0xa06204ae |
| 750 | 0x007dc010 0x00000000 0x00000000 0x00000000 |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 751 | 0x00000000 0x00000000 0x00000000 0x00000000>; |
Simon Glass | d376e8d | 2012-04-05 11:55:15 +0000 | [diff] [blame] | 752 | }; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 753 | |
Simon Glass | d376e8d | 2012-04-05 11:55:15 +0000 | [diff] [blame] | 754 | emc-table@380000 { |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 755 | reg = <380000>; |
Simon Glass | d376e8d | 2012-04-05 11:55:15 +0000 | [diff] [blame] | 756 | compatible = "nvidia,tegra20-emc-table"; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 757 | clock-frequency = <380000>; |
| 758 | nvidia,emc-registers = <0x00000017 0x0000004b |
Simon Glass | d376e8d | 2012-04-05 11:55:15 +0000 | [diff] [blame] | 759 | 0x00000012 0x00000006 0x00000004 0x00000005 |
| 760 | 0x00000003 0x0000000c 0x00000006 0x00000006 |
| 761 | 0x00000003 0x00000001 0x00000004 0x00000005 |
| 762 | 0x00000004 0x00000009 0x0000000d 0x00000b5f |
| 763 | 0x00000000 0x00000003 0x00000003 0x00000006 |
| 764 | 0x00000006 0x00000001 0x00000011 0x000000c8 |
| 765 | 0x00000003 0x0000000e 0x00000007 0x0000000f |
| 766 | 0x00000002 0x00000000 0x00000000 0x00000002 |
| 767 | 0x00000000 0x00000000 0x00000083 0xe044048b |
| 768 | 0x007d8010 0x00000000 0x00000000 0x00000000 |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 769 | 0x00000000 0x00000000 0x00000000 0x00000000>; |
Simon Glass | d376e8d | 2012-04-05 11:55:15 +0000 | [diff] [blame] | 770 | }; |
| 771 | }; |
Anton Staff | c3ab91f | 2012-04-17 09:01:34 +0000 | [diff] [blame] | 772 | |
Allen Martin | b7723f3 | 2013-01-16 13:12:24 +0000 | [diff] [blame] | 773 | usb@c5000000 { |
Simon Glass | ee7d755 | 2016-01-30 16:37:52 -0700 | [diff] [blame] | 774 | status = "okay"; |
Simon Glass | 2b2b50b | 2015-01-05 20:05:41 -0700 | [diff] [blame] | 775 | nvidia,vbus-gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>; |
Allen Martin | b7723f3 | 2013-01-16 13:12:24 +0000 | [diff] [blame] | 776 | dr_mode = "otg"; |
Anton Staff | c3ab91f | 2012-04-17 09:01:34 +0000 | [diff] [blame] | 777 | }; |
Simon Glass | 7cedd181 | 2012-07-29 20:53:28 +0000 | [diff] [blame] | 778 | |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 779 | usb-phy@c5000000 { |
| 780 | status = "okay"; |
| 781 | vbus-supply = <&vbus_reg>; |
| 782 | dr_mode = "otg"; |
| 783 | }; |
| 784 | |
Allen Martin | b7723f3 | 2013-01-16 13:12:24 +0000 | [diff] [blame] | 785 | usb@c5004000 { |
| 786 | status = "disabled"; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 787 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
| 788 | GPIO_ACTIVE_LOW>; |
| 789 | }; |
| 790 | |
| 791 | usb-phy@c5004000 { |
| 792 | status = "okay"; |
| 793 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
| 794 | GPIO_ACTIVE_LOW>; |
Simon Glass | 7cedd181 | 2012-07-29 20:53:28 +0000 | [diff] [blame] | 795 | }; |
Simon Glass | 77139f5 | 2012-10-17 13:24:58 +0000 | [diff] [blame] | 796 | |
Simon Glass | ee7d755 | 2016-01-30 16:37:52 -0700 | [diff] [blame] | 797 | usb@c5008000 { |
| 798 | status = "okay"; |
| 799 | }; |
| 800 | |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 801 | usb-phy@c5008000 { |
| 802 | status = "okay"; |
| 803 | }; |
| 804 | |
| 805 | sdhci@c8000000 { |
| 806 | status = "okay"; |
| 807 | power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
| 808 | bus-width = <4>; |
| 809 | keep-power-in-suspend; |
| 810 | }; |
| 811 | |
Allen Martin | b7723f3 | 2013-01-16 13:12:24 +0000 | [diff] [blame] | 812 | sdhci@c8000400 { |
Tom Warren | 126685a | 2013-02-21 12:31:29 +0000 | [diff] [blame] | 813 | status = "okay"; |
Simon Glass | 2b2b50b | 2015-01-05 20:05:41 -0700 | [diff] [blame] | 814 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
| 815 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; |
| 816 | power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; |
Tom Warren | 126685a | 2013-02-21 12:31:29 +0000 | [diff] [blame] | 817 | bus-width = <4>; |
Allen Martin | b7723f3 | 2013-01-16 13:12:24 +0000 | [diff] [blame] | 818 | }; |
| 819 | |
| 820 | sdhci@c8000600 { |
Tom Warren | 126685a | 2013-02-21 12:31:29 +0000 | [diff] [blame] | 821 | status = "okay"; |
| 822 | bus-width = <8>; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 823 | non-removable; |
| 824 | }; |
| 825 | |
| 826 | backlight: backlight { |
| 827 | compatible = "pwm-backlight"; |
| 828 | |
| 829 | enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; |
| 830 | power-supply = <&vdd_bl_reg>; |
| 831 | pwms = <&pwm 2 5000000>; |
| 832 | |
| 833 | brightness-levels = <0 4 8 16 32 64 128 255>; |
| 834 | default-brightness-level = <6>; |
Simon Glass | 77139f5 | 2012-10-17 13:24:58 +0000 | [diff] [blame] | 835 | }; |
| 836 | |
Simon Glass | ee7d755 | 2016-01-30 16:37:52 -0700 | [diff] [blame] | 837 | clocks { |
| 838 | compatible = "simple-bus"; |
| 839 | #address-cells = <1>; |
| 840 | #size-cells = <0>; |
| 841 | |
| 842 | clk32k_in: clock@0 { |
| 843 | compatible = "fixed-clock"; |
| 844 | reg=<0>; |
| 845 | #clock-cells = <0>; |
| 846 | clock-frequency = <32768>; |
| 847 | }; |
| 848 | }; |
| 849 | |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 850 | gpio-keys { |
| 851 | compatible = "gpio-keys"; |
| 852 | |
| 853 | power { |
| 854 | label = "Power"; |
| 855 | gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
| 856 | linux,code = <KEY_POWER>; |
| 857 | gpio-key,wakeup; |
| 858 | }; |
| 859 | |
| 860 | lid { |
| 861 | label = "Lid"; |
| 862 | gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>; |
| 863 | linux,input-type = <5>; /* EV_SW */ |
| 864 | linux,code = <0>; /* SW_LID */ |
| 865 | debounce-interval = <1>; |
| 866 | gpio-key,wakeup; |
| 867 | }; |
Simon Glass | 91c08af | 2016-01-30 16:38:01 -0700 | [diff] [blame] | 868 | }; |
| 869 | |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 870 | panel: panel { |
Simon Glass | ec55077 | 2016-05-08 16:55:20 -0600 | [diff] [blame] | 871 | compatible = "chunghwa,claa101wa01a", "simple-panel"; |
| 872 | |
| 873 | power-supply = <&vdd_pnl_reg>; |
| 874 | enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>; |
| 875 | |
| 876 | backlight = <&backlight>; |
| 877 | ddc-i2c-bus = <&lvds_ddc>; |
Simon Glass | 77139f5 | 2012-10-17 13:24:58 +0000 | [diff] [blame] | 878 | }; |
Simon Glass | ce02a71 | 2016-05-08 16:55:19 -0600 | [diff] [blame] | 879 | |
| 880 | regulators { |
| 881 | compatible = "simple-bus"; |
| 882 | #address-cells = <1>; |
| 883 | #size-cells = <0>; |
| 884 | |
| 885 | vdd_5v0_reg: regulator@0 { |
| 886 | compatible = "regulator-fixed"; |
| 887 | reg = <0>; |
| 888 | regulator-name = "vdd_5v0"; |
| 889 | regulator-min-microvolt = <5000000>; |
| 890 | regulator-max-microvolt = <5000000>; |
| 891 | regulator-always-on; |
| 892 | }; |
| 893 | |
| 894 | regulator@1 { |
| 895 | compatible = "regulator-fixed"; |
| 896 | reg = <1>; |
| 897 | regulator-name = "vdd_1v5"; |
| 898 | regulator-min-microvolt = <1500000>; |
| 899 | regulator-max-microvolt = <1500000>; |
| 900 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
| 901 | }; |
| 902 | |
| 903 | regulator@2 { |
| 904 | compatible = "regulator-fixed"; |
| 905 | reg = <2>; |
| 906 | regulator-name = "vdd_1v2"; |
| 907 | regulator-min-microvolt = <1200000>; |
| 908 | regulator-max-microvolt = <1200000>; |
| 909 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
| 910 | enable-active-high; |
| 911 | }; |
| 912 | |
| 913 | vbus_reg: regulator@3 { |
| 914 | compatible = "regulator-fixed"; |
| 915 | reg = <3>; |
| 916 | regulator-name = "vdd_vbus_wup1"; |
| 917 | regulator-min-microvolt = <5000000>; |
| 918 | regulator-max-microvolt = <5000000>; |
| 919 | enable-active-high; |
| 920 | gpio = <&gpio TEGRA_GPIO(D, 0) 0>; |
| 921 | regulator-always-on; |
| 922 | regulator-boot-on; |
| 923 | }; |
| 924 | |
| 925 | vdd_pnl_reg: regulator@4 { |
| 926 | compatible = "regulator-fixed"; |
| 927 | reg = <4>; |
| 928 | regulator-name = "vdd_pnl"; |
| 929 | regulator-min-microvolt = <2800000>; |
| 930 | regulator-max-microvolt = <2800000>; |
| 931 | gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; |
| 932 | enable-active-high; |
| 933 | }; |
| 934 | |
| 935 | vdd_bl_reg: regulator@5 { |
| 936 | compatible = "regulator-fixed"; |
| 937 | reg = <5>; |
| 938 | regulator-name = "vdd_bl"; |
| 939 | regulator-min-microvolt = <2800000>; |
| 940 | regulator-max-microvolt = <2800000>; |
| 941 | gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; |
| 942 | enable-active-high; |
| 943 | }; |
| 944 | |
| 945 | vdd_hdmi: regulator@6 { |
| 946 | compatible = "regulator-fixed"; |
| 947 | reg = <6>; |
| 948 | regulator-name = "VDDIO_HDMI"; |
| 949 | regulator-min-microvolt = <5000000>; |
| 950 | regulator-max-microvolt = <5000000>; |
| 951 | gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; |
| 952 | enable-active-high; |
| 953 | vin-supply = <&vdd_5v0_reg>; |
| 954 | }; |
| 955 | }; |
| 956 | |
| 957 | sound { |
| 958 | compatible = "nvidia,tegra-audio-wm8903-seaboard", |
| 959 | "nvidia,tegra-audio-wm8903"; |
| 960 | nvidia,model = "NVIDIA Tegra Seaboard"; |
| 961 | |
| 962 | nvidia,audio-routing = |
| 963 | "Headphone Jack", "HPOUTR", |
| 964 | "Headphone Jack", "HPOUTL", |
| 965 | "Int Spk", "ROP", |
| 966 | "Int Spk", "RON", |
| 967 | "Int Spk", "LOP", |
| 968 | "Int Spk", "LON", |
| 969 | "Mic Jack", "MICBIAS", |
| 970 | "IN1R", "Mic Jack"; |
| 971 | |
| 972 | nvidia,i2s-controller = <&tegra_i2s1>; |
| 973 | nvidia,audio-codec = <&wm8903>; |
| 974 | |
| 975 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
| 976 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>; |
| 977 | |
| 978 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
| 979 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, |
| 980 | <&tegra_car TEGRA20_CLK_CDEV1>; |
| 981 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
| 982 | }; |
Simon Glass | 6710b5b | 2012-02-27 10:52:39 +0000 | [diff] [blame] | 983 | }; |