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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marek Vasutd21f08b2017-10-09 21:08:10 +02002/*
3 * board/renesas/eagle/eagle.c
4 * This file is Eagle board support.
5 *
6 * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasutd21f08b2017-10-09 21:08:10 +02007 */
8
9#include <common.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -070010#include <cpu_func.h>
Simon Glassdb41d652019-12-28 10:45:07 -070011#include <hang.h>
Simon Glass691d7192020-05-10 11:40:02 -060012#include <init.h>
Marek Vasutd21f08b2017-10-09 21:08:10 +020013#include <malloc.h>
14#include <netdev.h>
15#include <dm.h>
16#include <dm/platform_data/serial_sh.h>
17#include <asm/processor.h>
18#include <asm/mach-types.h>
19#include <asm/io.h>
20#include <linux/errno.h>
21#include <asm/arch/sys_proto.h>
22#include <asm/gpio.h>
23#include <asm/arch/gpio.h>
24#include <asm/arch/rmobile.h>
25#include <asm/arch/rcar-mstp.h>
26#include <asm/arch/sh_sdhi.h>
27#include <i2c.h>
28#include <mmc.h>
29
30DECLARE_GLOBAL_DATA_PTR;
31
Marek Vasutc2679522018-06-16 01:16:50 +020032#define CPGWPR 0xE6150900
Marek Vasutd21f08b2017-10-09 21:08:10 +020033#define CPGWPCR 0xE6150904
Marek Vasutd21f08b2017-10-09 21:08:10 +020034
35/* PLL */
36#define PLL0CR 0xE61500D8
37#define PLL0_STC_MASK 0x7F000000
38#define PLL0_STC_OFFSET 24
39
40#define CLK2MHZ(clk) (clk / 1000 / 1000)
41void s_init(void)
42{
43 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
44 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
45 u32 stc;
46
47 /* Watchdog init */
48 writel(0xA5A5A500, &rwdt->rwtcsra);
49 writel(0xA5A5A500, &swdt->swtcsra);
50
51 /* CPU frequency setting. Set to 0.8GHz */
52 stc = ((800 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1) << PLL0_STC_OFFSET;
53 clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
54}
55
Marek Vasutd21f08b2017-10-09 21:08:10 +020056int board_early_init_f(void)
57{
Marek Vasutc2679522018-06-16 01:16:50 +020058 /* Unlock CPG access */
59 writel(0xA5A5FFFF, CPGWPR);
60 writel(0x5A5A0000, CPGWPCR);
Marek Vasutd21f08b2017-10-09 21:08:10 +020061
Marek Vasutd21f08b2017-10-09 21:08:10 +020062 return 0;
63}
64
65int board_init(void)
66{
67 /* adress of boot parameters */
68 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
69
70 return 0;
71}
72
Marek Vasutd21f08b2017-10-09 21:08:10 +020073#define RST_BASE 0xE6160000
74#define RST_CA57RESCNT (RST_BASE + 0x40)
75#define RST_CA53RESCNT (RST_BASE + 0x44)
76#define RST_RSTOUTCR (RST_BASE + 0x58)
77#define RST_CA57_CODE 0xA5A5000F
78#define RST_CA53_CODE 0x5A5A000F
79
80void reset_cpu(ulong addr)
81{
82 unsigned long midr, cputype;
83
84 asm volatile("mrs %0, midr_el1" : "=r" (midr));
85 cputype = (midr >> 4) & 0xfff;
86
87 if (cputype == 0xd03)
88 writel(RST_CA53_CODE, RST_CA53RESCNT);
89 else if (cputype == 0xd07)
90 writel(RST_CA57_CODE, RST_CA57RESCNT);
91 else
92 hang();
93}