Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * Author: Fabio Estevam <fabio.estevam@freescale.com> |
| 5 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 6 | * SPDX-License-Identifier: GPL-2.0+ |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <asm/arch/clock.h> |
| 10 | #include <asm/arch/iomux.h> |
| 11 | #include <asm/arch/imx-regs.h> |
| 12 | #include <asm/arch/mx6-pins.h> |
| 13 | #include <asm/arch/sys_proto.h> |
| 14 | #include <asm/gpio.h> |
| 15 | #include <asm/imx-common/iomux-v3.h> |
| 16 | #include <asm/io.h> |
Alexey Brodkin | 1ace402 | 2014-02-26 17:47:58 +0400 | [diff] [blame] | 17 | #include <linux/sizes.h> |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 18 | #include <common.h> |
| 19 | #include <fsl_esdhc.h> |
| 20 | #include <mmc.h> |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 21 | #include <netdev.h> |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 22 | |
| 23 | DECLARE_GLOBAL_DATA_PTR; |
| 24 | |
Benoît Thébaudeau | 7e2173c | 2013-04-26 01:34:47 +0000 | [diff] [blame] | 25 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 26 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| 27 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 28 | |
Benoît Thébaudeau | 7e2173c | 2013-04-26 01:34:47 +0000 | [diff] [blame] | 29 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ |
| 30 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ |
| 31 | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 32 | |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 33 | #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
| 34 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ |
| 35 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) |
| 36 | |
Fabio Estevam | 694c3bc | 2014-04-11 08:39:43 -0300 | [diff] [blame^] | 37 | #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ |
| 38 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) |
| 39 | |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 40 | #define ETH_PHY_RESET IMX_GPIO_NR(4, 21) |
| 41 | |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 42 | int dram_init(void) |
| 43 | { |
| 44 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
| 45 | |
| 46 | return 0; |
| 47 | } |
| 48 | |
| 49 | static iomux_v3_cfg_t const uart1_pads[] = { |
| 50 | MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 51 | MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 52 | }; |
| 53 | |
| 54 | static iomux_v3_cfg_t const usdhc2_pads[] = { |
| 55 | MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 56 | MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 57 | MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 58 | MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 59 | MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 60 | MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 61 | }; |
| 62 | |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 63 | static iomux_v3_cfg_t const fec_pads[] = { |
| 64 | MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 65 | MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 66 | MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 67 | MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 68 | MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 69 | MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 70 | MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 71 | MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 72 | MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL), |
| 73 | MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 74 | MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 75 | }; |
| 76 | |
Fabio Estevam | 694c3bc | 2014-04-11 08:39:43 -0300 | [diff] [blame^] | 77 | #ifdef CONFIG_MXC_SPI |
| 78 | static iomux_v3_cfg_t ecspi1_pads[] = { |
| 79 | MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 80 | MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 81 | MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), |
| 82 | MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 83 | }; |
| 84 | |
| 85 | static void setup_spi(void) |
| 86 | { |
| 87 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); |
| 88 | } |
| 89 | #endif |
| 90 | |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 91 | static void setup_iomux_uart(void) |
| 92 | { |
| 93 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 94 | } |
| 95 | |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 96 | static void setup_iomux_fec(void) |
| 97 | { |
| 98 | imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); |
| 99 | |
| 100 | /* Reset LAN8720 PHY */ |
| 101 | gpio_direction_output(ETH_PHY_RESET , 0); |
| 102 | udelay(1000); |
| 103 | gpio_set_value(ETH_PHY_RESET, 1); |
| 104 | } |
| 105 | |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 106 | static struct fsl_esdhc_cfg usdhc_cfg[1] = { |
| 107 | {USDHC2_BASE_ADDR}, |
| 108 | }; |
| 109 | |
| 110 | int board_mmc_getcd(struct mmc *mmc) |
| 111 | { |
| 112 | return 1; /* Assume boot SD always present */ |
| 113 | } |
| 114 | |
| 115 | int board_mmc_init(bd_t *bis) |
| 116 | { |
| 117 | imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| 118 | |
| 119 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 120 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
| 121 | } |
| 122 | |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 123 | #ifdef CONFIG_FEC_MXC |
| 124 | int board_eth_init(bd_t *bis) |
| 125 | { |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 126 | setup_iomux_fec(); |
| 127 | |
Fabio Estevam | 12c20c0 | 2014-01-04 17:36:33 -0200 | [diff] [blame] | 128 | return cpu_eth_init(bis); |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | static int setup_fec(void) |
| 132 | { |
| 133 | struct iomuxc_base_regs *iomuxc_regs = |
| 134 | (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR; |
| 135 | int ret; |
| 136 | |
| 137 | /* clear gpr1[14], gpr1[18:17] to select anatop clock */ |
| 138 | clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); |
| 139 | |
Fabio Estevam | 5f98d0b | 2014-01-03 15:55:57 -0200 | [diff] [blame] | 140 | ret = enable_fec_anatop_clock(ENET_50MHz); |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 141 | if (ret) |
| 142 | return ret; |
| 143 | |
| 144 | return 0; |
| 145 | } |
| 146 | #endif |
| 147 | |
| 148 | |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 149 | int board_early_init_f(void) |
| 150 | { |
| 151 | setup_iomux_uart(); |
Fabio Estevam | 694c3bc | 2014-04-11 08:39:43 -0300 | [diff] [blame^] | 152 | #ifdef CONFIG_MXC_SPI |
| 153 | setup_spi(); |
| 154 | #endif |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 155 | return 0; |
| 156 | } |
| 157 | |
| 158 | int board_init(void) |
| 159 | { |
| 160 | /* address of boot parameters */ |
| 161 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 162 | |
Fabio Estevam | 31f0796 | 2013-09-13 00:36:28 -0300 | [diff] [blame] | 163 | #ifdef CONFIG_FEC_MXC |
| 164 | setup_fec(); |
| 165 | #endif |
Fabio Estevam | 57ca432 | 2013-04-10 09:32:58 +0000 | [diff] [blame] | 166 | return 0; |
| 167 | } |
| 168 | |
| 169 | u32 get_board_rev(void) |
| 170 | { |
| 171 | return get_cpu_rev(); |
| 172 | } |
| 173 | |
| 174 | int checkboard(void) |
| 175 | { |
| 176 | puts("Board: MX6SLEVK\n"); |
| 177 | |
| 178 | return 0; |
| 179 | } |