blob: 81b085572dc9639a2f7abf98e22c0ea03b70feb2 [file] [log] [blame]
Poonam Aggrwal49249e12011-02-09 19:17:53 +00001/*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Poonam Aggrwal49249e12011-02-09 19:17:53 +00005 */
6
7/*
8 * P010 RDB board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#ifdef CONFIG_36BIT
15#define CONFIG_PHYS_64BIT
16#endif
Ying Zhang653c28f2014-11-06 13:05:08 +080017#define CONFIG_DISPLAY_BOARDINFO
Poonam Aggrwal49249e12011-02-09 19:17:53 +000018
Poonam Aggrwal49249e12011-02-09 19:17:53 +000019#define CONFIG_P1010
Prabhakar Kushwaha74fa22e2013-04-16 13:27:44 +053020#define CONFIG_E500 /* BOOKE e500 family */
21#include <asm/config_mpc85xx.h>
Dipen Dudhatd793e5a2011-07-28 14:47:28 -050022#define CONFIG_NAND_FSL_IFC
Poonam Aggrwal49249e12011-02-09 19:17:53 +000023
24#ifdef CONFIG_SDCARD
Ying Zhangc9e1f582014-01-24 15:50:09 +080025#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
26#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
27#define CONFIG_SPL_ENV_SUPPORT
28#define CONFIG_SPL_SERIAL_SUPPORT
29#define CONFIG_SPL_MMC_SUPPORT
30#define CONFIG_SPL_MMC_MINIMAL
31#define CONFIG_SPL_FLUSH_IMAGE
32#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
33#define CONFIG_SPL_LIBGENERIC_SUPPORT
34#define CONFIG_SPL_LIBCOMMON_SUPPORT
35#define CONFIG_SPL_I2C_SUPPORT
36#define CONFIG_FSL_LAW /* Use common FSL init code */
37#define CONFIG_SYS_TEXT_BASE 0x11001000
38#define CONFIG_SPL_TEXT_BASE 0xD0001000
39#define CONFIG_SPL_PAD_TO 0x18000
40#define CONFIG_SPL_MAX_SIZE (96 * 1024)
41#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
42#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
43#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
44#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
45#define CONFIG_SYS_MPC85XX_NO_RESETVEC
46#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
47#define CONFIG_SPL_MMC_BOOT
48#ifdef CONFIG_SPL_BUILD
49#define CONFIG_SPL_COMMON_INIT_DDR
50#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +000051#endif
52
53#ifdef CONFIG_SPIFLASH
Ying Zhangc9e1f582014-01-24 15:50:09 +080054#ifdef CONFIG_SECURE_BOOT
Poonam Aggrwal49249e12011-02-09 19:17:53 +000055#define CONFIG_RAMBOOT_SPIFLASH
56#define CONFIG_SYS_TEXT_BASE 0x11000000
Ruchika Gupta84e0fb42014-09-29 11:14:35 +053057#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Ying Zhangc9e1f582014-01-24 15:50:09 +080058#else
Ying Zhangc9e1f582014-01-24 15:50:09 +080059#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
60#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
61#define CONFIG_SPL_ENV_SUPPORT
62#define CONFIG_SPL_SERIAL_SUPPORT
63#define CONFIG_SPL_SPI_SUPPORT
64#define CONFIG_SPL_SPI_FLASH_SUPPORT
65#define CONFIG_SPL_SPI_FLASH_MINIMAL
66#define CONFIG_SPL_FLUSH_IMAGE
67#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
68#define CONFIG_SPL_LIBGENERIC_SUPPORT
69#define CONFIG_SPL_LIBCOMMON_SUPPORT
70#define CONFIG_SPL_I2C_SUPPORT
71#define CONFIG_FSL_LAW /* Use common FSL init code */
72#define CONFIG_SYS_TEXT_BASE 0x11001000
73#define CONFIG_SPL_TEXT_BASE 0xD0001000
74#define CONFIG_SPL_PAD_TO 0x18000
75#define CONFIG_SPL_MAX_SIZE (96 * 1024)
76#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
77#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
78#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
79#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
80#define CONFIG_SYS_MPC85XX_NO_RESETVEC
81#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
82#define CONFIG_SPL_SPI_BOOT
83#ifdef CONFIG_SPL_BUILD
84#define CONFIG_SPL_COMMON_INIT_DDR
85#endif
86#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +000087#endif
88
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053089#ifdef CONFIG_NAND
Ying Zhangc9e1f582014-01-24 15:50:09 +080090#ifdef CONFIG_SECURE_BOOT
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053091#define CONFIG_SPL_INIT_MINIMAL
92#define CONFIG_SPL_SERIAL_SUPPORT
93#define CONFIG_SPL_NAND_SUPPORT
Prabhakar Kushwahafbe76ae2013-12-11 12:42:11 +053094#define CONFIG_SPL_NAND_BOOT
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053095#define CONFIG_SPL_FLUSH_IMAGE
96#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
97
98#define CONFIG_SYS_TEXT_BASE 0x00201000
99#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
100#define CONFIG_SPL_MAX_SIZE 8192
101#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
102#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530103#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530104#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
105#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
106#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
107#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Ying Zhangc9e1f582014-01-24 15:50:09 +0800108#else
Ying Zhangc9e1f582014-01-24 15:50:09 +0800109#ifdef CONFIG_TPL_BUILD
110#define CONFIG_SPL_NAND_BOOT
111#define CONFIG_SPL_FLUSH_IMAGE
112#define CONFIG_SPL_ENV_SUPPORT
113#define CONFIG_SPL_NAND_INIT
114#define CONFIG_SPL_SERIAL_SUPPORT
115#define CONFIG_SPL_LIBGENERIC_SUPPORT
116#define CONFIG_SPL_LIBCOMMON_SUPPORT
117#define CONFIG_SPL_I2C_SUPPORT
118#define CONFIG_SPL_NAND_SUPPORT
119#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
120#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
121#define CONFIG_SPL_COMMON_INIT_DDR
122#define CONFIG_SPL_MAX_SIZE (128 << 10)
123#define CONFIG_SPL_TEXT_BASE 0xD0001000
124#define CONFIG_SYS_MPC85XX_NO_RESETVEC
125#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
126#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
127#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
128#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
129#elif defined(CONFIG_SPL_BUILD)
130#define CONFIG_SPL_INIT_MINIMAL
131#define CONFIG_SPL_SERIAL_SUPPORT
132#define CONFIG_SPL_NAND_SUPPORT
133#define CONFIG_SPL_NAND_MINIMAL
134#define CONFIG_SPL_FLUSH_IMAGE
135#define CONFIG_SPL_TEXT_BASE 0xff800000
136#define CONFIG_SPL_MAX_SIZE 8192
137#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
138#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
139#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
140#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500141#endif
Ying Zhangc9e1f582014-01-24 15:50:09 +0800142#define CONFIG_SPL_PAD_TO 0x20000
143#define CONFIG_TPL_PAD_TO 0x20000
144#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
145#define CONFIG_SYS_TEXT_BASE 0x11001000
146#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
147#endif
148#endif
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500149
150#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
151#define CONFIG_RAMBOOT_NAND
152#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530153#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500154#endif
155
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000156#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530157#define CONFIG_SYS_TEXT_BASE 0xeff40000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000158#endif
159
160#ifndef CONFIG_RESET_VECTOR_ADDRESS
161#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
162#endif
163
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530164#ifdef CONFIG_SPL_BUILD
165#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
166#else
167#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000168#endif
169
170/* High Level Configuration Options */
171#define CONFIG_BOOKE /* BOOKE */
172#define CONFIG_E500 /* BOOKE e500 family */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000173#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +0530174#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000175#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
176
177#define CONFIG_PCI /* Enable PCI/PCIE */
178#if defined(CONFIG_PCI)
179#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
180#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
181#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +0000182#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000183#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
184#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
185
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000186#define CONFIG_CMD_PCI
187
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000188
189/*
190 * PCI Windows
191 * Memory space is mapped 1-1, but I/O space must start from 0.
192 */
193/* controller 1, Slot 1, tgtid 1, Base address a000 */
194#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
195#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
196#ifdef CONFIG_PHYS_64BIT
197#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
198#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
199#else
200#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
201#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
202#endif
203#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
204#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
205#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
206#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
207#ifdef CONFIG_PHYS_64BIT
208#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
209#else
210#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
211#endif
212
213/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Shengzhou Liue512c502013-09-13 14:46:03 +0800214#if defined(CONFIG_P1010RDB_PA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000215#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
Shengzhou Liue512c502013-09-13 14:46:03 +0800216#elif defined(CONFIG_P1010RDB_PB)
217#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
218#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000219#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
220#ifdef CONFIG_PHYS_64BIT
221#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
222#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
223#else
224#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
225#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
226#endif
227#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
228#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
229#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
230#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
231#ifdef CONFIG_PHYS_64BIT
232#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
233#else
234#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
235#endif
236
237#define CONFIG_PCI_PNP /* do pci plug-and-play */
238
239#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
240#define CONFIG_DOS_PARTITION
241#endif
242
243#define CONFIG_FSL_LAW /* Use common FSL init code */
244#define CONFIG_TSEC_ENET
245#define CONFIG_ENV_OVERWRITE
246
247#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
248#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
249
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000250#define CONFIG_MISC_INIT_R
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000251#define CONFIG_HWCONFIG
252/*
253 * These can be toggled for performance analysis, otherwise use default.
254 */
255#define CONFIG_L2_CACHE /* toggle L2 cache */
256#define CONFIG_BTB /* toggle branch predition */
257
258#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
259
260#define CONFIG_ENABLE_36BIT_PHYS
261
262#ifdef CONFIG_PHYS_64BIT
263#define CONFIG_ADDR_MAP 1
264#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
265#endif
266
Zhao Qiangc3cc02a2013-11-26 13:59:15 +0800267#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000268#define CONFIG_SYS_MEMTEST_END 0x1fffffff
269#define CONFIG_PANIC_HANG /* do not reset board on panic */
270
271/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700272#define CONFIG_SYS_FSL_DDR3
York Sun1ba62f12012-02-29 12:36:51 +0000273#define CONFIG_SYS_DDR_RAW_TIMING
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000274#define CONFIG_DDR_SPD
275#define CONFIG_SYS_SPD_BUS_NUM 1
276#define SPD_EEPROM_ADDRESS 0x52
277
278#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
279
280#ifndef __ASSEMBLY__
281extern unsigned long get_sdram_size(void);
282#endif
283#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
284#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
285#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
286
287#define CONFIG_DIMM_SLOTS_PER_CTLR 1
288#define CONFIG_CHIP_SELECTS_PER_CTRL 1
289
290/* DDR3 Controller Settings */
291#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
292#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
293#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
294#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
295#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
296#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
297#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000298#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
299#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
300#define CONFIG_SYS_DDR_RCW_1 0x00000000
301#define CONFIG_SYS_DDR_RCW_2 0x00000000
Shengzhou Liue512c502013-09-13 14:46:03 +0800302#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
303#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000304#define CONFIG_SYS_DDR_TIMING_4 0x00000001
305#define CONFIG_SYS_DDR_TIMING_5 0x03402400
306
Shengzhou Liue512c502013-09-13 14:46:03 +0800307#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
308#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
309#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000310#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
311#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
Shengzhou Liue512c502013-09-13 14:46:03 +0800312#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
313#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000314#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
Shengzhou Liue512c502013-09-13 14:46:03 +0800315#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000316
317/* settings for DDR3 at 667MT/s */
318#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
319#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
320#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
321#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
322#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
323#define CONFIG_SYS_DDR_MODE_1_667 0x00441210
324#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
325#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
326#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
327
328#define CONFIG_SYS_CCSRBAR 0xffe00000
329#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
330
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500331/* Don't relocate CCSRBAR while in NAND_SPL */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530332#ifdef CONFIG_SPL_BUILD
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500333#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
334#endif
335
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000336/*
337 * Memory map
338 *
339 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
340 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
341 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
342 *
343 * Localbus non-cacheable
344 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
345 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
346 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
347 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
348 */
349
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000350/*
351 * IFC Definitions
352 */
353/* NOR Flash on IFC */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530354#ifdef CONFIG_SPL_BUILD
355#define CONFIG_SYS_NO_FLASH
356#endif
357
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000358#define CONFIG_SYS_FLASH_BASE 0xee000000
359#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
360
361#ifdef CONFIG_PHYS_64BIT
362#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
363#else
364#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
365#endif
366
367#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
368 CSPR_PORT_SIZE_16 | \
369 CSPR_MSEL_NOR | \
370 CSPR_V)
371#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
372#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
373/* NOR Flash Timing Params */
374#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
375 FTIM0_NOR_TEADC(0x5) | \
376 FTIM0_NOR_TEAHC(0x5)
377#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
378 FTIM1_NOR_TRAD_NOR(0x0f)
379#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
380 FTIM2_NOR_TCH(0x4) | \
381 FTIM2_NOR_TWP(0x1c)
382#define CONFIG_SYS_NOR_FTIM3 0x0
383
384#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
385#define CONFIG_SYS_FLASH_QUIET_TEST
386#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
387#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
388
389#undef CONFIG_SYS_FLASH_CHECKSUM
390#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
391#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
392
393/* CFI for NOR Flash */
394#define CONFIG_FLASH_CFI_DRIVER
395#define CONFIG_SYS_FLASH_CFI
396#define CONFIG_SYS_FLASH_EMPTY_INFO
397#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
398
399/* NAND Flash on IFC */
400#define CONFIG_SYS_NAND_BASE 0xff800000
401#ifdef CONFIG_PHYS_64BIT
402#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
403#else
404#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
405#endif
406
Zhao Qiangac688072013-09-26 09:10:32 +0800407#define CONFIG_MTD_DEVICE
408#define CONFIG_MTD_PARTITION
409#define CONFIG_CMD_MTDPARTS
410#define MTDIDS_DEFAULT "nand0=ff800000.flash"
411#define MTDPARTS_DEFAULT \
412 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
413
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000414#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
415 | CSPR_PORT_SIZE_8 \
416 | CSPR_MSEL_NAND \
417 | CSPR_V)
418#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
Shengzhou Liue512c502013-09-13 14:46:03 +0800419
420#if defined(CONFIG_P1010RDB_PA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000421#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
422 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
423 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
424 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
425 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
426 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
427 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
Shengzhou Liue512c502013-09-13 14:46:03 +0800428#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
429
430#elif defined(CONFIG_P1010RDB_PB)
431#define CONFIG_SYS_NAND_ONFI_DETECTION
432#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
433 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
434 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
435 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
436 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
437 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
438 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
439#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
440#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000441
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500442#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
443#define CONFIG_SYS_MAX_NAND_DEVICE 1
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500444#define CONFIG_CMD_NAND
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500445
Shengzhou Liue512c502013-09-13 14:46:03 +0800446#if defined(CONFIG_P1010RDB_PA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000447/* NAND Flash Timing Params */
448#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
449 FTIM0_NAND_TWP(0x0C) | \
450 FTIM0_NAND_TWCHT(0x04) | \
451 FTIM0_NAND_TWH(0x05)
452#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
453 FTIM1_NAND_TWBE(0x1d) | \
454 FTIM1_NAND_TRR(0x07) | \
455 FTIM1_NAND_TRP(0x0c)
456#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
457 FTIM2_NAND_TREH(0x05) | \
458 FTIM2_NAND_TWHRE(0x0f)
459#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
460
Shengzhou Liue512c502013-09-13 14:46:03 +0800461#elif defined(CONFIG_P1010RDB_PB)
462/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
463/* ONFI NAND Flash mode0 Timing Params */
464#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
465 FTIM0_NAND_TWP(0x18) | \
466 FTIM0_NAND_TWCHT(0x07) | \
467 FTIM0_NAND_TWH(0x0a))
468#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
469 FTIM1_NAND_TWBE(0x39) | \
470 FTIM1_NAND_TRR(0x0e) | \
471 FTIM1_NAND_TRP(0x18))
472#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
473 FTIM2_NAND_TREH(0x0a) | \
474 FTIM2_NAND_TWHRE(0x1e))
475#define CONFIG_SYS_NAND_FTIM3 0x0
476#endif
477
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000478#define CONFIG_SYS_NAND_DDR_LAW 11
479
480/* Set up IFC registers for boot location NOR/NAND */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530481#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500482#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
483#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
484#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
485#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
486#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
487#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
488#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
489#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
490#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
491#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
492#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
493#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
494#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
495#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
496#else
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000497#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
498#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
499#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
500#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
501#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
502#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
503#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
504#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
505#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
506#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
507#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
508#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
509#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
510#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500511#endif
512
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000513/* CPLD on IFC */
514#define CONFIG_SYS_CPLD_BASE 0xffb00000
515
516#ifdef CONFIG_PHYS_64BIT
517#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
518#else
519#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
520#endif
521
522#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
523 | CSPR_PORT_SIZE_8 \
524 | CSPR_MSEL_GPCM \
525 | CSPR_V)
526#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
527#define CONFIG_SYS_CSOR3 0x0
528/* CPLD Timing parameters for IFC CS3 */
529#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
530 FTIM0_GPCM_TEADC(0x0e) | \
531 FTIM0_GPCM_TEAHC(0x0e))
532#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
533 FTIM1_GPCM_TRAD(0x1f))
534#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800535 FTIM2_GPCM_TCH(0x8) | \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000536 FTIM2_GPCM_TWP(0x1f))
537#define CONFIG_SYS_CS3_FTIM3 0x0
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000538
Aneesh Bansal76c9aaf2014-03-07 19:12:09 +0530539#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
540 defined(CONFIG_RAMBOOT_NAND)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000541#define CONFIG_SYS_RAMBOOT
542#define CONFIG_SYS_EXTRA_ENV_RELOC
543#else
544#undef CONFIG_SYS_RAMBOOT
545#endif
546
Prabhakar Kushwaha74fa22e2013-04-16 13:27:44 +0530547#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Aneesh Bansal50c76362014-01-20 14:57:03 +0530548#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
Prabhakar Kushwaha74fa22e2013-04-16 13:27:44 +0530549#define CONFIG_A003399_NOR_WORKAROUND
550#endif
551#endif
552
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000553#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
554#define CONFIG_BOARD_EARLY_INIT_R
555
556#define CONFIG_SYS_INIT_RAM_LOCK
557#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
558#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
559
560#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
561 - GENERATED_GBL_DATA_SIZE)
562#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
563
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530564#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000565#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
566
Ying Zhangc9e1f582014-01-24 15:50:09 +0800567/*
568 * Config the L2 Cache as L2 SRAM
569 */
570#if defined(CONFIG_SPL_BUILD)
571#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
572#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
573#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
574#define CONFIG_SYS_L2_SIZE (256 << 10)
575#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
576#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
577#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
578#define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10)
579#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
580#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
581#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
582#elif defined(CONFIG_NAND)
583#ifdef CONFIG_TPL_BUILD
584#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
585#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
586#define CONFIG_SYS_L2_SIZE (256 << 10)
587#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
588#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
589#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
590#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
591#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
592#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
593#else
594#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
595#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
596#define CONFIG_SYS_L2_SIZE (256 << 10)
597#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
598#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
599#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
600#endif
601#endif
602#endif
603
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000604/* Serial Port */
605#define CONFIG_CONS_INDEX 1
606#undef CONFIG_SERIAL_SOFTWARE_FIFO
607#define CONFIG_SYS_NS16550
608#define CONFIG_SYS_NS16550_SERIAL
609#define CONFIG_SYS_NS16550_REG_SIZE 1
610#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhangc9e1f582014-01-24 15:50:09 +0800611#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500612#define CONFIG_NS16550_MIN_FUNCTIONS
613#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000614
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000615#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
616
617#define CONFIG_SYS_BAUDRATE_TABLE \
618 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
619
620#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
621#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
622
623/* Use the HUSH parser */
624#define CONFIG_SYS_HUSH_PARSER
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000625
626/*
627 * Pass open firmware flat tree
628 */
629#define CONFIG_OF_LIBFDT
630#define CONFIG_OF_BOARD_SETUP
631#define CONFIG_OF_STDOUT_VIA_ALIAS
632
633/* new uImage format support */
634#define CONFIG_FIT
635#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
636
Heiko Schocher00f792e2012-10-24 13:48:22 +0200637/* I2C */
638#define CONFIG_SYS_I2C
639#define CONFIG_SYS_I2C_FSL
640#define CONFIG_SYS_FSL_I2C_SPEED 400000
641#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
642#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
643#define CONFIG_SYS_FSL_I2C2_SPEED 400000
644#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
645#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Shengzhou Liuad89da02013-09-13 14:46:02 +0800646#define I2C_PCA9557_ADDR1 0x18
Shengzhou Liue512c502013-09-13 14:46:03 +0800647#define I2C_PCA9557_ADDR2 0x19
Shengzhou Liuad89da02013-09-13 14:46:02 +0800648#define I2C_PCA9557_BUS_NUM 0
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000649
650/* I2C EEPROM */
Shengzhou Liue512c502013-09-13 14:46:03 +0800651#if defined(CONFIG_P1010RDB_PB)
652#define CONFIG_ID_EEPROM
653#ifdef CONFIG_ID_EEPROM
654#define CONFIG_SYS_I2C_EEPROM_NXID
655#endif
656#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
657#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
658#define CONFIG_SYS_EEPROM_BUS_NUM 0
659#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
660#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000661/* enable read and write access to EEPROM */
662#define CONFIG_CMD_EEPROM
663#define CONFIG_SYS_I2C_MULTI_EEPROMS
664#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
665#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
666#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
667
668/* RTC */
669#define CONFIG_RTC_PT7C4338
670#define CONFIG_SYS_I2C_RTC_ADDR 0x68
671
672#define CONFIG_CMD_I2C
673
674/*
675 * SPI interface will not be available in case of NAND boot SPI CS0 will be
676 * used for SLIC
677 */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530678#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000679/* eSPI - Enhanced SPI */
680#define CONFIG_FSL_ESPI
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000681#define CONFIG_SPI_FLASH_SPANSION
682#define CONFIG_CMD_SF
683#define CONFIG_SF_DEFAULT_SPEED 10000000
684#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500685#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000686
687#if defined(CONFIG_TSEC_ENET)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000688#define CONFIG_MII /* MII PHY management */
689#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
690#define CONFIG_TSEC1 1
691#define CONFIG_TSEC1_NAME "eTSEC1"
692#define CONFIG_TSEC2 1
693#define CONFIG_TSEC2_NAME "eTSEC2"
694#define CONFIG_TSEC3 1
695#define CONFIG_TSEC3_NAME "eTSEC3"
696
697#define TSEC1_PHY_ADDR 1
698#define TSEC2_PHY_ADDR 0
699#define TSEC3_PHY_ADDR 2
700
701#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
702#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
703#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
704
705#define TSEC1_PHYIDX 0
706#define TSEC2_PHYIDX 0
707#define TSEC3_PHYIDX 0
708
709#define CONFIG_ETHPRIME "eTSEC1"
710
711#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
712
713/* TBI PHY configuration for SGMII mode */
714#define CONFIG_TSEC_TBICR_SETTINGS ( \
715 TBICR_PHY_RESET \
716 | TBICR_ANEG_ENABLE \
717 | TBICR_FULL_DUPLEX \
718 | TBICR_SPEED1_SET \
719 )
720
721#endif /* CONFIG_TSEC_ENET */
722
723
724/* SATA */
725#define CONFIG_FSL_SATA
Zang Roy-R619119760b272012-11-26 00:05:38 +0000726#define CONFIG_FSL_SATA_V2
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000727#define CONFIG_LIBATA
728
729#ifdef CONFIG_FSL_SATA
730#define CONFIG_SYS_SATA_MAX_DEVICE 2
731#define CONFIG_SATA1
732#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
733#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
734#define CONFIG_SATA2
735#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
736#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
737
738#define CONFIG_CMD_SATA
739#define CONFIG_LBA48
740#endif /* #ifdef CONFIG_FSL_SATA */
741
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000742#define CONFIG_MMC
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000743#ifdef CONFIG_MMC
744#define CONFIG_CMD_MMC
745#define CONFIG_DOS_PARTITION
746#define CONFIG_FSL_ESDHC
747#define CONFIG_GENERIC_MMC
748#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
749#endif
750
751#define CONFIG_HAS_FSL_DR_USB
752
753#if defined(CONFIG_HAS_FSL_DR_USB)
754#define CONFIG_USB_EHCI
755
756#ifdef CONFIG_USB_EHCI
757#define CONFIG_CMD_USB
758#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
759#define CONFIG_USB_EHCI_FSL
760#define CONFIG_USB_STORAGE
761#endif
762#endif
763
764/*
765 * Environment
766 */
Ying Zhangc9e1f582014-01-24 15:50:09 +0800767#if defined(CONFIG_SDCARD)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000768#define CONFIG_ENV_IS_IN_MMC
Fabio Estevam4394d0c2012-01-11 09:20:50 +0000769#define CONFIG_FSL_FIXED_MMC_LOCATION
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000770#define CONFIG_SYS_MMC_ENV_DEV 0
771#define CONFIG_ENV_SIZE 0x2000
Ying Zhangc9e1f582014-01-24 15:50:09 +0800772#elif defined(CONFIG_SPIFLASH)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000773#define CONFIG_ENV_IS_IN_SPI_FLASH
774#define CONFIG_ENV_SPI_BUS 0
775#define CONFIG_ENV_SPI_CS 0
776#define CONFIG_ENV_SPI_MAX_HZ 10000000
777#define CONFIG_ENV_SPI_MODE 0
778#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
779#define CONFIG_ENV_SECT_SIZE 0x10000
780#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530781#elif defined(CONFIG_NAND)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500782#define CONFIG_ENV_IS_IN_NAND
Ying Zhangc9e1f582014-01-24 15:50:09 +0800783#ifdef CONFIG_TPL_BUILD
784#define CONFIG_ENV_SIZE 0x2000
785#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
786#else
Shengzhou Liue512c502013-09-13 14:46:03 +0800787#if defined(CONFIG_P1010RDB_PA)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500788#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Shengzhou Liue512c502013-09-13 14:46:03 +0800789#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
790#elif defined(CONFIG_P1010RDB_PB)
791#define CONFIG_ENV_SIZE (16 * 1024)
792#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
793#endif
Ying Zhangc9e1f582014-01-24 15:50:09 +0800794#endif
795#define CONFIG_ENV_OFFSET (1024 * 1024)
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530796#elif defined(CONFIG_SYS_RAMBOOT)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000797#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
798#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
799#define CONFIG_ENV_SIZE 0x2000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000800#else
801#define CONFIG_ENV_IS_IN_FLASH
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000802#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000803#define CONFIG_ENV_SIZE 0x2000
804#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
805#endif
806
807#define CONFIG_LOADS_ECHO /* echo on for serial download */
808#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
809
810/*
811 * Command line configuration.
812 */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000813#define CONFIG_CMD_DATE
814#define CONFIG_CMD_ERRATA
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000815#define CONFIG_CMD_IRQ
816#define CONFIG_CMD_MII
817#define CONFIG_CMD_PING
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000818#define CONFIG_CMD_REGINFO
819
820#undef CONFIG_WATCHDOG /* watchdog disabled */
821
822#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
823 || defined(CONFIG_FSL_SATA)
824#define CONFIG_CMD_EXT2
825#define CONFIG_CMD_FAT
826#define CONFIG_DOS_PARTITION
827#endif
828
Ruchika Gupta737537e2014-10-15 11:35:31 +0530829/* Hash command with SHA acceleration supported in hardware */
830#ifdef CONFIG_FSL_CAAM
831#define CONFIG_CMD_HASH
832#define CONFIG_SHA_HW_ACCEL
833#endif
834
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000835/*
836 * Miscellaneous configurable options
837 */
838#define CONFIG_SYS_LONGHELP /* undef to save memory */
839#define CONFIG_CMDLINE_EDITING /* Command-line editing */
840#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
841#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000842
843#if defined(CONFIG_CMD_KGDB)
844#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
845#else
846#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
847#endif
848#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
849 /* Print Buffer Size */
850#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
851#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000852
853/*
854 * Internal Definitions
855 *
856 * Boot Flags
857 */
858#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
859#define BOOTFLAG_WARM 0x02 /* Software reboot */
860
861/*
862 * For booting Linux, the board info and command line data
863 * have to be in the first 64 MB of memory, since this is
864 * the maximum mapped by the Linux kernel during initialization.
865 */
866#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
867#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
868
869#if defined(CONFIG_CMD_KGDB)
870#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000871#endif
872
873/*
874 * Environment Configuration
875 */
876
877#if defined(CONFIG_TSEC_ENET)
878#define CONFIG_HAS_ETH0
879#define CONFIG_HAS_ETH1
880#define CONFIG_HAS_ETH2
881#endif
882
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000883#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000884#define CONFIG_BOOTFILE "uImage"
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000885#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
886
887/* default location for tftp and bootm */
888#define CONFIG_LOADADDR 1000000
889
890#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
891#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
892
893#define CONFIG_BAUDRATE 115200
894
895#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200896 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000897 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200898 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000899 "loadaddr=1000000\0" \
900 "consoledev=ttyS0\0" \
901 "ramdiskaddr=2000000\0" \
902 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
903 "fdtaddr=c00000\0" \
904 "fdtfile=p1010rdb.dtb\0" \
905 "bdev=sda1\0" \
906 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
907 "othbootargs=ramdisk_size=600000\0" \
908 "usbfatboot=setenv bootargs root=/dev/ram rw " \
909 "console=$consoledev,$baudrate $othbootargs; " \
910 "usb start;" \
911 "fatload usb 0:2 $loadaddr $bootfile;" \
912 "fatload usb 0:2 $fdtaddr $fdtfile;" \
913 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
914 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
915 "usbext2boot=setenv bootargs root=/dev/ram rw " \
916 "console=$consoledev,$baudrate $othbootargs; " \
917 "usb start;" \
918 "ext2load usb 0:4 $loadaddr $bootfile;" \
919 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
920 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
Shengzhou Liue512c502013-09-13 14:46:03 +0800921 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
922 CONFIG_BOOTMODE
923
924#if defined(CONFIG_P1010RDB_PA)
925#define CONFIG_BOOTMODE \
926 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
927 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
928 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
929 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
930 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
931 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
932
933#elif defined(CONFIG_P1010RDB_PB)
934#define CONFIG_BOOTMODE \
935 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
936 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
937 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
938 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
939 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
940 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
941 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
942 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
943 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
944 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
945#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000946
947#define CONFIG_RAMBOOTCOMMAND \
948 "setenv bootargs root=/dev/ram rw " \
949 "console=$consoledev,$baudrate $othbootargs; " \
950 "tftp $ramdiskaddr $ramdiskfile;" \
951 "tftp $loadaddr $bootfile;" \
952 "tftp $fdtaddr $fdtfile;" \
953 "bootm $loadaddr $ramdiskaddr $fdtaddr"
954
955#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
956
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500957#include <asm/fsl_secure_boot.h>
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500958
Ruchika Gupta789490b2014-10-07 15:48:46 +0530959#ifdef CONFIG_SECURE_BOOT
960#define CONFIG_CMD_BLOB
961#endif
962
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000963#endif /* __CONFIG_H */