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wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk0ac6f8b2004-07-09 23:27:13 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * Copyright (C) 2003 Motorola Inc.
4 * Xianghua Xiao (x.xiao@motorola.com)
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * PCI Configuration space access support for MPC85xx PCI Bridge
27 */
28#include <common.h>
29#include <asm/cpm_85xx.h>
30#include <pci.h>
31
Kumar Gala129ba612008-08-12 11:13:08 -050032#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)
wdenk0ac6f8b2004-07-09 23:27:13 +000033
Matthew McClintock08745462006-06-28 10:45:17 -050034static struct pci_controller *pci_hose;
35
wdenk9aea9532004-08-01 23:02:45 +000036void
Matthew McClintock08745462006-06-28 10:45:17 -050037pci_mpc85xx_init(struct pci_controller *board_hose)
wdenk42d1f032003-10-15 23:53:47 +000038{
Matthew McClintock08745462006-06-28 10:45:17 -050039 u16 reg16;
40 u32 dev;
41
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042 volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
Matthew McClintock7376eb82006-10-11 15:13:01 -050043#ifdef CONFIG_MPC85XX_PCI2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044 volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
Matthew McClintock7376eb82006-10-11 15:13:01 -050045#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Matthew McClintock08745462006-06-28 10:45:17 -050047 struct pci_controller * hose;
wdenk42d1f032003-10-15 23:53:47 +000048
Matthew McClintock08745462006-06-28 10:45:17 -050049 pci_hose = board_hose;
50
51 hose = &pci_hose[0];
wdenk42d1f032003-10-15 23:53:47 +000052
wdenk0ac6f8b2004-07-09 23:27:13 +000053 hose->first_busno = 0;
54 hose->last_busno = 0xff;
wdenk42d1f032003-10-15 23:53:47 +000055
Matthew McClintock08745462006-06-28 10:45:17 -050056 pci_setup_indirect(hose,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057 (CONFIG_SYS_IMMR+0x8000),
58 (CONFIG_SYS_IMMR+0x8004));
Matthew McClintock08745462006-06-28 10:45:17 -050059
60 /*
61 * Hose scan.
62 */
63 dev = PCI_BDF(hose->first_busno, 0, 0);
64 pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
65 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
66 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
67
68 /*
69 * Clear non-reserved bits in status register.
70 */
71 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
72
73 if (!(gur->pordevsr & PORDEVSR_PCI)) {
74 /* PCI-X init */
Matthew McClintock38433cc2006-06-28 10:47:03 -050075 if (CONFIG_SYS_CLK_FREQ < 66000000)
76 printf("PCI-X will only work at 66 MHz\n");
77
Matthew McClintock08745462006-06-28 10:45:17 -050078 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
79 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
80 pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
81 }
82
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083 pcix->potar1 = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & 0x000fffff;
Matthew McClintock08745462006-06-28 10:45:17 -050084 pcix->potear1 = 0x00000000;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085 pcix->powbar1 = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
Matthew McClintock08745462006-06-28 10:45:17 -050086 pcix->powbear1 = 0x00000000;
87 pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088 POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
Matthew McClintock08745462006-06-28 10:45:17 -050089
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090 pcix->potar2 = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff;
Matthew McClintock08745462006-06-28 10:45:17 -050091 pcix->potear2 = 0x00000000;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092 pcix->powbar2 = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
Matthew McClintock08745462006-06-28 10:45:17 -050093 pcix->powbear2 = 0x00000000;
94 pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095 POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
Matthew McClintock08745462006-06-28 10:45:17 -050096
97 pcix->pitar1 = 0x00000000;
98 pcix->piwbar1 = 0x00000000;
99 pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
100 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
101
102 pcix->powar3 = 0;
103 pcix->powar4 = 0;
104 pcix->piwar2 = 0;
105 pcix->piwar3 = 0;
106
wdenk9aea9532004-08-01 23:02:45 +0000107 pci_set_region(hose->regions + 0,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108 CONFIG_SYS_PCI1_MEM_BASE,
109 CONFIG_SYS_PCI1_MEM_PHYS,
110 CONFIG_SYS_PCI1_MEM_SIZE,
wdenk9aea9532004-08-01 23:02:45 +0000111 PCI_REGION_MEM);
wdenk42d1f032003-10-15 23:53:47 +0000112
wdenk9aea9532004-08-01 23:02:45 +0000113 pci_set_region(hose->regions + 1,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114 CONFIG_SYS_PCI1_IO_BASE,
115 CONFIG_SYS_PCI1_IO_PHYS,
116 CONFIG_SYS_PCI1_IO_SIZE,
wdenk9aea9532004-08-01 23:02:45 +0000117 PCI_REGION_IO);
wdenk42d1f032003-10-15 23:53:47 +0000118
wdenk0ac6f8b2004-07-09 23:27:13 +0000119 hose->region_count = 2;
wdenk42d1f032003-10-15 23:53:47 +0000120
wdenk9aea9532004-08-01 23:02:45 +0000121 pci_register_hose(hose);
wdenkcf336782004-10-10 20:23:57 +0000122
123#if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
124 /*
125 * This is a SW workaround for an apparent HW problem
126 * in the PCI controller on the MPC85555/41 CDS boards.
127 * The first config cycle must be to a valid, known
128 * device on the PCI bus in order to trick the PCI
129 * controller state machine into a known valid state.
130 * Without this, the first config cycle has the chance
131 * of hanging the controller permanently, just leaving
132 * it in a semi-working state, or leaving it working.
133 *
134 * Pick on the Tundra, Device 17, to get it right.
135 */
136 {
137 u8 header_type;
138
139 pci_hose_read_config_byte(hose,
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700140 PCI_BDF(0,BRIDGE_ID,0),
wdenkcf336782004-10-10 20:23:57 +0000141 PCI_HEADER_TYPE,
142 &header_type);
143 }
wdenkcf336782004-10-10 20:23:57 +0000144#endif
145
wdenk9aea9532004-08-01 23:02:45 +0000146 hose->last_busno = pci_hose_scan(hose);
Matthew McClintock08745462006-06-28 10:45:17 -0500147
148#ifdef CONFIG_MPC85XX_PCI2
149 hose = &pci_hose[1];
150
151 hose->first_busno = pci_hose[0].last_busno + 1;
152 hose->last_busno = 0xff;
153
154 pci_setup_indirect(hose,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155 (CONFIG_SYS_IMMR+0x9000),
156 (CONFIG_SYS_IMMR+0x9004));
Matthew McClintock08745462006-06-28 10:45:17 -0500157
158 dev = PCI_BDF(hose->first_busno, 0, 0);
159 pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
160 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
161 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
162
163 /*
164 * Clear non-reserved bits in status register.
165 */
166 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168 pcix2->potar1 = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & 0x000fffff;
Matthew McClintock08745462006-06-28 10:45:17 -0500169 pcix2->potear1 = 0x00000000;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170 pcix2->powbar1 = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
Matthew McClintock08745462006-06-28 10:45:17 -0500171 pcix2->powbear1 = 0x00000000;
172 pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
Matthew McClintock08745462006-06-28 10:45:17 -0500174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175 pcix2->potar2 = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff;
Matthew McClintock08745462006-06-28 10:45:17 -0500176 pcix2->potear2 = 0x00000000;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177 pcix2->powbar2 = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
Matthew McClintock08745462006-06-28 10:45:17 -0500178 pcix2->powbear2 = 0x00000000;
179 pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180 POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
Matthew McClintock08745462006-06-28 10:45:17 -0500181
182 pcix2->pitar1 = 0x00000000;
183 pcix2->piwbar1 = 0x00000000;
184 pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
185 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
186
187 pcix2->powar3 = 0;
188 pcix2->powar4 = 0;
189 pcix2->piwar2 = 0;
190 pcix2->piwar3 = 0;
191
192 pci_set_region(hose->regions + 0,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193 CONFIG_SYS_PCI2_MEM_BASE,
194 CONFIG_SYS_PCI2_MEM_PHYS,
195 CONFIG_SYS_PCI2_MEM_SIZE,
Matthew McClintock08745462006-06-28 10:45:17 -0500196 PCI_REGION_MEM);
197
198 pci_set_region(hose->regions + 1,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199 CONFIG_SYS_PCI2_IO_BASE,
200 CONFIG_SYS_PCI2_IO_PHYS,
201 CONFIG_SYS_PCI2_IO_SIZE,
Matthew McClintock08745462006-06-28 10:45:17 -0500202 PCI_REGION_IO);
203
204 hose->region_count = 2;
205
206 /*
207 * Hose scan.
208 */
209 pci_register_hose(hose);
210
211 hose->last_busno = pci_hose_scan(hose);
212#endif
wdenk42d1f032003-10-15 23:53:47 +0000213}
wdenk42d1f032003-10-15 23:53:47 +0000214#endif /* CONFIG_PCI */