blob: 4e3c05ad276868d34cb9b01af78c21e2c4188482 [file] [log] [blame]
Poonam Aggrwal49249e12011-02-09 19:17:53 +00001/*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Poonam Aggrwal49249e12011-02-09 19:17:53 +00005 */
6
7/*
8 * P010 RDB board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#ifdef CONFIG_36BIT
15#define CONFIG_PHYS_64BIT
16#endif
Ying Zhang653c28f2014-11-06 13:05:08 +080017#define CONFIG_SYS_GENERIC_BOARD
18#define CONFIG_DISPLAY_BOARDINFO
Poonam Aggrwal49249e12011-02-09 19:17:53 +000019
Poonam Aggrwal49249e12011-02-09 19:17:53 +000020#define CONFIG_P1010
Prabhakar Kushwaha74fa22e2013-04-16 13:27:44 +053021#define CONFIG_E500 /* BOOKE e500 family */
22#include <asm/config_mpc85xx.h>
Dipen Dudhatd793e5a2011-07-28 14:47:28 -050023#define CONFIG_NAND_FSL_IFC
Poonam Aggrwal49249e12011-02-09 19:17:53 +000024
25#ifdef CONFIG_SDCARD
Ying Zhangc9e1f582014-01-24 15:50:09 +080026#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
27#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
28#define CONFIG_SPL_ENV_SUPPORT
29#define CONFIG_SPL_SERIAL_SUPPORT
30#define CONFIG_SPL_MMC_SUPPORT
31#define CONFIG_SPL_MMC_MINIMAL
32#define CONFIG_SPL_FLUSH_IMAGE
33#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
34#define CONFIG_SPL_LIBGENERIC_SUPPORT
35#define CONFIG_SPL_LIBCOMMON_SUPPORT
36#define CONFIG_SPL_I2C_SUPPORT
37#define CONFIG_FSL_LAW /* Use common FSL init code */
38#define CONFIG_SYS_TEXT_BASE 0x11001000
39#define CONFIG_SPL_TEXT_BASE 0xD0001000
40#define CONFIG_SPL_PAD_TO 0x18000
41#define CONFIG_SPL_MAX_SIZE (96 * 1024)
42#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
43#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
44#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
45#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
46#define CONFIG_SYS_MPC85XX_NO_RESETVEC
47#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
48#define CONFIG_SPL_MMC_BOOT
49#ifdef CONFIG_SPL_BUILD
50#define CONFIG_SPL_COMMON_INIT_DDR
51#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +000052#endif
53
54#ifdef CONFIG_SPIFLASH
Ying Zhangc9e1f582014-01-24 15:50:09 +080055#ifdef CONFIG_SECURE_BOOT
Poonam Aggrwal49249e12011-02-09 19:17:53 +000056#define CONFIG_RAMBOOT_SPIFLASH
57#define CONFIG_SYS_TEXT_BASE 0x11000000
Ruchika Gupta84e0fb42014-09-29 11:14:35 +053058#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Ying Zhangc9e1f582014-01-24 15:50:09 +080059#else
Ying Zhangc9e1f582014-01-24 15:50:09 +080060#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
61#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
62#define CONFIG_SPL_ENV_SUPPORT
63#define CONFIG_SPL_SERIAL_SUPPORT
64#define CONFIG_SPL_SPI_SUPPORT
65#define CONFIG_SPL_SPI_FLASH_SUPPORT
66#define CONFIG_SPL_SPI_FLASH_MINIMAL
67#define CONFIG_SPL_FLUSH_IMAGE
68#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
69#define CONFIG_SPL_LIBGENERIC_SUPPORT
70#define CONFIG_SPL_LIBCOMMON_SUPPORT
71#define CONFIG_SPL_I2C_SUPPORT
72#define CONFIG_FSL_LAW /* Use common FSL init code */
73#define CONFIG_SYS_TEXT_BASE 0x11001000
74#define CONFIG_SPL_TEXT_BASE 0xD0001000
75#define CONFIG_SPL_PAD_TO 0x18000
76#define CONFIG_SPL_MAX_SIZE (96 * 1024)
77#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
78#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
79#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
80#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
81#define CONFIG_SYS_MPC85XX_NO_RESETVEC
82#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
83#define CONFIG_SPL_SPI_BOOT
84#ifdef CONFIG_SPL_BUILD
85#define CONFIG_SPL_COMMON_INIT_DDR
86#endif
87#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +000088#endif
89
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053090#ifdef CONFIG_NAND
Ying Zhangc9e1f582014-01-24 15:50:09 +080091#ifdef CONFIG_SECURE_BOOT
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053092#define CONFIG_SPL_INIT_MINIMAL
93#define CONFIG_SPL_SERIAL_SUPPORT
94#define CONFIG_SPL_NAND_SUPPORT
Prabhakar Kushwahafbe76ae2013-12-11 12:42:11 +053095#define CONFIG_SPL_NAND_BOOT
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053096#define CONFIG_SPL_FLUSH_IMAGE
97#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
98
99#define CONFIG_SYS_TEXT_BASE 0x00201000
100#define CONFIG_SPL_TEXT_BASE 0xFFFFE000
101#define CONFIG_SPL_MAX_SIZE 8192
102#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
103#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530104#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530105#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
106#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
107#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
108#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Ying Zhangc9e1f582014-01-24 15:50:09 +0800109#else
Ying Zhangc9e1f582014-01-24 15:50:09 +0800110#ifdef CONFIG_TPL_BUILD
111#define CONFIG_SPL_NAND_BOOT
112#define CONFIG_SPL_FLUSH_IMAGE
113#define CONFIG_SPL_ENV_SUPPORT
114#define CONFIG_SPL_NAND_INIT
115#define CONFIG_SPL_SERIAL_SUPPORT
116#define CONFIG_SPL_LIBGENERIC_SUPPORT
117#define CONFIG_SPL_LIBCOMMON_SUPPORT
118#define CONFIG_SPL_I2C_SUPPORT
119#define CONFIG_SPL_NAND_SUPPORT
120#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
121#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
122#define CONFIG_SPL_COMMON_INIT_DDR
123#define CONFIG_SPL_MAX_SIZE (128 << 10)
124#define CONFIG_SPL_TEXT_BASE 0xD0001000
125#define CONFIG_SYS_MPC85XX_NO_RESETVEC
126#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
127#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
128#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
129#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
130#elif defined(CONFIG_SPL_BUILD)
131#define CONFIG_SPL_INIT_MINIMAL
132#define CONFIG_SPL_SERIAL_SUPPORT
133#define CONFIG_SPL_NAND_SUPPORT
134#define CONFIG_SPL_NAND_MINIMAL
135#define CONFIG_SPL_FLUSH_IMAGE
136#define CONFIG_SPL_TEXT_BASE 0xff800000
137#define CONFIG_SPL_MAX_SIZE 8192
138#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
139#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
140#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
141#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500142#endif
Ying Zhangc9e1f582014-01-24 15:50:09 +0800143#define CONFIG_SPL_PAD_TO 0x20000
144#define CONFIG_TPL_PAD_TO 0x20000
145#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
146#define CONFIG_SYS_TEXT_BASE 0x11001000
147#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
148#endif
149#endif
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500150
151#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
152#define CONFIG_RAMBOOT_NAND
153#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530154#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500155#endif
156
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000157#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530158#define CONFIG_SYS_TEXT_BASE 0xeff40000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000159#endif
160
161#ifndef CONFIG_RESET_VECTOR_ADDRESS
162#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
163#endif
164
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530165#ifdef CONFIG_SPL_BUILD
166#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
167#else
168#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000169#endif
170
171/* High Level Configuration Options */
172#define CONFIG_BOOKE /* BOOKE */
173#define CONFIG_E500 /* BOOKE e500 family */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000174#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +0530175#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000176#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
177
178#define CONFIG_PCI /* Enable PCI/PCIE */
179#if defined(CONFIG_PCI)
180#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
181#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
182#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +0000183#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000184#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
185#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
186
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000187#define CONFIG_CMD_PCI
188
189#define CONFIG_E1000 /* E1000 pci Ethernet card*/
190
191/*
192 * PCI Windows
193 * Memory space is mapped 1-1, but I/O space must start from 0.
194 */
195/* controller 1, Slot 1, tgtid 1, Base address a000 */
196#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
197#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
198#ifdef CONFIG_PHYS_64BIT
199#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
200#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
201#else
202#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
203#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
204#endif
205#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
206#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
207#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
208#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
209#ifdef CONFIG_PHYS_64BIT
210#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
211#else
212#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
213#endif
214
215/* controller 2, Slot 2, tgtid 2, Base address 9000 */
Shengzhou Liue512c502013-09-13 14:46:03 +0800216#if defined(CONFIG_P1010RDB_PA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000217#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
Shengzhou Liue512c502013-09-13 14:46:03 +0800218#elif defined(CONFIG_P1010RDB_PB)
219#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
220#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000221#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
222#ifdef CONFIG_PHYS_64BIT
223#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
224#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
225#else
226#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
227#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
228#endif
229#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
230#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
231#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
232#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
233#ifdef CONFIG_PHYS_64BIT
234#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
235#else
236#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
237#endif
238
239#define CONFIG_PCI_PNP /* do pci plug-and-play */
240
241#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
242#define CONFIG_DOS_PARTITION
243#endif
244
245#define CONFIG_FSL_LAW /* Use common FSL init code */
246#define CONFIG_TSEC_ENET
247#define CONFIG_ENV_OVERWRITE
248
249#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
250#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
251
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000252#define CONFIG_MISC_INIT_R
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000253#define CONFIG_HWCONFIG
254/*
255 * These can be toggled for performance analysis, otherwise use default.
256 */
257#define CONFIG_L2_CACHE /* toggle L2 cache */
258#define CONFIG_BTB /* toggle branch predition */
259
260#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
261
262#define CONFIG_ENABLE_36BIT_PHYS
263
264#ifdef CONFIG_PHYS_64BIT
265#define CONFIG_ADDR_MAP 1
266#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
267#endif
268
Zhao Qiangc3cc02a2013-11-26 13:59:15 +0800269#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000270#define CONFIG_SYS_MEMTEST_END 0x1fffffff
271#define CONFIG_PANIC_HANG /* do not reset board on panic */
272
273/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700274#define CONFIG_SYS_FSL_DDR3
York Sun1ba62f12012-02-29 12:36:51 +0000275#define CONFIG_SYS_DDR_RAW_TIMING
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000276#define CONFIG_DDR_SPD
277#define CONFIG_SYS_SPD_BUS_NUM 1
278#define SPD_EEPROM_ADDRESS 0x52
279
280#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
281
282#ifndef __ASSEMBLY__
283extern unsigned long get_sdram_size(void);
284#endif
285#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
286#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
287#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
288
289#define CONFIG_DIMM_SLOTS_PER_CTLR 1
290#define CONFIG_CHIP_SELECTS_PER_CTRL 1
291
292/* DDR3 Controller Settings */
293#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
294#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
295#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
296#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
297#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
298#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
299#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000300#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
301#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
302#define CONFIG_SYS_DDR_RCW_1 0x00000000
303#define CONFIG_SYS_DDR_RCW_2 0x00000000
Shengzhou Liue512c502013-09-13 14:46:03 +0800304#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
305#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000306#define CONFIG_SYS_DDR_TIMING_4 0x00000001
307#define CONFIG_SYS_DDR_TIMING_5 0x03402400
308
Shengzhou Liue512c502013-09-13 14:46:03 +0800309#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
310#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
311#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000312#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
313#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
Shengzhou Liue512c502013-09-13 14:46:03 +0800314#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
315#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000316#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
Shengzhou Liue512c502013-09-13 14:46:03 +0800317#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000318
319/* settings for DDR3 at 667MT/s */
320#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
321#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
322#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
323#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
324#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
325#define CONFIG_SYS_DDR_MODE_1_667 0x00441210
326#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
327#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
328#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
329
330#define CONFIG_SYS_CCSRBAR 0xffe00000
331#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
332
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500333/* Don't relocate CCSRBAR while in NAND_SPL */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530334#ifdef CONFIG_SPL_BUILD
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500335#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
336#endif
337
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000338/*
339 * Memory map
340 *
341 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
342 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
343 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
344 *
345 * Localbus non-cacheable
346 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
347 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
348 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
349 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
350 */
351
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000352/*
353 * IFC Definitions
354 */
355/* NOR Flash on IFC */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530356#ifdef CONFIG_SPL_BUILD
357#define CONFIG_SYS_NO_FLASH
358#endif
359
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000360#define CONFIG_SYS_FLASH_BASE 0xee000000
361#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
362
363#ifdef CONFIG_PHYS_64BIT
364#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
365#else
366#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
367#endif
368
369#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
370 CSPR_PORT_SIZE_16 | \
371 CSPR_MSEL_NOR | \
372 CSPR_V)
373#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
374#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
375/* NOR Flash Timing Params */
376#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
377 FTIM0_NOR_TEADC(0x5) | \
378 FTIM0_NOR_TEAHC(0x5)
379#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
380 FTIM1_NOR_TRAD_NOR(0x0f)
381#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
382 FTIM2_NOR_TCH(0x4) | \
383 FTIM2_NOR_TWP(0x1c)
384#define CONFIG_SYS_NOR_FTIM3 0x0
385
386#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
387#define CONFIG_SYS_FLASH_QUIET_TEST
388#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
389#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
390
391#undef CONFIG_SYS_FLASH_CHECKSUM
392#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
393#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
394
395/* CFI for NOR Flash */
396#define CONFIG_FLASH_CFI_DRIVER
397#define CONFIG_SYS_FLASH_CFI
398#define CONFIG_SYS_FLASH_EMPTY_INFO
399#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
400
401/* NAND Flash on IFC */
402#define CONFIG_SYS_NAND_BASE 0xff800000
403#ifdef CONFIG_PHYS_64BIT
404#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
405#else
406#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
407#endif
408
Zhao Qiangac688072013-09-26 09:10:32 +0800409#define CONFIG_MTD_DEVICE
410#define CONFIG_MTD_PARTITION
411#define CONFIG_CMD_MTDPARTS
412#define MTDIDS_DEFAULT "nand0=ff800000.flash"
413#define MTDPARTS_DEFAULT \
414 "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)"
415
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000416#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
417 | CSPR_PORT_SIZE_8 \
418 | CSPR_MSEL_NAND \
419 | CSPR_V)
420#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
Shengzhou Liue512c502013-09-13 14:46:03 +0800421
422#if defined(CONFIG_P1010RDB_PA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000423#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
424 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
425 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
426 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
427 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
428 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
429 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
Shengzhou Liue512c502013-09-13 14:46:03 +0800430#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
431
432#elif defined(CONFIG_P1010RDB_PB)
433#define CONFIG_SYS_NAND_ONFI_DETECTION
434#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
435 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
436 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
437 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
438 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
439 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
440 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
441#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
442#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000443
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500444#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
445#define CONFIG_SYS_MAX_NAND_DEVICE 1
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500446#define CONFIG_CMD_NAND
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500447
Shengzhou Liue512c502013-09-13 14:46:03 +0800448#if defined(CONFIG_P1010RDB_PA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000449/* NAND Flash Timing Params */
450#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
451 FTIM0_NAND_TWP(0x0C) | \
452 FTIM0_NAND_TWCHT(0x04) | \
453 FTIM0_NAND_TWH(0x05)
454#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
455 FTIM1_NAND_TWBE(0x1d) | \
456 FTIM1_NAND_TRR(0x07) | \
457 FTIM1_NAND_TRP(0x0c)
458#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
459 FTIM2_NAND_TREH(0x05) | \
460 FTIM2_NAND_TWHRE(0x0f)
461#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
462
Shengzhou Liue512c502013-09-13 14:46:03 +0800463#elif defined(CONFIG_P1010RDB_PB)
464/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
465/* ONFI NAND Flash mode0 Timing Params */
466#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
467 FTIM0_NAND_TWP(0x18) | \
468 FTIM0_NAND_TWCHT(0x07) | \
469 FTIM0_NAND_TWH(0x0a))
470#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
471 FTIM1_NAND_TWBE(0x39) | \
472 FTIM1_NAND_TRR(0x0e) | \
473 FTIM1_NAND_TRP(0x18))
474#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
475 FTIM2_NAND_TREH(0x0a) | \
476 FTIM2_NAND_TWHRE(0x1e))
477#define CONFIG_SYS_NAND_FTIM3 0x0
478#endif
479
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000480#define CONFIG_SYS_NAND_DDR_LAW 11
481
482/* Set up IFC registers for boot location NOR/NAND */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530483#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500484#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
485#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
486#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
487#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
488#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
489#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
490#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
491#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
492#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
493#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
494#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
495#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
496#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
497#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
498#else
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000499#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
500#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
501#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
502#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
503#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
504#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
505#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
506#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
507#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
508#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
509#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
510#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
511#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
512#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500513#endif
514
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000515/* CPLD on IFC */
516#define CONFIG_SYS_CPLD_BASE 0xffb00000
517
518#ifdef CONFIG_PHYS_64BIT
519#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
520#else
521#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
522#endif
523
524#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
525 | CSPR_PORT_SIZE_8 \
526 | CSPR_MSEL_GPCM \
527 | CSPR_V)
528#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
529#define CONFIG_SYS_CSOR3 0x0
530/* CPLD Timing parameters for IFC CS3 */
531#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
532 FTIM0_GPCM_TEADC(0x0e) | \
533 FTIM0_GPCM_TEAHC(0x0e))
534#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
535 FTIM1_GPCM_TRAD(0x1f))
536#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800537 FTIM2_GPCM_TCH(0x8) | \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000538 FTIM2_GPCM_TWP(0x1f))
539#define CONFIG_SYS_CS3_FTIM3 0x0
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000540
Aneesh Bansal76c9aaf2014-03-07 19:12:09 +0530541#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
542 defined(CONFIG_RAMBOOT_NAND)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000543#define CONFIG_SYS_RAMBOOT
544#define CONFIG_SYS_EXTRA_ENV_RELOC
545#else
546#undef CONFIG_SYS_RAMBOOT
547#endif
548
Prabhakar Kushwaha74fa22e2013-04-16 13:27:44 +0530549#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Aneesh Bansal50c76362014-01-20 14:57:03 +0530550#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
Prabhakar Kushwaha74fa22e2013-04-16 13:27:44 +0530551#define CONFIG_A003399_NOR_WORKAROUND
552#endif
553#endif
554
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000555#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
556#define CONFIG_BOARD_EARLY_INIT_R
557
558#define CONFIG_SYS_INIT_RAM_LOCK
559#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
560#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
561
562#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
563 - GENERATED_GBL_DATA_SIZE)
564#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
565
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530566#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000567#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
568
Ying Zhangc9e1f582014-01-24 15:50:09 +0800569/*
570 * Config the L2 Cache as L2 SRAM
571 */
572#if defined(CONFIG_SPL_BUILD)
573#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
574#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
575#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
576#define CONFIG_SYS_L2_SIZE (256 << 10)
577#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
578#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
579#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
580#define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10)
581#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
582#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
583#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
584#elif defined(CONFIG_NAND)
585#ifdef CONFIG_TPL_BUILD
586#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
587#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
588#define CONFIG_SYS_L2_SIZE (256 << 10)
589#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
590#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
591#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
592#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
593#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
594#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
595#else
596#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
597#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
598#define CONFIG_SYS_L2_SIZE (256 << 10)
599#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
600#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
601#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
602#endif
603#endif
604#endif
605
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000606/* Serial Port */
607#define CONFIG_CONS_INDEX 1
608#undef CONFIG_SERIAL_SOFTWARE_FIFO
609#define CONFIG_SYS_NS16550
610#define CONFIG_SYS_NS16550_SERIAL
611#define CONFIG_SYS_NS16550_REG_SIZE 1
612#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhangc9e1f582014-01-24 15:50:09 +0800613#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500614#define CONFIG_NS16550_MIN_FUNCTIONS
615#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000616
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000617#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
618
619#define CONFIG_SYS_BAUDRATE_TABLE \
620 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
621
622#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
623#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
624
625/* Use the HUSH parser */
626#define CONFIG_SYS_HUSH_PARSER
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000627
628/*
629 * Pass open firmware flat tree
630 */
631#define CONFIG_OF_LIBFDT
632#define CONFIG_OF_BOARD_SETUP
633#define CONFIG_OF_STDOUT_VIA_ALIAS
634
635/* new uImage format support */
636#define CONFIG_FIT
637#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
638
Heiko Schocher00f792e2012-10-24 13:48:22 +0200639/* I2C */
640#define CONFIG_SYS_I2C
641#define CONFIG_SYS_I2C_FSL
642#define CONFIG_SYS_FSL_I2C_SPEED 400000
643#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
644#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
645#define CONFIG_SYS_FSL_I2C2_SPEED 400000
646#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
647#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Shengzhou Liuad89da02013-09-13 14:46:02 +0800648#define I2C_PCA9557_ADDR1 0x18
Shengzhou Liue512c502013-09-13 14:46:03 +0800649#define I2C_PCA9557_ADDR2 0x19
Shengzhou Liuad89da02013-09-13 14:46:02 +0800650#define I2C_PCA9557_BUS_NUM 0
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000651
652/* I2C EEPROM */
Shengzhou Liue512c502013-09-13 14:46:03 +0800653#if defined(CONFIG_P1010RDB_PB)
654#define CONFIG_ID_EEPROM
655#ifdef CONFIG_ID_EEPROM
656#define CONFIG_SYS_I2C_EEPROM_NXID
657#endif
658#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
659#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
660#define CONFIG_SYS_EEPROM_BUS_NUM 0
661#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
662#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000663/* enable read and write access to EEPROM */
664#define CONFIG_CMD_EEPROM
665#define CONFIG_SYS_I2C_MULTI_EEPROMS
666#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
667#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
668#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
669
670/* RTC */
671#define CONFIG_RTC_PT7C4338
672#define CONFIG_SYS_I2C_RTC_ADDR 0x68
673
674#define CONFIG_CMD_I2C
675
676/*
677 * SPI interface will not be available in case of NAND boot SPI CS0 will be
678 * used for SLIC
679 */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530680#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000681/* eSPI - Enhanced SPI */
682#define CONFIG_FSL_ESPI
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000683#define CONFIG_SPI_FLASH_SPANSION
684#define CONFIG_CMD_SF
685#define CONFIG_SF_DEFAULT_SPEED 10000000
686#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500687#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000688
689#if defined(CONFIG_TSEC_ENET)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000690#define CONFIG_MII /* MII PHY management */
691#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
692#define CONFIG_TSEC1 1
693#define CONFIG_TSEC1_NAME "eTSEC1"
694#define CONFIG_TSEC2 1
695#define CONFIG_TSEC2_NAME "eTSEC2"
696#define CONFIG_TSEC3 1
697#define CONFIG_TSEC3_NAME "eTSEC3"
698
699#define TSEC1_PHY_ADDR 1
700#define TSEC2_PHY_ADDR 0
701#define TSEC3_PHY_ADDR 2
702
703#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
704#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
705#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
706
707#define TSEC1_PHYIDX 0
708#define TSEC2_PHYIDX 0
709#define TSEC3_PHYIDX 0
710
711#define CONFIG_ETHPRIME "eTSEC1"
712
713#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
714
715/* TBI PHY configuration for SGMII mode */
716#define CONFIG_TSEC_TBICR_SETTINGS ( \
717 TBICR_PHY_RESET \
718 | TBICR_ANEG_ENABLE \
719 | TBICR_FULL_DUPLEX \
720 | TBICR_SPEED1_SET \
721 )
722
723#endif /* CONFIG_TSEC_ENET */
724
725
726/* SATA */
727#define CONFIG_FSL_SATA
Zang Roy-R619119760b272012-11-26 00:05:38 +0000728#define CONFIG_FSL_SATA_V2
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000729#define CONFIG_LIBATA
730
731#ifdef CONFIG_FSL_SATA
732#define CONFIG_SYS_SATA_MAX_DEVICE 2
733#define CONFIG_SATA1
734#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
735#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
736#define CONFIG_SATA2
737#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
738#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
739
740#define CONFIG_CMD_SATA
741#define CONFIG_LBA48
742#endif /* #ifdef CONFIG_FSL_SATA */
743
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000744#define CONFIG_MMC
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000745#ifdef CONFIG_MMC
746#define CONFIG_CMD_MMC
747#define CONFIG_DOS_PARTITION
748#define CONFIG_FSL_ESDHC
749#define CONFIG_GENERIC_MMC
750#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
751#endif
752
753#define CONFIG_HAS_FSL_DR_USB
754
755#if defined(CONFIG_HAS_FSL_DR_USB)
756#define CONFIG_USB_EHCI
757
758#ifdef CONFIG_USB_EHCI
759#define CONFIG_CMD_USB
760#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
761#define CONFIG_USB_EHCI_FSL
762#define CONFIG_USB_STORAGE
763#endif
764#endif
765
766/*
767 * Environment
768 */
Ying Zhangc9e1f582014-01-24 15:50:09 +0800769#if defined(CONFIG_SDCARD)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000770#define CONFIG_ENV_IS_IN_MMC
Fabio Estevam4394d0c2012-01-11 09:20:50 +0000771#define CONFIG_FSL_FIXED_MMC_LOCATION
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000772#define CONFIG_SYS_MMC_ENV_DEV 0
773#define CONFIG_ENV_SIZE 0x2000
Ying Zhangc9e1f582014-01-24 15:50:09 +0800774#elif defined(CONFIG_SPIFLASH)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000775#define CONFIG_ENV_IS_IN_SPI_FLASH
776#define CONFIG_ENV_SPI_BUS 0
777#define CONFIG_ENV_SPI_CS 0
778#define CONFIG_ENV_SPI_MAX_HZ 10000000
779#define CONFIG_ENV_SPI_MODE 0
780#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
781#define CONFIG_ENV_SECT_SIZE 0x10000
782#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530783#elif defined(CONFIG_NAND)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500784#define CONFIG_ENV_IS_IN_NAND
Ying Zhangc9e1f582014-01-24 15:50:09 +0800785#ifdef CONFIG_TPL_BUILD
786#define CONFIG_ENV_SIZE 0x2000
787#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
788#else
Shengzhou Liue512c502013-09-13 14:46:03 +0800789#if defined(CONFIG_P1010RDB_PA)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500790#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Shengzhou Liue512c502013-09-13 14:46:03 +0800791#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
792#elif defined(CONFIG_P1010RDB_PB)
793#define CONFIG_ENV_SIZE (16 * 1024)
794#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
795#endif
Ying Zhangc9e1f582014-01-24 15:50:09 +0800796#endif
797#define CONFIG_ENV_OFFSET (1024 * 1024)
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530798#elif defined(CONFIG_SYS_RAMBOOT)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000799#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
800#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
801#define CONFIG_ENV_SIZE 0x2000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000802#else
803#define CONFIG_ENV_IS_IN_FLASH
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000804#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000805#define CONFIG_ENV_SIZE 0x2000
806#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
807#endif
808
809#define CONFIG_LOADS_ECHO /* echo on for serial download */
810#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
811
812/*
813 * Command line configuration.
814 */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000815#define CONFIG_CMD_DATE
816#define CONFIG_CMD_ERRATA
817#define CONFIG_CMD_ELF
818#define CONFIG_CMD_IRQ
819#define CONFIG_CMD_MII
820#define CONFIG_CMD_PING
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000821#define CONFIG_CMD_REGINFO
822
823#undef CONFIG_WATCHDOG /* watchdog disabled */
824
825#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
826 || defined(CONFIG_FSL_SATA)
827#define CONFIG_CMD_EXT2
828#define CONFIG_CMD_FAT
829#define CONFIG_DOS_PARTITION
830#endif
831
Ruchika Gupta737537e2014-10-15 11:35:31 +0530832/* Hash command with SHA acceleration supported in hardware */
833#ifdef CONFIG_FSL_CAAM
834#define CONFIG_CMD_HASH
835#define CONFIG_SHA_HW_ACCEL
836#endif
837
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000838/*
839 * Miscellaneous configurable options
840 */
841#define CONFIG_SYS_LONGHELP /* undef to save memory */
842#define CONFIG_CMDLINE_EDITING /* Command-line editing */
843#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
844#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000845
846#if defined(CONFIG_CMD_KGDB)
847#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
848#else
849#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
850#endif
851#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
852 /* Print Buffer Size */
853#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
854#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000855
856/*
857 * Internal Definitions
858 *
859 * Boot Flags
860 */
861#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
862#define BOOTFLAG_WARM 0x02 /* Software reboot */
863
864/*
865 * For booting Linux, the board info and command line data
866 * have to be in the first 64 MB of memory, since this is
867 * the maximum mapped by the Linux kernel during initialization.
868 */
869#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
870#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
871
872#if defined(CONFIG_CMD_KGDB)
873#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000874#endif
875
876/*
877 * Environment Configuration
878 */
879
880#if defined(CONFIG_TSEC_ENET)
881#define CONFIG_HAS_ETH0
882#define CONFIG_HAS_ETH1
883#define CONFIG_HAS_ETH2
884#endif
885
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000886#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000887#define CONFIG_BOOTFILE "uImage"
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000888#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
889
890/* default location for tftp and bootm */
891#define CONFIG_LOADADDR 1000000
892
893#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
894#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
895
896#define CONFIG_BAUDRATE 115200
897
898#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200899 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000900 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200901 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000902 "loadaddr=1000000\0" \
903 "consoledev=ttyS0\0" \
904 "ramdiskaddr=2000000\0" \
905 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
906 "fdtaddr=c00000\0" \
907 "fdtfile=p1010rdb.dtb\0" \
908 "bdev=sda1\0" \
909 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
910 "othbootargs=ramdisk_size=600000\0" \
911 "usbfatboot=setenv bootargs root=/dev/ram rw " \
912 "console=$consoledev,$baudrate $othbootargs; " \
913 "usb start;" \
914 "fatload usb 0:2 $loadaddr $bootfile;" \
915 "fatload usb 0:2 $fdtaddr $fdtfile;" \
916 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
917 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
918 "usbext2boot=setenv bootargs root=/dev/ram rw " \
919 "console=$consoledev,$baudrate $othbootargs; " \
920 "usb start;" \
921 "ext2load usb 0:4 $loadaddr $bootfile;" \
922 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
923 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
Shengzhou Liue512c502013-09-13 14:46:03 +0800924 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
925 CONFIG_BOOTMODE
926
927#if defined(CONFIG_P1010RDB_PA)
928#define CONFIG_BOOTMODE \
929 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
930 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
931 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
932 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
933 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
934 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
935
936#elif defined(CONFIG_P1010RDB_PB)
937#define CONFIG_BOOTMODE \
938 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
939 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
940 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
941 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
942 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
943 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
944 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
945 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
946 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
947 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
948#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000949
950#define CONFIG_RAMBOOTCOMMAND \
951 "setenv bootargs root=/dev/ram rw " \
952 "console=$consoledev,$baudrate $othbootargs; " \
953 "tftp $ramdiskaddr $ramdiskfile;" \
954 "tftp $loadaddr $bootfile;" \
955 "tftp $fdtaddr $fdtfile;" \
956 "bootm $loadaddr $ramdiskaddr $fdtaddr"
957
958#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
959
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500960#include <asm/fsl_secure_boot.h>
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500961
Ruchika Gupta789490b2014-10-07 15:48:46 +0530962#ifdef CONFIG_SECURE_BOOT
963#define CONFIG_CMD_BLOB
964#endif
965
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000966#endif /* __CONFIG_H */