blob: cc8700bfb30c04524d23090f7f82ba72c615ba5b [file] [log] [blame]
Mingkai Hu4f1d1b72011-07-07 12:29:15 +08001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Mingkai Hu4f1d1b72011-07-07 12:29:15 +08003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Mingkai Hu4f1d1b72011-07-07 12:29:15 +08005 */
6
7/*
8 * P2041 RDB board configuration file
Scott Wood3e978f52012-08-14 10:14:51 +00009 * Also supports P2040 RDB
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080010 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#define CONFIG_P2041RDB
15#define CONFIG_PHYS_64BIT
Shaohui Xie84d13c52014-12-01 15:39:23 +080016#define CONFIG_SYS_GENERIC_BOARD
17#define CONFIG_DISPLAY_BOARDINFO
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080018#define CONFIG_PPC_P2041
19
20#ifdef CONFIG_RAMBOOT_PBL
21#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
22#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Masahiro Yamadae4536f82014-03-11 11:05:16 +090023#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
24#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080025#endif
26
Liu Gang461632b2012-08-09 05:10:03 +000027#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
Liu Gangff65f122012-08-09 05:09:59 +000028/* Set 1M boot space */
Liu Gang461632b2012-08-09 05:10:03 +000029#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
30#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
31 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
Liu Gangff65f122012-08-09 05:09:59 +000032#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
33#define CONFIG_SYS_NO_FLASH
34#endif
35
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080036/* High Level Configuration Options */
37#define CONFIG_BOOKE
38#define CONFIG_E500 /* BOOKE e500 family */
39#define CONFIG_E500MC /* BOOKE e500mc family */
40#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080041#define CONFIG_MP /* support multiple processors */
42
43#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053044#define CONFIG_SYS_TEXT_BASE 0xeff40000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080045#endif
46
47#ifndef CONFIG_RESET_VECTOR_ADDRESS
48#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
49#endif
50
51#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
52#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
53#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
Ruchika Gupta737537e2014-10-15 11:35:31 +053054#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080055#define CONFIG_PCI /* Enable PCI/PCIE */
56#define CONFIG_PCIE1 /* PCIE controler 1 */
57#define CONFIG_PCIE2 /* PCIE controler 2 */
58#define CONFIG_PCIE3 /* PCIE controler 3 */
59#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
60#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
61
62#define CONFIG_SYS_SRIO
63#define CONFIG_SRIO1 /* SRIO port 1 */
64#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gangc8b28152013-05-07 16:30:46 +080065#define CONFIG_SRIO_PCIE_BOOT_MASTER
Kumar Gala4d28db82011-10-14 13:28:52 -050066#define CONFIG_SYS_DPAA_RMAN /* RMan */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080067
68#define CONFIG_FSL_LAW /* Use common FSL init code */
69
70#define CONFIG_ENV_OVERWRITE
71
72#ifdef CONFIG_SYS_NO_FLASH
Liu Gang461632b2012-08-09 05:10:03 +000073#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080074#define CONFIG_ENV_IS_NOWHERE
Shaohui Xie0f57f6a2012-06-28 23:35:34 +000075#endif
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080076#else
77#define CONFIG_FLASH_CFI_DRIVER
78#define CONFIG_SYS_FLASH_CFI
Shaohui Xie0f57f6a2012-06-28 23:35:34 +000079#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080080#endif
81
82#if defined(CONFIG_SPIFLASH)
83 #define CONFIG_SYS_EXTRA_ENV_RELOC
84 #define CONFIG_ENV_IS_IN_SPI_FLASH
85 #define CONFIG_ENV_SPI_BUS 0
86 #define CONFIG_ENV_SPI_CS 0
87 #define CONFIG_ENV_SPI_MAX_HZ 10000000
88 #define CONFIG_ENV_SPI_MODE 0
89 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
90 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
91 #define CONFIG_ENV_SECT_SIZE 0x10000
92#elif defined(CONFIG_SDCARD)
93 #define CONFIG_SYS_EXTRA_ENV_RELOC
94 #define CONFIG_ENV_IS_IN_MMC
Fabio Estevam4394d0c2012-01-11 09:20:50 +000095 #define CONFIG_FSL_FIXED_MMC_LOCATION
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080096 #define CONFIG_SYS_MMC_ENV_DEV 0
97 #define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053098 #define CONFIG_ENV_OFFSET (512 * 1658)
Shaohui Xie15c8c6c2012-02-28 23:28:40 +000099#elif defined(CONFIG_NAND)
100#define CONFIG_SYS_EXTRA_ENV_RELOC
101#define CONFIG_ENV_IS_IN_NAND
102#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530103#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang461632b2012-08-09 05:10:03 +0000104#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Liu Gangff65f122012-08-09 05:09:59 +0000105#define CONFIG_ENV_IS_IN_REMOTE
106#define CONFIG_ENV_ADDR 0xffe20000
107#define CONFIG_ENV_SIZE 0x2000
Shaohui Xie0f57f6a2012-06-28 23:35:34 +0000108#elif defined(CONFIG_ENV_IS_NOWHERE)
Liu Gangff65f122012-08-09 05:09:59 +0000109#define CONFIG_ENV_SIZE 0x2000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800110#else
111 #define CONFIG_ENV_IS_IN_FLASH
112 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
113 - CONFIG_ENV_SECT_SIZE)
114 #define CONFIG_ENV_SIZE 0x2000
115 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
116#endif
117
Shaohui Xie44d50f02011-09-13 17:55:11 +0800118#ifndef __ASSEMBLY__
119unsigned long get_board_sys_clk(unsigned long dummy);
120#endif
121#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800122
123/*
124 * These can be toggled for performance analysis, otherwise use default.
125 */
126#define CONFIG_SYS_CACHE_STASHING
Mingkai Hucd420e02011-07-21 17:03:54 -0500127#define CONFIG_BACKSIDE_L2_CACHE
128#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800129#define CONFIG_BTB /* toggle branch predition */
130
131#define CONFIG_ENABLE_36BIT_PHYS
132
133#ifdef CONFIG_PHYS_64BIT
134#define CONFIG_ADDR_MAP
135#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
136#endif
137
138#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
139#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
140#define CONFIG_SYS_MEMTEST_END 0x00400000
141#define CONFIG_SYS_ALT_MEMTEST
142#define CONFIG_PANIC_HANG /* do not reset board on panic */
143
144/*
145 * Config the L3 Cache as L3 SRAM
146 */
147#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
148#ifdef CONFIG_PHYS_64BIT
149#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
150 CONFIG_RAMBOOT_TEXT_BASE)
151#else
152#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
153#endif
154#define CONFIG_SYS_L3_SIZE (1024 << 10)
155#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
156
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800157#ifdef CONFIG_PHYS_64BIT
158#define CONFIG_SYS_DCSRBAR 0xf0000000
159#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
160#endif
161
162/* EEPROM */
163#define CONFIG_ID_EEPROM
164#define CONFIG_SYS_I2C_EEPROM_NXID
165#define CONFIG_SYS_EEPROM_BUS_NUM 0
166#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
167#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
168
169/*
170 * DDR Setup
171 */
172#define CONFIG_VERY_BIG_RAM
173#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
174#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
175
176#define CONFIG_DIMM_SLOTS_PER_CTLR 1
177#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
178
179#define CONFIG_DDR_SPD
York Sun5614e712013-09-30 09:22:09 -0700180#define CONFIG_SYS_FSL_DDR3
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800181
182#define CONFIG_SYS_SPD_BUS_NUM 0
183#define SPD_EEPROM_ADDRESS 0x52
184#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
185
186/*
187 * Local Bus Definitions
188 */
189
190/* Set the local bus clock 1/8 of platform clock */
191#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
192
York Sunca1b0b82012-10-26 16:40:15 +0000193/*
194 * This board doesn't have a promjet connector.
195 * However, it uses commone corenet board LAW and TLB.
196 * It is necessary to use the same start address with proper offset.
197 */
198#define CONFIG_SYS_FLASH_BASE 0xe0000000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800199#ifdef CONFIG_PHYS_64BIT
York Sunca1b0b82012-10-26 16:40:15 +0000200#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800201#else
202#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
203#endif
204
Shaohui Xiec9b2fea2012-02-28 23:28:07 +0000205#define CONFIG_SYS_FLASH_BR_PRELIM \
York Sunca1b0b82012-10-26 16:40:15 +0000206 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
207 BR_PS_16 | BR_V)
Shaohui Xiec9b2fea2012-02-28 23:28:07 +0000208#define CONFIG_SYS_FLASH_OR_PRELIM \
209 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
210 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800211
212#define CONFIG_FSL_CPLD
213#define CPLD_BASE 0xffdf0000 /* CPLD registers */
214#ifdef CONFIG_PHYS_64BIT
215#define CPLD_BASE_PHYS 0xfffdf0000ull
216#else
217#define CPLD_BASE_PHYS CPLD_BASE
218#endif
219
220#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
221#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
222
223#define PIXIS_LBMAP_SWITCH 7
224#define PIXIS_LBMAP_MASK 0xf0
225#define PIXIS_LBMAP_SHIFT 4
226#define PIXIS_LBMAP_ALTBANK 0x40
227
228#define CONFIG_SYS_FLASH_QUIET_TEST
229#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
230
231#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
232#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
233#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
234#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
235
236#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
237
238#if defined(CONFIG_RAMBOOT_PBL)
239#define CONFIG_SYS_RAMBOOT
240#endif
241
Shaohui Xiec9b2fea2012-02-28 23:28:07 +0000242#define CONFIG_NAND_FSL_ELBC
243/* Nand Flash */
244#ifdef CONFIG_NAND_FSL_ELBC
245#define CONFIG_SYS_NAND_BASE 0xffa00000
246#ifdef CONFIG_PHYS_64BIT
247#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
248#else
249#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
250#endif
251
252#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
253#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shaohui Xiec9b2fea2012-02-28 23:28:07 +0000254#define CONFIG_CMD_NAND
255#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
256
257/* NAND flash config */
258#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
259 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
260 | BR_PS_8 /* Port Size = 8 bit */ \
261 | BR_MS_FCM /* MSEL = FCM */ \
262 | BR_V) /* valid */
263#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
264 | OR_FCM_PGS /* Large Page*/ \
265 | OR_FCM_CSCT \
266 | OR_FCM_CST \
267 | OR_FCM_CHT \
268 | OR_FCM_SCY_1 \
269 | OR_FCM_TRLX \
270 | OR_FCM_EHTR)
271
272#ifdef CONFIG_NAND
273#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
274#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
275#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
276#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
277#else
278#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
279#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
280#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
281#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
282#endif
283#else
284#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
285#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
286#endif /* CONFIG_NAND_FSL_ELBC */
287
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800288#define CONFIG_SYS_FLASH_EMPTY_INFO
289#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
York Sunca1b0b82012-10-26 16:40:15 +0000290#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800291
292#define CONFIG_BOARD_EARLY_INIT_F
293#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
294#define CONFIG_MISC_INIT_R
295
296#define CONFIG_HWCONFIG
297
298/* define to use L1 as initial stack */
299#define CONFIG_L1_INIT_RAM
300#define CONFIG_SYS_INIT_RAM_LOCK
301#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
302#ifdef CONFIG_PHYS_64BIT
303#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
304#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
305/* The assembler doesn't like typecast */
306#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
307 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
308 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
309#else
310#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
311#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
312#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
313#endif
314#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
315
316#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
317 GENERATED_GBL_DATA_SIZE)
318#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
319
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530320#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800321#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
322
323/* Serial Port - controlled on board with jumper J8
324 * open - index 2
325 * shorted - index 1
326 */
327#define CONFIG_CONS_INDEX 1
328#define CONFIG_SYS_NS16550
329#define CONFIG_SYS_NS16550_SERIAL
330#define CONFIG_SYS_NS16550_REG_SIZE 1
331#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
332
333#define CONFIG_SYS_BAUDRATE_TABLE \
334 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
335
336#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
337#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
338#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
339#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
340
341/* Use the HUSH parser */
342#define CONFIG_SYS_HUSH_PARSER
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800343
344/* pass open firmware flat tree */
345#define CONFIG_OF_LIBFDT
346#define CONFIG_OF_BOARD_SETUP
347#define CONFIG_OF_STDOUT_VIA_ALIAS
348
349/* new uImage format support */
350#define CONFIG_FIT
351#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
352
353/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200354#define CONFIG_SYS_I2C
355#define CONFIG_SYS_I2C_FSL
356#define CONFIG_SYS_FSL_I2C_SPEED 400000
357#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
Shaohui Xie2bd1aab2013-09-10 16:15:07 +0800358#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
Heiko Schocher00f792e2012-10-24 13:48:22 +0200359#define CONFIG_SYS_FSL_I2C2_SPEED 400000
360#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
Shaohui Xie2bd1aab2013-09-10 16:15:07 +0800361#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800362
363/*
364 * RapidIO
365 */
366#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
367#ifdef CONFIG_PHYS_64BIT
368#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
369#else
370#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
371#endif
372#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
373
374#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
375#ifdef CONFIG_PHYS_64BIT
376#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
377#else
378#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
379#endif
380#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
381
382/*
Liu Gangff65f122012-08-09 05:09:59 +0000383 * for slave u-boot IMAGE instored in master memory space,
384 * PHYS must be aligned based on the SIZE
385 */
Liu Gange4911812014-05-15 14:30:34 +0800386#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
387#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
388#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
389#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Liu Gangff65f122012-08-09 05:09:59 +0000390/*
391 * for slave UCODE and ENV instored in master memory space,
392 * PHYS must be aligned based on the SIZE
393 */
Liu Gange4911812014-05-15 14:30:34 +0800394#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Liu Gangb5f7c872012-08-09 05:10:02 +0000395#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
396#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
Liu Gangff65f122012-08-09 05:09:59 +0000397
398/* slave core release by master*/
Liu Gangb5f7c872012-08-09 05:10:02 +0000399#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
400#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
Liu Gangff65f122012-08-09 05:09:59 +0000401
402/*
Liu Gang461632b2012-08-09 05:10:03 +0000403 * SRIO_PCIE_BOOT - SLAVE
Liu Gangff65f122012-08-09 05:09:59 +0000404 */
Liu Gang461632b2012-08-09 05:10:03 +0000405#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
406#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
407#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
408 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
Liu Gangff65f122012-08-09 05:09:59 +0000409#endif
410
411/*
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800412 * eSPI - Enhanced SPI
413 */
414#define CONFIG_FSL_ESPI
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800415#define CONFIG_SPI_FLASH_SPANSION
416#define CONFIG_CMD_SF
417#define CONFIG_SF_DEFAULT_SPEED 10000000
418#define CONFIG_SF_DEFAULT_MODE 0
419
420/*
421 * General PCI
422 * Memory space is mapped 1-1, but I/O space must start from 0.
423 */
424
425/* controller 1, direct to uli, tgtid 3, Base address 20000 */
426#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
427#ifdef CONFIG_PHYS_64BIT
428#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
429#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
430#else
431#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
432#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
433#endif
434#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
435#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
436#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
437#ifdef CONFIG_PHYS_64BIT
438#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
439#else
440#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
441#endif
442#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
443
444/* controller 2, Slot 2, tgtid 2, Base address 201000 */
445#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
446#ifdef CONFIG_PHYS_64BIT
447#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
448#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
449#else
450#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
451#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
452#endif
453#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
454#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
455#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
456#ifdef CONFIG_PHYS_64BIT
457#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
458#else
459#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
460#endif
461#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
462
463/* controller 3, Slot 1, tgtid 1, Base address 202000 */
464#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
465#ifdef CONFIG_PHYS_64BIT
466#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
467#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
468#else
469#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
470#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
471#endif
472#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
473#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
474#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
475#ifdef CONFIG_PHYS_64BIT
476#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
477#else
478#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
479#endif
480#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
481
482/* Qman/Bman */
483#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
484#define CONFIG_SYS_BMAN_NUM_PORTALS 10
485#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
486#ifdef CONFIG_PHYS_64BIT
487#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
488#else
489#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
490#endif
491#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500492#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
493#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
494#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
495#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
496#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
497 CONFIG_SYS_BMAN_CENA_SIZE)
498#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
499#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800500#define CONFIG_SYS_QMAN_NUM_PORTALS 10
501#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
502#ifdef CONFIG_PHYS_64BIT
503#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
504#else
505#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
506#endif
507#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500508#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
509#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
510#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
511#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
512#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
513 CONFIG_SYS_QMAN_CENA_SIZE)
514#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
515#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800516
517#define CONFIG_SYS_DPAA_FMAN
518#define CONFIG_SYS_DPAA_PME
519/* Default address of microcode for the Linux Fman driver */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800520#if defined(CONFIG_SPIFLASH)
521/*
522 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
523 * env, so we got 0x110000.
524 */
Timur Tabif2717b42011-11-22 09:21:25 -0600525#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800526#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800527#elif defined(CONFIG_SDCARD)
528/*
529 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530530 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
531 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800532 */
Timur Tabif2717b42011-11-22 09:21:25 -0600533#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800534#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800535#elif defined(CONFIG_NAND)
Timur Tabif2717b42011-11-22 09:21:25 -0600536#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800537#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang461632b2012-08-09 05:10:03 +0000538#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Liu Gangff65f122012-08-09 05:09:59 +0000539/*
540 * Slave has no ucode locally, it can fetch this from remote. When implementing
541 * in two corenet boards, slave's ucode could be stored in master's memory
542 * space, the address can be mapped from slave TLB->slave LAW->
Liu Gang461632b2012-08-09 05:10:03 +0000543 * slave SRIO or PCIE outbound window->master inbound window->
544 * master LAW->the ucode address in master's memory space.
Liu Gangff65f122012-08-09 05:09:59 +0000545 */
546#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800547#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800548#else
Timur Tabif2717b42011-11-22 09:21:25 -0600549#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800550#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800551#endif
Timur Tabif2717b42011-11-22 09:21:25 -0600552#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
553#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800554
555#ifdef CONFIG_SYS_DPAA_FMAN
556#define CONFIG_FMAN_ENET
Mingkai Hu0787ecc2011-07-19 16:20:13 +0800557#define CONFIG_PHYLIB_10G
558#define CONFIG_PHY_VITESSE
559#define CONFIG_PHY_TERANETICS
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800560#endif
561
562#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000563#define CONFIG_PCI_INDIRECT_BRIDGE
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800564#define CONFIG_PCI_PNP /* do pci plug-and-play */
565#define CONFIG_E1000
566
567#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
568#define CONFIG_DOS_PARTITION
569#endif /* CONFIG_PCI */
570
Mingkai Huaa7f281c2011-07-27 09:55:51 +0800571/* SATA */
Zang Roy-R619119760b272012-11-26 00:05:38 +0000572#define CONFIG_FSL_SATA_V2
573
574#ifdef CONFIG_FSL_SATA_V2
Mingkai Huaa7f281c2011-07-27 09:55:51 +0800575#define CONFIG_FSL_SATA
Timur Tabi3e0529f2011-11-21 17:10:22 -0600576#define CONFIG_LIBATA
Mingkai Huaa7f281c2011-07-27 09:55:51 +0800577
578#define CONFIG_SYS_SATA_MAX_DEVICE 2
579#define CONFIG_SATA1
580#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
581#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
582#define CONFIG_SATA2
583#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
584#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
585
586#define CONFIG_LBA48
587#define CONFIG_CMD_SATA
588#define CONFIG_DOS_PARTITION
589#define CONFIG_CMD_EXT2
590#endif
591
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800592#ifdef CONFIG_FMAN_ENET
593#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
594#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
595#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
596#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
597#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
598
599#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
600#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
601#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
602#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
603
Mingkai Hu0787ecc2011-07-19 16:20:13 +0800604#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
605
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800606#define CONFIG_SYS_TBIPA_VALUE 8
607#define CONFIG_MII /* MII PHY management */
608#define CONFIG_ETHPRIME "FM1@DTSEC1"
609#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
610#endif
611
612/*
613 * Environment
614 */
615#define CONFIG_LOADS_ECHO /* echo on for serial download */
616#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
617
618/*
619 * Command line configuration.
620 */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800621#define CONFIG_CMD_DHCP
622#define CONFIG_CMD_ELF
623#define CONFIG_CMD_ERRATA
624#define CONFIG_CMD_GREPENV
625#define CONFIG_CMD_IRQ
626#define CONFIG_CMD_I2C
627#define CONFIG_CMD_MII
628#define CONFIG_CMD_PING
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800629
630#ifdef CONFIG_PCI
631#define CONFIG_CMD_PCI
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800632#endif
633
634/*
635* USB
636*/
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000637#define CONFIG_HAS_FSL_DR_USB
638#define CONFIG_HAS_FSL_MPH_USB
639
640#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800641#define CONFIG_CMD_USB
642#define CONFIG_USB_STORAGE
643#define CONFIG_USB_EHCI
644#define CONFIG_USB_EHCI_FSL
645#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000646#endif
647
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800648#define CONFIG_CMD_EXT2
649
650#define CONFIG_MMC
651
652#ifdef CONFIG_MMC
653#define CONFIG_FSL_ESDHC
654#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
655#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
656#define CONFIG_CMD_MMC
657#define CONFIG_GENERIC_MMC
658#define CONFIG_CMD_EXT2
659#define CONFIG_CMD_FAT
660#define CONFIG_DOS_PARTITION
661#endif
662
Ruchika Gupta737537e2014-10-15 11:35:31 +0530663/* Hash command with SHA acceleration supported in hardware */
664#ifdef CONFIG_FSL_CAAM
665#define CONFIG_CMD_HASH
666#define CONFIG_SHA_HW_ACCEL
667#endif
668
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800669/*
670 * Miscellaneous configurable options
671 */
672#define CONFIG_SYS_LONGHELP /* undef to save memory */
673#define CONFIG_CMDLINE_EDITING /* Command-line editing */
674#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
675#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800676#ifdef CONFIG_CMD_KGDB
677#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
678#else
679#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
680#endif
681/* Print Buffer Size */
682#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
683 sizeof(CONFIG_SYS_PROMPT)+16)
684#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
685/* Boot Argument Buffer Size */
686#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800687
688/*
689 * For booting Linux, the board info and command line data
690 * have to be in the first 64 MB of memory, since this is
691 * the maximum mapped by the Linux kernel during initialization.
692 */
693#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
694#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
695
696#ifdef CONFIG_CMD_KGDB
697#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800698#endif
699
700/*
701 * Environment Configuration
702 */
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000703#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000704#define CONFIG_BOOTFILE "uImage"
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800705#define CONFIG_UBOOTPATH u-boot.bin
706
707/* default location for tftp and bootm */
708#define CONFIG_LOADADDR 1000000
709
710#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
711
712#define CONFIG_BAUDRATE 115200
713
714#define __USB_PHY_TYPE utmi
715
716#define CONFIG_EXTRA_ENV_SETTINGS \
717 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
718 "bank_intlv=cs0_cs1\0" \
719 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200720 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
721 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800722 "tftpflash=tftpboot $loadaddr $uboot && " \
723 "protect off $ubootaddr +$filesize && " \
724 "erase $ubootaddr +$filesize && " \
725 "cp.b $loadaddr $ubootaddr $filesize && " \
726 "protect on $ubootaddr +$filesize && " \
727 "cmp.b $loadaddr $ubootaddr $filesize\0" \
728 "consoledev=ttyS0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200729 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800730 "usb_dr_mode=host\0" \
731 "ramdiskaddr=2000000\0" \
732 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
733 "fdtaddr=c00000\0" \
734 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500735 "bdev=sda3\0"
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800736
737#define CONFIG_HDBOOT \
738 "setenv bootargs root=/dev/$bdev rw " \
739 "console=$consoledev,$baudrate $othbootargs;" \
740 "tftp $loadaddr $bootfile;" \
741 "tftp $fdtaddr $fdtfile;" \
742 "bootm $loadaddr - $fdtaddr"
743
744#define CONFIG_NFSBOOTCOMMAND \
745 "setenv bootargs root=/dev/nfs rw " \
746 "nfsroot=$serverip:$rootpath " \
747 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
748 "console=$consoledev,$baudrate $othbootargs;" \
749 "tftp $loadaddr $bootfile;" \
750 "tftp $fdtaddr $fdtfile;" \
751 "bootm $loadaddr - $fdtaddr"
752
753#define CONFIG_RAMBOOTCOMMAND \
754 "setenv bootargs root=/dev/ram rw " \
755 "console=$consoledev,$baudrate $othbootargs;" \
756 "tftp $ramdiskaddr $ramdiskfile;" \
757 "tftp $loadaddr $bootfile;" \
758 "tftp $fdtaddr $fdtfile;" \
759 "bootm $loadaddr $ramdiskaddr $fdtaddr"
760
761#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
762
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800763#include <asm/fsl_secure_boot.h>
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800764
Ruchika Gupta789490b2014-10-07 15:48:46 +0530765#ifdef CONFIG_SECURE_BOOT
766#define CONFIG_CMD_BLOB
767#endif
768
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800769#endif /* __CONFIG_H */