blob: 635227800e1e940ee1cb56b866bbf3ebfc7da664 [file] [log] [blame]
wdenk10a36a92004-07-10 23:02:23 +00001/*
2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
4 *
5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
6 * Added support for Wind River SBC8560 board
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
Paul Gortmaker928435d2009-09-21 17:19:17 -040027/*
28 * sbc8560 board configuration file.
wdenk10a36a92004-07-10 23:02:23 +000029 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
Paul Gortmaker928435d2009-09-21 17:19:17 -040034/*
35 * Top level Makefile configuration choices
36 */
37#ifdef CONFIG_MK_66
38#define CONFIG_PCI_66
39#endif
40
41/*
42 * High Level Configuration Options
43 */
wdenk10a36a92004-07-10 23:02:23 +000044#define CONFIG_BOOKE 1 /* BOOKE */
45#define CONFIG_E500 1 /* BOOKE e500 family */
46#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
47#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
48
49
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050050#define CONFIG_CPM2 1 /* has CPM2 */
wdenk10a36a92004-07-10 23:02:23 +000051#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
Kumar Galaf0600542008-06-11 00:44:10 -050052#define CONFIG_MPC8560 1
wdenk10a36a92004-07-10 23:02:23 +000053
54/* XXX flagging this as something I might want to delete */
55#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
56
57#define CONFIG_TSEC_ENET /* tsec ethernet support */
58#undef CONFIG_PCI /* pci ethernet support */
59#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
60
Kumar Galae2b159d2008-01-16 09:05:27 -060061#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk10a36a92004-07-10 23:02:23 +000062
63#define CONFIG_ENV_OVERWRITE
64
65/* Using Localbus SDRAM to emulate flash before we can program the flash,
66 * normally you need a flash-boot image(u-boot.bin), if so undef this.
67 */
68#undef CONFIG_RAM_AS_FLASH
69
70#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
71 #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
72#else
73 #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
74#endif
75
76/* below can be toggled for performance analysis. otherwise use default */
77#define CONFIG_L2_CACHE /* toggle L2 cache */
78#undef CONFIG_BTB /* toggle branch predition */
wdenk10a36a92004-07-10 23:02:23 +000079
80#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Peter Tyser004eca02009-09-16 22:03:08 -050081#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk10a36a92004-07-10 23:02:23 +000082
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
84#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
85#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk10a36a92004-07-10 23:02:23 +000086
87#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
88 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
89 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
90#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
91#endif
92
93/*
94 * Base addresses -- Note these are effective addresses where the
95 * actual resources get mapped (not physical addresses)
96 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
wdenk10a36a92004-07-10 23:02:23 +000098
99#if XXX
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100 #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
wdenk10a36a92004-07-10 23:02:23 +0000101#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102 #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */
wdenk10a36a92004-07-10 23:02:23 +0000103#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
105#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenk10a36a92004-07-10 23:02:23 +0000106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
wdenk10a36a92004-07-10 23:02:23 +0000108
Kumar Gala8e553132008-08-26 23:52:58 -0500109/* DDR Setup */
110#define CONFIG_FSL_DDR1
111#undef CONFIG_FSL_DDR_INTERACTIVE
112#undef CONFIG_DDR_ECC /* only for ECC DDR module */
113#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
114#undef CONFIG_DDR_SPD
wdenk10a36a92004-07-10 23:02:23 +0000115
116#if defined(CONFIG_MPC85xx_REV1)
Kumar Gala8e553132008-08-26 23:52:58 -0500117 #define CONFIG_DDR_DLL /* possible DLL fix needed */
wdenk10a36a92004-07-10 23:02:23 +0000118#endif
119
Kumar Gala8e553132008-08-26 23:52:58 -0500120#undef CONFIG_DDR_ECC /* only for ECC DDR module */
121#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
122#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
125#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala8e553132008-08-26 23:52:58 -0500126#define CONFIG_VERY_BIG_RAM
127
128#define CONFIG_NUM_DDR_CONTROLLERS 1
129#define CONFIG_DIMM_SLOTS_PER_CTLR 1
130#define CONFIG_CHIP_SELECTS_PER_CTRL 2
131
132/* I2C addresses of SPD EEPROMs */
133#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
134
wdenk10a36a92004-07-10 23:02:23 +0000135#undef CONFIG_CLOCKS_IN_MHZ
136
137#if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138 #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
139 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
140 #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
141 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
wdenk10a36a92004-07-10 23:02:23 +0000142#else /* Boot from real Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
144 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
145 #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
146 #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
wdenk10a36a92004-07-10 23:02:23 +0000147#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk10a36a92004-07-10 23:02:23 +0000149
150/* local bus definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
152#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
wdenk10a36a92004-07-10 23:02:23 +0000153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
155#define CONFIG_SYS_OR2_PRELIM 0x00000000
wdenk10a36a92004-07-10 23:02:23 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
158#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
wdenk10a36a92004-07-10 23:02:23 +0000159
160#if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
wdenk10a36a92004-07-10 23:02:23 +0000162#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163 #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
wdenk10a36a92004-07-10 23:02:23 +0000164#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
wdenk10a36a92004-07-10 23:02:23 +0000166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
wdenk10a36a92004-07-10 23:02:23 +0000168#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
wdenk10a36a92004-07-10 23:02:23 +0000170#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171 #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
wdenk10a36a92004-07-10 23:02:23 +0000172#endif
173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
175#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
176#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
177#define CONFIG_SYS_LBC_LBCR 0x00000000
178#define CONFIG_SYS_LBC_LSRT 0x20000000
179#define CONFIG_SYS_LBC_MRTPR 0x20000000
180#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
181#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
182#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
183#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
184#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
wdenk10a36a92004-07-10 23:02:23 +0000185
186/* just hijack the MOT BCSR def for SBC8560 misc devices */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
wdenk10a36a92004-07-10 23:02:23 +0000188/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_INIT_RAM_LOCK 1
191#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
192#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenk10a36a92004-07-10 23:02:23 +0000193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
195#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
196#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk10a36a92004-07-10 23:02:23 +0000197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
199#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk10a36a92004-07-10 23:02:23 +0000200
201/* Serial Port */
Paul Gortmakerc158bca2008-07-11 15:33:05 -0400202#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
203#undef CONFIG_CONS_NONE /* define if console on something else */
wdenk10a36a92004-07-10 23:02:23 +0000204
205#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_NS16550
207#define CONFIG_SYS_NS16550_SERIAL
208#define CONFIG_SYS_NS16550_REG_SIZE 1
209#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
wdenk10a36a92004-07-10 23:02:23 +0000210#define CONFIG_BAUDRATE 9600
211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk10a36a92004-07-10 23:02:23 +0000213 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
216#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
wdenk10a36a92004-07-10 23:02:23 +0000217
218/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_HUSH_PARSER
220#ifdef CONFIG_SYS_HUSH_PARSER
221#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk10a36a92004-07-10 23:02:23 +0000222#endif
223
Paul Gortmakerc3ca7e52008-07-11 15:33:08 -0400224/* pass open firmware flat tree */
225#define CONFIG_OF_LIBFDT 1
226#define CONFIG_OF_BOARD_SETUP 1
227#define CONFIG_OF_STDOUT_VIA_ALIAS 1
228
Jon Loeliger20476722006-10-20 15:50:15 -0500229/*
230 * I2C
231 */
232#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
233#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk10a36a92004-07-10 23:02:23 +0000234#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
236#define CONFIG_SYS_I2C_SLAVE 0x7F
237#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
238#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk10a36a92004-07-10 23:02:23 +0000239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
241#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
242#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
wdenk10a36a92004-07-10 23:02:23 +0000243
Paul Gortmaker6de5bf22008-07-11 15:33:03 -0400244#ifdef CONFIG_TSEC_ENET
wdenk10a36a92004-07-10 23:02:23 +0000245
Paul Gortmaker6de5bf22008-07-11 15:33:03 -0400246#ifndef CONFIG_NET_MULTI
247#define CONFIG_NET_MULTI 1
248#endif
249
250#ifndef CONFIG_MII
251#define CONFIG_MII 1 /* MII PHY management */
252#endif
253#define CONFIG_TSEC1 1
254#define CONFIG_TSEC1_NAME "TSEC0"
255#define CONFIG_TSEC2 1
256#define CONFIG_TSEC2_NAME "TSEC1"
257#define TSEC1_PHY_ADDR 0x19
258#define TSEC2_PHY_ADDR 0x1a
259#define TSEC1_PHYIDX 0
260#define TSEC2_PHYIDX 0
261#define TSEC1_FLAGS TSEC_GIGABIT
262#define TSEC2_FLAGS TSEC_GIGABIT
263
264/* Options are: TSEC[0-1] */
265#define CONFIG_ETHPRIME "TSEC0"
wdenk10a36a92004-07-10 23:02:23 +0000266
267#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
268
269 #undef CONFIG_ETHER_NONE /* define if ether on something else */
270 #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
271 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
272
273 #if (CONFIG_ETHER_INDEX == 2)
274 /*
275 * - Rx-CLK is CLK13
276 * - Tx-CLK is CLK14
277 * - Select bus for bd/buffers
278 * - Full duplex
279 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
281 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
282 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
283 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk10a36a92004-07-10 23:02:23 +0000284
285 #elif (CONFIG_ETHER_INDEX == 3)
286 /* need more definitions here for FE3 */
287 #endif /* CONFIG_ETHER_INDEX */
288
289 #define CONFIG_MII /* MII PHY management */
290 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
291 /*
292 * GPIO pins used for bit-banged MII communications
293 */
294 #define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200295 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
296 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
297 #define MDC_DECLARE MDIO_DECLARE
298
wdenk10a36a92004-07-10 23:02:23 +0000299 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
300 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
301 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
302
303 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
304 else iop->pdat &= ~0x00400000
305
306 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
307 else iop->pdat &= ~0x00200000
308
309 #define MIIDELAY udelay(1)
310
311#endif
312
313/*-----------------------------------------------------------------------
314 * FLASH and environment organization
315 */
316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200318#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
wdenk10a36a92004-07-10 23:02:23 +0000319#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
321#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
wdenk10a36a92004-07-10 23:02:23 +0000322#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
324#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk10a36a92004-07-10 23:02:23 +0000325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#undef CONFIG_SYS_FLASH_CHECKSUM
327#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
328#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
wdenk10a36a92004-07-10 23:02:23 +0000329
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
wdenk10a36a92004-07-10 23:02:23 +0000331
332#if 0
333/* XXX This doesn't work and I don't want to fix it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
335 #define CONFIG_SYS_RAMBOOT
wdenk10a36a92004-07-10 23:02:23 +0000336#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337 #undef CONFIG_SYS_RAMBOOT
wdenk10a36a92004-07-10 23:02:23 +0000338#endif
339#endif
340
341/* Environment */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#if !defined(CONFIG_SYS_RAMBOOT)
wdenk10a36a92004-07-10 23:02:23 +0000343 #if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200344 #define CONFIG_ENV_IS_NOWHERE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200346 #define CONFIG_ENV_SIZE 0x2000
wdenk10a36a92004-07-10 23:02:23 +0000347 #else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200348 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200349 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200351 #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
wdenk10a36a92004-07-10 23:02:23 +0000352 #endif
353#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200355 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200357 #define CONFIG_ENV_SIZE 0x2000
wdenk10a36a92004-07-10 23:02:23 +0000358#endif
359
Paul Gortmakerc158bca2008-07-11 15:33:05 -0400360#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600"
wdenk10a36a92004-07-10 23:02:23 +0000361/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
wdenk10a36a92004-07-10 23:02:23 +0000362#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
363
364#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk10a36a92004-07-10 23:02:23 +0000366
Jon Loeliger2835e512007-06-13 13:22:08 -0500367
368/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500369 * BOOTP options
370 */
371#define CONFIG_BOOTP_BOOTFILESIZE
372#define CONFIG_BOOTP_BOOTPATH
373#define CONFIG_BOOTP_GATEWAY
374#define CONFIG_BOOTP_HOSTNAME
375
376
377/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500378 * Command line configuration.
379 */
380#include <config_cmd_default.h>
381
382#define CONFIG_CMD_PING
383#define CONFIG_CMD_I2C
Becky Bruce199e2622010-06-17 11:37:25 -0500384#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500385
386#if defined(CONFIG_PCI)
387 #define CONFIG_CMD_PCI
wdenk10a36a92004-07-10 23:02:23 +0000388#endif
389
Jon Loeliger2835e512007-06-13 13:22:08 -0500390#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
391 #define CONFIG_CMD_MII
392#endif
393
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500395 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500396 #undef CONFIG_CMD_LOADS
397#endif
398
wdenk10a36a92004-07-10 23:02:23 +0000399
400#undef CONFIG_WATCHDOG /* watchdog disabled */
401
402/*
403 * Miscellaneous configurable options
404 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_LONGHELP /* undef to save memory */
406#define CONFIG_SYS_PROMPT "SBC8560=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500407#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk10a36a92004-07-10 23:02:23 +0000409#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk10a36a92004-07-10 23:02:23 +0000411#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
413#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
414#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
415#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
416#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk10a36a92004-07-10 23:02:23 +0000417
418/*
419 * For booting Linux, the board info and command line data
420 * have to be in the first 8 MB of memory, since this is
421 * the maximum mapped by the Linux kernel during initialization.
422 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk10a36a92004-07-10 23:02:23 +0000424
wdenk10a36a92004-07-10 23:02:23 +0000425/*
426 * Internal Definitions
427 *
428 * Boot Flags
429 */
430#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
431#define BOOTFLAG_WARM 0x02 /* Software reboot */
432
Jon Loeliger2835e512007-06-13 13:22:08 -0500433#if defined(CONFIG_CMD_KGDB)
Paul Gortmaker37fef492008-07-11 15:33:07 -0400434#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
435#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
wdenk10a36a92004-07-10 23:02:23 +0000436#endif
437
wdenk10a36a92004-07-10 23:02:23 +0000438#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Paul Gortmakerc158bca2008-07-11 15:33:05 -0400439#define CONFIG_HAS_ETH0
440#define CONFIG_HAS_ETH1
wdenk10a36a92004-07-10 23:02:23 +0000441#endif
442
Paul Gortmakerc158bca2008-07-11 15:33:05 -0400443/* You can compile in a MAC address and your custom net settings by using
444 * the following syntax. Your board should be marked with the assigned
445 * MAC addresses directly on it.
446 *
447 * #define CONFIG_ETHADDR de:ad:be:ef:00:00
448 * #define CONFIG_ETH1ADDR fa:ke:ad:dr:es:s!
449 * #define CONFIG_SERVERIP <server ip>
450 * #define CONFIG_IPADDR <board ip>
451 * #define CONFIG_GATEWAYIP <gateway ip>
452 * #define CONFIG_NETMASK <your netmask>
453 */
454
wdenk10a36a92004-07-10 23:02:23 +0000455#define CONFIG_HOSTNAME SBC8560
456#define CONFIG_ROOTPATH /home/ppc
Paul Gortmaker37fef492008-07-11 15:33:07 -0400457#define CONFIG_BOOTFILE uImage
458
459#define CONFIG_EXTRA_ENV_SETTINGS \
460 "netdev=eth0\0" \
461 "consoledev=ttyS0\0" \
462 "ramdiskaddr=2000000\0" \
463 "ramdiskfile=ramdisk.uboot\0" \
464 "fdtaddr=c00000\0" \
465 "fdtfile=sbc8560.dtb\0"
466
467#define CONFIG_NFSBOOTCOMMAND \
468 "setenv bootargs root=/dev/nfs rw " \
469 "nfsroot=$serverip:$rootpath " \
470 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
471 "console=$consoledev,$baudrate $othbootargs;" \
472 "tftp $loadaddr $bootfile;" \
473 "tftp $fdtaddr $fdtfile;" \
474 "bootm $loadaddr - $fdtaddr"
475
476
477#define CONFIG_RAMBOOTCOMMAND \
478 "setenv bootargs root=/dev/ram rw " \
479 "console=$consoledev,$baudrate $othbootargs;" \
480 "tftp $ramdiskaddr $ramdiskfile;" \
481 "tftp $loadaddr $bootfile;" \
482 "tftp $fdtaddr $fdtfile;" \
483 "bootm $loadaddr $ramdiskaddr $fdtaddr"
484
485#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk10a36a92004-07-10 23:02:23 +0000486
487#endif /* __CONFIG_H */