blob: 11d1f0c24cd84f25ae08e2e406150d7a966d9edc [file] [log] [blame]
Lei Wenaf62a552011-06-28 21:50:06 +00001/*
2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Lei Wenaf62a552011-06-28 21:50:06 +00006 *
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
9 */
10
11#include <common.h>
Simon Glass2a809092016-06-12 23:30:27 -060012#include <errno.h>
Lei Wenaf62a552011-06-28 21:50:06 +000013#include <malloc.h>
14#include <mmc.h>
15#include <sdhci.h>
16
Stefan Roese492d3222015-06-29 14:58:09 +020017#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
18void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
19#else
Lei Wenaf62a552011-06-28 21:50:06 +000020void *aligned_buffer;
Stefan Roese492d3222015-06-29 14:58:09 +020021#endif
Lei Wenaf62a552011-06-28 21:50:06 +000022
23static void sdhci_reset(struct sdhci_host *host, u8 mask)
24{
25 unsigned long timeout;
26
27 /* Wait max 100 ms */
28 timeout = 100;
29 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
30 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
31 if (timeout == 0) {
Darwin Rambo30e6d972013-12-19 15:13:25 -080032 printf("%s: Reset 0x%x never completed.\n",
33 __func__, (int)mask);
Lei Wenaf62a552011-06-28 21:50:06 +000034 return;
35 }
36 timeout--;
37 udelay(1000);
38 }
39}
40
41static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
42{
43 int i;
44 if (cmd->resp_type & MMC_RSP_136) {
45 /* CRC is stripped so we need to do some shifting. */
46 for (i = 0; i < 4; i++) {
47 cmd->response[i] = sdhci_readl(host,
48 SDHCI_RESPONSE + (3-i)*4) << 8;
49 if (i != 3)
50 cmd->response[i] |= sdhci_readb(host,
51 SDHCI_RESPONSE + (3-i)*4-1);
52 }
53 } else {
54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
55 }
56}
57
58static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
59{
60 int i;
61 char *offs;
62 for (i = 0; i < data->blocksize; i += 4) {
63 offs = data->dest + i;
64 if (data->flags == MMC_DATA_READ)
65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
66 else
67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
68 }
69}
70
71static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
72 unsigned int start_addr)
73{
Lei Wena004abd2011-10-08 04:14:57 +000074 unsigned int stat, rdy, mask, timeout, block = 0;
Alex Deymo7dde50d2017-04-02 01:24:34 -070075 bool transfer_done = false;
Masahiro Yamada45a68fe2016-12-07 22:10:29 +090076#ifdef CONFIG_MMC_SDHCI_SDMA
Jaehoon Chung804c7f42012-09-20 20:31:55 +000077 unsigned char ctrl;
Juhyun \(Justin\) Oh2c011842013-09-13 18:06:00 +000078 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
Jaehoon Chung804c7f42012-09-20 20:31:55 +000079 ctrl &= ~SDHCI_CTRL_DMA_MASK;
Juhyun \(Justin\) Oh2c011842013-09-13 18:06:00 +000080 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Jaehoon Chung804c7f42012-09-20 20:31:55 +000081#endif
Lei Wenaf62a552011-06-28 21:50:06 +000082
Jaehoon Chung5d48e422012-09-20 20:31:54 +000083 timeout = 1000000;
Lei Wenaf62a552011-06-28 21:50:06 +000084 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
85 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
86 do {
87 stat = sdhci_readl(host, SDHCI_INT_STATUS);
88 if (stat & SDHCI_INT_ERROR) {
Darwin Rambo30e6d972013-12-19 15:13:25 -080089 printf("%s: Error detected in status(0x%X)!\n",
90 __func__, stat);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +090091 return -EIO;
Lei Wenaf62a552011-06-28 21:50:06 +000092 }
Alex Deymo7dde50d2017-04-02 01:24:34 -070093 if (!transfer_done && (stat & rdy)) {
Lei Wenaf62a552011-06-28 21:50:06 +000094 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
95 continue;
96 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
97 sdhci_transfer_pio(host, data);
98 data->dest += data->blocksize;
Alex Deymo7dde50d2017-04-02 01:24:34 -070099 if (++block >= data->blocks) {
100 /* Keep looping until the SDHCI_INT_DATA_END is
101 * cleared, even if we finished sending all the
102 * blocks.
103 */
104 transfer_done = true;
105 continue;
106 }
Lei Wenaf62a552011-06-28 21:50:06 +0000107 }
Masahiro Yamada45a68fe2016-12-07 22:10:29 +0900108#ifdef CONFIG_MMC_SDHCI_SDMA
Alex Deymo7dde50d2017-04-02 01:24:34 -0700109 if (!transfer_done && (stat & SDHCI_INT_DMA_END)) {
Lei Wenaf62a552011-06-28 21:50:06 +0000110 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
Lei Wen3e81c772011-10-08 04:14:58 +0000111 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
Lei Wenaf62a552011-06-28 21:50:06 +0000112 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
113 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
114 }
115#endif
Lei Wena004abd2011-10-08 04:14:57 +0000116 if (timeout-- > 0)
117 udelay(10);
118 else {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800119 printf("%s: Transfer data timeout\n", __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900120 return -ETIMEDOUT;
Lei Wena004abd2011-10-08 04:14:57 +0000121 }
Lei Wenaf62a552011-06-28 21:50:06 +0000122 } while (!(stat & SDHCI_INT_DATA_END));
123 return 0;
124}
125
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200126/*
127 * No command will be sent by driver if card is busy, so driver must wait
128 * for card ready state.
129 * Every time when card is busy after timeout then (last) timeout value will be
130 * increased twice but only if it doesn't exceed global defined maximum.
Masahiro Yamada65a25b22016-08-25 16:07:39 +0900131 * Each function call will use last timeout value.
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200132 */
Masahiro Yamada65a25b22016-08-25 16:07:39 +0900133#define SDHCI_CMD_MAX_TIMEOUT 3200
Masahiro Yamadad8ce77b2016-08-25 16:07:38 +0900134#define SDHCI_CMD_DEFAULT_TIMEOUT 100
Steve Raed90bb432016-06-29 13:42:01 -0700135#define SDHCI_READ_STATUS_TIMEOUT 1000
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200136
Simon Glasse7881d82017-07-29 11:35:31 -0600137#ifdef CONFIG_DM_MMC
Simon Glassef1e4ed2016-06-12 23:30:28 -0600138static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
139 struct mmc_data *data)
Lei Wenaf62a552011-06-28 21:50:06 +0000140{
Simon Glassef1e4ed2016-06-12 23:30:28 -0600141 struct mmc *mmc = mmc_get_mmc_dev(dev);
142
143#else
144static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
145 struct mmc_data *data)
146{
147#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200148 struct sdhci_host *host = mmc->priv;
Lei Wenaf62a552011-06-28 21:50:06 +0000149 unsigned int stat = 0;
150 int ret = 0;
151 int trans_bytes = 0, is_aligned = 1;
152 u32 mask, flags, mode;
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200153 unsigned int time = 0, start_addr = 0;
Simon Glass19d2e342016-05-14 14:03:04 -0600154 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
Stefan Roese29905a42015-06-29 14:58:08 +0200155 unsigned start = get_timer(0);
Lei Wenaf62a552011-06-28 21:50:06 +0000156
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200157 /* Timeout unit - ms */
Masahiro Yamadad8ce77b2016-08-25 16:07:38 +0900158 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
Lei Wenaf62a552011-06-28 21:50:06 +0000159
160 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
161 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
162
163 /* We shouldn't wait for data inihibit for stop commands, even
164 though they might use busy signaling */
165 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
166 mask &= ~SDHCI_DATA_INHIBIT;
167
168 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200169 if (time >= cmd_timeout) {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800170 printf("%s: MMC: %d busy ", __func__, mmc_dev);
Masahiro Yamada65a25b22016-08-25 16:07:39 +0900171 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200172 cmd_timeout += cmd_timeout;
173 printf("timeout increasing to: %u ms.\n",
174 cmd_timeout);
175 } else {
176 puts("timeout.\n");
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900177 return -ECOMM;
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200178 }
Lei Wenaf62a552011-06-28 21:50:06 +0000179 }
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200180 time++;
Lei Wenaf62a552011-06-28 21:50:06 +0000181 udelay(1000);
182 }
183
184 mask = SDHCI_INT_RESPONSE;
185 if (!(cmd->resp_type & MMC_RSP_PRESENT))
186 flags = SDHCI_CMD_RESP_NONE;
187 else if (cmd->resp_type & MMC_RSP_136)
188 flags = SDHCI_CMD_RESP_LONG;
189 else if (cmd->resp_type & MMC_RSP_BUSY) {
190 flags = SDHCI_CMD_RESP_SHORT_BUSY;
Jaehoon Chung17ea3c82016-07-12 21:18:46 +0900191 if (data)
192 mask |= SDHCI_INT_DATA_END;
Lei Wenaf62a552011-06-28 21:50:06 +0000193 } else
194 flags = SDHCI_CMD_RESP_SHORT;
195
196 if (cmd->resp_type & MMC_RSP_CRC)
197 flags |= SDHCI_CMD_CRC;
198 if (cmd->resp_type & MMC_RSP_OPCODE)
199 flags |= SDHCI_CMD_INDEX;
200 if (data)
201 flags |= SDHCI_CMD_DATA;
202
Darwin Rambo30e6d972013-12-19 15:13:25 -0800203 /* Set Transfer mode regarding to data flag */
Lei Wenaf62a552011-06-28 21:50:06 +0000204 if (data != 0) {
205 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
206 mode = SDHCI_TRNS_BLK_CNT_EN;
207 trans_bytes = data->blocks * data->blocksize;
208 if (data->blocks > 1)
209 mode |= SDHCI_TRNS_MULTI;
210
211 if (data->flags == MMC_DATA_READ)
212 mode |= SDHCI_TRNS_READ;
213
Masahiro Yamada45a68fe2016-12-07 22:10:29 +0900214#ifdef CONFIG_MMC_SDHCI_SDMA
Lei Wenaf62a552011-06-28 21:50:06 +0000215 if (data->flags == MMC_DATA_READ)
Rob Herring3c1fcb72015-03-17 15:46:38 -0500216 start_addr = (unsigned long)data->dest;
Lei Wenaf62a552011-06-28 21:50:06 +0000217 else
Rob Herring3c1fcb72015-03-17 15:46:38 -0500218 start_addr = (unsigned long)data->src;
Lei Wenaf62a552011-06-28 21:50:06 +0000219 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
220 (start_addr & 0x7) != 0x0) {
221 is_aligned = 0;
Rob Herring3c1fcb72015-03-17 15:46:38 -0500222 start_addr = (unsigned long)aligned_buffer;
Lei Wenaf62a552011-06-28 21:50:06 +0000223 if (data->flags != MMC_DATA_READ)
224 memcpy(aligned_buffer, data->src, trans_bytes);
225 }
226
Stefan Roese492d3222015-06-29 14:58:09 +0200227#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
228 /*
229 * Always use this bounce-buffer when
230 * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
231 */
232 is_aligned = 0;
233 start_addr = (unsigned long)aligned_buffer;
234 if (data->flags != MMC_DATA_READ)
235 memcpy(aligned_buffer, data->src, trans_bytes);
236#endif
237
Lei Wenaf62a552011-06-28 21:50:06 +0000238 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
239 mode |= SDHCI_TRNS_DMA;
240#endif
241 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
242 data->blocksize),
243 SDHCI_BLOCK_SIZE);
244 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
245 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
Kevin Liu5e1c23c2015-03-23 17:57:00 -0500246 } else if (cmd->resp_type & MMC_RSP_BUSY) {
247 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
Lei Wenaf62a552011-06-28 21:50:06 +0000248 }
249
250 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
Masahiro Yamada45a68fe2016-12-07 22:10:29 +0900251#ifdef CONFIG_MMC_SDHCI_SDMA
Kevin Liufa7720b2017-03-08 15:16:44 +0800252 if (data != 0) {
253 trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE);
254 flush_cache(start_addr, trans_bytes);
255 }
Lei Wenaf62a552011-06-28 21:50:06 +0000256#endif
257 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
Stefan Roese29905a42015-06-29 14:58:08 +0200258 start = get_timer(0);
Lei Wenaf62a552011-06-28 21:50:06 +0000259 do {
260 stat = sdhci_readl(host, SDHCI_INT_STATUS);
261 if (stat & SDHCI_INT_ERROR)
262 break;
Lei Wenaf62a552011-06-28 21:50:06 +0000263
Masahiro Yamadabae4a1f2016-07-10 00:40:22 +0900264 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
265 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
266 return 0;
267 } else {
268 printf("%s: Timeout for status update!\n",
269 __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900270 return -ETIMEDOUT;
Masahiro Yamadabae4a1f2016-07-10 00:40:22 +0900271 }
Jaehoon Chung3a638322012-04-23 02:36:25 +0000272 }
Masahiro Yamadabae4a1f2016-07-10 00:40:22 +0900273 } while ((stat & mask) != mask);
Jaehoon Chung3a638322012-04-23 02:36:25 +0000274
Lei Wenaf62a552011-06-28 21:50:06 +0000275 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
276 sdhci_cmd_done(host, cmd);
277 sdhci_writel(host, mask, SDHCI_INT_STATUS);
278 } else
279 ret = -1;
280
281 if (!ret && data)
282 ret = sdhci_transfer_data(host, data, start_addr);
283
Tushar Behera13243f22012-09-20 20:31:57 +0000284 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
285 udelay(1000);
286
Lei Wenaf62a552011-06-28 21:50:06 +0000287 stat = sdhci_readl(host, SDHCI_INT_STATUS);
288 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
289 if (!ret) {
290 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
291 !is_aligned && (data->flags == MMC_DATA_READ))
292 memcpy(data->dest, aligned_buffer, trans_bytes);
293 return 0;
294 }
295
296 sdhci_reset(host, SDHCI_RESET_CMD);
297 sdhci_reset(host, SDHCI_RESET_DATA);
298 if (stat & SDHCI_INT_TIMEOUT)
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900299 return -ETIMEDOUT;
Lei Wenaf62a552011-06-28 21:50:06 +0000300 else
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900301 return -ECOMM;
Lei Wenaf62a552011-06-28 21:50:06 +0000302}
303
304static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
305{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200306 struct sdhci_host *host = mmc->priv;
Stefan Roese899fb9e2016-12-12 08:34:42 +0100307 unsigned int div, clk = 0, timeout;
Lei Wenaf62a552011-06-28 21:50:06 +0000308
Wenyou Yang79667b72015-09-22 14:59:25 +0800309 /* Wait max 20 ms */
310 timeout = 200;
311 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
312 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
313 if (timeout == 0) {
314 printf("%s: Timeout to wait cmd & data inhibit\n",
315 __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900316 return -EBUSY;
Wenyou Yang79667b72015-09-22 14:59:25 +0800317 }
318
319 timeout--;
320 udelay(100);
321 }
322
Stefan Roese899fb9e2016-12-12 08:34:42 +0100323 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
Lei Wenaf62a552011-06-28 21:50:06 +0000324
325 if (clock == 0)
326 return 0;
327
Jaehoon Chung113e5df2013-07-19 17:44:49 +0900328 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800329 /*
330 * Check if the Host Controller supports Programmable Clock
331 * Mode.
332 */
333 if (host->clk_mul) {
334 for (div = 1; div <= 1024; div++) {
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800335 if ((host->max_clk / div) <= clock)
Lei Wenaf62a552011-06-28 21:50:06 +0000336 break;
337 }
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800338
339 /*
340 * Set Programmable Clock Mode in the Clock
341 * Control register.
342 */
343 clk = SDHCI_PROG_CLOCK_MODE;
344 div--;
345 } else {
346 /* Version 3.00 divisors must be a multiple of 2. */
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100347 if (host->max_clk <= clock) {
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800348 div = 1;
349 } else {
350 for (div = 2;
351 div < SDHCI_MAX_DIV_SPEC_300;
352 div += 2) {
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100353 if ((host->max_clk / div) <= clock)
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800354 break;
355 }
356 }
357 div >>= 1;
Lei Wenaf62a552011-06-28 21:50:06 +0000358 }
359 } else {
360 /* Version 2.00 divisors must be a power of 2. */
361 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100362 if ((host->max_clk / div) <= clock)
Lei Wenaf62a552011-06-28 21:50:06 +0000363 break;
364 }
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800365 div >>= 1;
Lei Wenaf62a552011-06-28 21:50:06 +0000366 }
Lei Wenaf62a552011-06-28 21:50:06 +0000367
Masahiro Yamadabf9c4d12017-01-13 11:51:51 +0900368 if (host->ops && host->ops->set_clock)
Jaehoon Chung62226b62016-12-30 15:30:18 +0900369 host->ops->set_clock(host, div);
Jaehoon Chungb09ed6e2012-08-30 16:24:11 +0000370
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800371 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
Lei Wenaf62a552011-06-28 21:50:06 +0000372 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
373 << SDHCI_DIVIDER_HI_SHIFT;
374 clk |= SDHCI_CLOCK_INT_EN;
375 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
376
377 /* Wait max 20 ms */
378 timeout = 20;
379 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
380 & SDHCI_CLOCK_INT_STABLE)) {
381 if (timeout == 0) {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800382 printf("%s: Internal clock never stabilised.\n",
383 __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900384 return -EBUSY;
Lei Wenaf62a552011-06-28 21:50:06 +0000385 }
386 timeout--;
387 udelay(1000);
388 }
389
390 clk |= SDHCI_CLOCK_CARD_EN;
391 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
392 return 0;
393}
394
395static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
396{
397 u8 pwr = 0;
398
399 if (power != (unsigned short)-1) {
400 switch (1 << power) {
401 case MMC_VDD_165_195:
402 pwr = SDHCI_POWER_180;
403 break;
404 case MMC_VDD_29_30:
405 case MMC_VDD_30_31:
406 pwr = SDHCI_POWER_300;
407 break;
408 case MMC_VDD_32_33:
409 case MMC_VDD_33_34:
410 pwr = SDHCI_POWER_330;
411 break;
412 }
413 }
414
415 if (pwr == 0) {
416 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
417 return;
418 }
419
420 pwr |= SDHCI_POWER_ON;
421
422 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
423}
424
Simon Glasse7881d82017-07-29 11:35:31 -0600425#ifdef CONFIG_DM_MMC
Simon Glassef1e4ed2016-06-12 23:30:28 -0600426static int sdhci_set_ios(struct udevice *dev)
427{
428 struct mmc *mmc = mmc_get_mmc_dev(dev);
429#else
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900430static int sdhci_set_ios(struct mmc *mmc)
Lei Wenaf62a552011-06-28 21:50:06 +0000431{
Simon Glassef1e4ed2016-06-12 23:30:28 -0600432#endif
Lei Wenaf62a552011-06-28 21:50:06 +0000433 u32 ctrl;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200434 struct sdhci_host *host = mmc->priv;
Lei Wenaf62a552011-06-28 21:50:06 +0000435
Masahiro Yamadabf9c4d12017-01-13 11:51:51 +0900436 if (host->ops && host->ops->set_control_reg)
Jaehoon Chung62226b62016-12-30 15:30:18 +0900437 host->ops->set_control_reg(host);
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000438
Lei Wenaf62a552011-06-28 21:50:06 +0000439 if (mmc->clock != host->clock)
440 sdhci_set_clock(mmc, mmc->clock);
441
442 /* Set bus width */
443 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
444 if (mmc->bus_width == 8) {
445 ctrl &= ~SDHCI_CTRL_4BITBUS;
Jaehoon Chung113e5df2013-07-19 17:44:49 +0900446 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
447 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
Lei Wenaf62a552011-06-28 21:50:06 +0000448 ctrl |= SDHCI_CTRL_8BITBUS;
449 } else {
Matt Reimerf88a4292015-02-19 11:22:53 -0700450 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
451 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
Lei Wenaf62a552011-06-28 21:50:06 +0000452 ctrl &= ~SDHCI_CTRL_8BITBUS;
453 if (mmc->bus_width == 4)
454 ctrl |= SDHCI_CTRL_4BITBUS;
455 else
456 ctrl &= ~SDHCI_CTRL_4BITBUS;
457 }
458
459 if (mmc->clock > 26000000)
460 ctrl |= SDHCI_CTRL_HISPD;
461 else
462 ctrl &= ~SDHCI_CTRL_HISPD;
463
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000464 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
465 ctrl &= ~SDHCI_CTRL_HISPD;
466
Lei Wenaf62a552011-06-28 21:50:06 +0000467 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900468
Stefan Roese210841c2016-12-12 08:24:56 +0100469 /* If available, call the driver specific "post" set_ios() function */
470 if (host->ops && host->ops->set_ios_post)
471 host->ops->set_ios_post(host);
472
Simon Glassef1e4ed2016-06-12 23:30:28 -0600473 return 0;
Lei Wenaf62a552011-06-28 21:50:06 +0000474}
475
Jeroen Hofstee6588c782014-10-08 22:57:43 +0200476static int sdhci_init(struct mmc *mmc)
Lei Wenaf62a552011-06-28 21:50:06 +0000477{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200478 struct sdhci_host *host = mmc->priv;
Lei Wenaf62a552011-06-28 21:50:06 +0000479
Masahiro Yamada8d549b62016-08-25 16:07:34 +0900480 sdhci_reset(host, SDHCI_RESET_ALL);
481
Lei Wenaf62a552011-06-28 21:50:06 +0000482 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
483 aligned_buffer = memalign(8, 512*1024);
484 if (!aligned_buffer) {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800485 printf("%s: Aligned buffer alloc failed!!!\n",
486 __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900487 return -ENOMEM;
Lei Wenaf62a552011-06-28 21:50:06 +0000488 }
489 }
490
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200491 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
Joe Hershberger470dcc72012-08-17 10:18:55 +0000492
Masahiro Yamadabf9c4d12017-01-13 11:51:51 +0900493 if (host->ops && host->ops->get_cd)
Jaehoon Chung6f88a3a2016-12-30 15:30:15 +0900494 host->ops->get_cd(host);
Joe Hershberger470dcc72012-08-17 10:18:55 +0000495
Łukasz Majewskice0c1bc2013-01-11 05:08:54 +0000496 /* Enable only interrupts served by the SD controller */
Darwin Rambo30e6d972013-12-19 15:13:25 -0800497 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
498 SDHCI_INT_ENABLE);
Łukasz Majewskice0c1bc2013-01-11 05:08:54 +0000499 /* Mask all sdhci interrupt sources */
500 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
Lei Wenaf62a552011-06-28 21:50:06 +0000501
Lei Wenaf62a552011-06-28 21:50:06 +0000502 return 0;
503}
504
Simon Glasse7881d82017-07-29 11:35:31 -0600505#ifdef CONFIG_DM_MMC
Simon Glassef1e4ed2016-06-12 23:30:28 -0600506int sdhci_probe(struct udevice *dev)
507{
508 struct mmc *mmc = mmc_get_mmc_dev(dev);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200509
Simon Glassef1e4ed2016-06-12 23:30:28 -0600510 return sdhci_init(mmc);
511}
512
513const struct dm_mmc_ops sdhci_ops = {
514 .send_cmd = sdhci_send_command,
515 .set_ios = sdhci_set_ios,
516};
517#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200518static const struct mmc_ops sdhci_ops = {
519 .send_cmd = sdhci_send_command,
520 .set_ios = sdhci_set_ios,
521 .init = sdhci_init,
522};
Simon Glassef1e4ed2016-06-12 23:30:28 -0600523#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200524
Jaehoon Chung14bed522016-07-26 19:06:24 +0900525int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100526 u32 f_max, u32 f_min)
Simon Glass2a809092016-06-12 23:30:27 -0600527{
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800528 u32 caps, caps_1;
Jaehoon Chung14bed522016-07-26 19:06:24 +0900529
530 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
Masahiro Yamada15bd0992016-08-25 16:07:37 +0900531
Masahiro Yamada45a68fe2016-12-07 22:10:29 +0900532#ifdef CONFIG_MMC_SDHCI_SDMA
Masahiro Yamada15bd0992016-08-25 16:07:37 +0900533 if (!(caps & SDHCI_CAN_DO_SDMA)) {
534 printf("%s: Your controller doesn't support SDMA!!\n",
535 __func__);
536 return -EINVAL;
537 }
538#endif
Jaehoon Chung895549a2016-09-26 08:10:01 +0900539 if (host->quirks & SDHCI_QUIRK_REG32_RW)
540 host->version =
541 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
542 else
543 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
Jaehoon Chung14bed522016-07-26 19:06:24 +0900544
545 cfg->name = host->name;
Simon Glasse7881d82017-07-29 11:35:31 -0600546#ifndef CONFIG_DM_MMC
Simon Glass2a809092016-06-12 23:30:27 -0600547 cfg->ops = &sdhci_ops;
548#endif
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800549
550 /* Check whether the clock multiplier is supported or not */
551 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
552 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
553 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
554 SDHCI_CLOCK_MUL_SHIFT;
555 }
556
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100557 if (host->max_clk == 0) {
Jaehoon Chung14bed522016-07-26 19:06:24 +0900558 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100559 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
Simon Glass2a809092016-06-12 23:30:27 -0600560 SDHCI_CLOCK_BASE_SHIFT;
561 else
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100562 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
Simon Glass2a809092016-06-12 23:30:27 -0600563 SDHCI_CLOCK_BASE_SHIFT;
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100564 host->max_clk *= 1000000;
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800565 if (host->clk_mul)
566 host->max_clk *= host->clk_mul;
Simon Glass2a809092016-06-12 23:30:27 -0600567 }
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100568 if (host->max_clk == 0) {
Masahiro Yamada6c679542016-08-25 16:07:35 +0900569 printf("%s: Hardware doesn't specify base clock frequency\n",
570 __func__);
Simon Glass2a809092016-06-12 23:30:27 -0600571 return -EINVAL;
Masahiro Yamada6c679542016-08-25 16:07:35 +0900572 }
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100573 if (f_max && (f_max < host->max_clk))
574 cfg->f_max = f_max;
575 else
576 cfg->f_max = host->max_clk;
577 if (f_min)
578 cfg->f_min = f_min;
Simon Glass2a809092016-06-12 23:30:27 -0600579 else {
Jaehoon Chung14bed522016-07-26 19:06:24 +0900580 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
Simon Glass2a809092016-06-12 23:30:27 -0600581 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
582 else
583 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
584 }
585 cfg->voltages = 0;
586 if (caps & SDHCI_CAN_VDD_330)
587 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
588 if (caps & SDHCI_CAN_VDD_300)
589 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
590 if (caps & SDHCI_CAN_VDD_180)
591 cfg->voltages |= MMC_VDD_165_195;
592
Masahiro Yamada3137e642016-08-25 16:07:36 +0900593 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
594 cfg->voltages |= host->voltages;
595
Simon Glass2a809092016-06-12 23:30:27 -0600596 cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
Jaehoon Chung3fd0a9b2016-12-30 15:30:21 +0900597
598 /* Since Host Controller Version3.0 */
Jaehoon Chung14bed522016-07-26 19:06:24 +0900599 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Jaehoon Chungecd7b242016-12-30 15:30:11 +0900600 if (!(caps & SDHCI_CAN_DO_8BIT))
601 cfg->host_caps &= ~MMC_MODE_8BIT;
Simon Glass2a809092016-06-12 23:30:27 -0600602 }
603
Jaehoon Chung14bed522016-07-26 19:06:24 +0900604 if (host->host_caps)
605 cfg->host_caps |= host->host_caps;
Simon Glass2a809092016-06-12 23:30:27 -0600606
607 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
608
609 return 0;
610}
611
Simon Glassef1e4ed2016-06-12 23:30:28 -0600612#ifdef CONFIG_BLK
613int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
614{
615 return mmc_bind(dev, mmc, cfg);
616}
617#else
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100618int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
Lei Wenaf62a552011-06-28 21:50:06 +0000619{
Masahiro Yamada6c679542016-08-25 16:07:35 +0900620 int ret;
621
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100622 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
Masahiro Yamada6c679542016-08-25 16:07:35 +0900623 if (ret)
624 return ret;
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000625
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200626 host->mmc = mmc_create(&host->cfg, host);
627 if (host->mmc == NULL) {
628 printf("%s: mmc create fail!\n", __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900629 return -ENOMEM;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200630 }
Lei Wenaf62a552011-06-28 21:50:06 +0000631
632 return 0;
633}
Simon Glassef1e4ed2016-06-12 23:30:28 -0600634#endif