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Stefan Roesec157d8e2005-08-01 16:41:48 +02001/*
Stefan Roese700200c2007-01-30 17:04:19 +01002 * (C) Copyright 2005-2007
Stefan Roese84286382005-08-11 18:03:14 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
Stefan Roesec157d8e2005-08-01 16:41:48 +02004 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roesec157d8e2005-08-01 16:41:48 +02006 */
7
8/************************************************************************
Stefan Roese700200c2007-01-30 17:04:19 +01009 * yosemite.h - configuration for Yosemite & Yellowstone boards
Stefan Roesec157d8e2005-08-01 16:41:48 +020010 ***********************************************************************/
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*-----------------------------------------------------------------------
15 * High Level Configuration Options
16 *----------------------------------------------------------------------*/
Stefan Roese700200c2007-01-30 17:04:19 +010017/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/
18#ifndef CONFIG_YELLOWSTONE
Stefan Roese700200c2007-01-30 17:04:19 +010019#define CONFIG_440EP 1 /* Specific PPC440EP support */
20#define CONFIG_HOSTNAME yosemite
21#else
22#define CONFIG_440GR 1 /* Specific PPC440GR support */
23#define CONFIG_HOSTNAME yellowstone
24#endif
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020025#define CONFIG_440 1 /* ... PPC440 family */
Stefan Roesec157d8e2005-08-01 16:41:48 +020026#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */
27
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028#define CONFIG_SYS_TEXT_BASE 0xFFF80000
29
Stefan Roese72675dc2008-06-06 15:55:21 +020030/*
31 * Include common defines/options for all AMCC eval boards
32 */
33#include "amcc-common.h"
34
Stefan Roese84286382005-08-11 18:03:14 +020035#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
36#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
Stefan Roesef3443862006-10-07 11:30:52 +020037#define CONFIG_BOARD_RESET 1 /* call board_reset() */
Stefan Roese84286382005-08-11 18:03:14 +020038
Stefan Roesec157d8e2005-08-01 16:41:48 +020039/*-----------------------------------------------------------------------
40 * Base addresses -- Note these are effective addresses where the
41 * actual resources get mapped (not physical addresses)
42 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
44#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
45#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
46#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
47#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
Stefan Roesec157d8e2005-08-01 16:41:48 +020048
49/*Don't change either of these*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/
Stefan Roesec157d8e2005-08-01 16:41:48 +020051/*Don't change either of these*/
52
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_USB_DEVICE 0x50000000
54#define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000
55#define CONFIG_SYS_BCSR_BASE (CONFIG_SYS_NVRAM_BASE_ADDR | 0x2000)
56#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
Stefan Roesec157d8e2005-08-01 16:41:48 +020057
58/*-----------------------------------------------------------------------
59 * Initial RAM & stack pointer (placed in SDRAM)
60 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
62#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
Wolfgang Denk553f0982010-10-26 13:32:32 +020063#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020064#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roesec157d8e2005-08-01 16:41:48 +020066
Stefan Roesec157d8e2005-08-01 16:41:48 +020067/*-----------------------------------------------------------------------
68 * Serial Port
69 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020070#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */
Stefan Roesec157d8e2005-08-01 16:41:48 +020072
Stefan Roesec157d8e2005-08-01 16:41:48 +020073/*-----------------------------------------------------------------------
Stefan Roese84286382005-08-11 18:03:14 +020074 * Environment
Stefan Roesec157d8e2005-08-01 16:41:48 +020075 *----------------------------------------------------------------------*/
Stefan Roese84286382005-08-11 18:03:14 +020076/*
77 * Define here the location of the environment variables (FLASH or EEPROM).
78 * Note: DENX encourages to use redundant environment in FLASH.
79 */
80#if 1
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020081#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese84286382005-08-11 18:03:14 +020082#else
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020083#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Stefan Roese84286382005-08-11 18:03:14 +020084#endif
Stefan Roesec157d8e2005-08-01 16:41:48 +020085
86/*-----------------------------------------------------------------------
87 * FLASH related
88 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020090#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
Stefan Roesec157d8e2005-08-01 16:41:48 +020092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
94#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roesec157d8e2005-08-01 16:41:48 +020095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
97#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roesec157d8e2005-08-01 16:41:48 +020098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Stefan Roese278bc4b2006-05-10 15:06:58 +0200100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese84286382005-08-11 18:03:14 +0200102
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200103#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200104#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200106#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roese84286382005-08-11 18:03:14 +0200107
108/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200109#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
110#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200111#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200112
113/*-----------------------------------------------------------------------
114 * DDR SDRAM
115 *----------------------------------------------------------------------*/
Wolfgang Denk095b8a32005-08-02 17:06:17 +0200116#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */
118#define CONFIG_SYS_SDRAM_BANKS (2)
Stefan Roese84286382005-08-11 18:03:14 +0200119
Ira Snyder4adb3022008-04-29 11:18:54 -0700120/*-----------------------------------------------------------------------
Stefan Roesec157d8e2005-08-01 16:41:48 +0200121 * I2C
122 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000123#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roesec157d8e2005-08-01 16:41:48 +0200124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
126#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
127#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
128#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roesec157d8e2005-08-01 16:41:48 +0200129
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200130#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200131#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */
132#define CONFIG_ENV_OFFSET 0x0
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200133#endif /* CONFIG_ENV_IS_IN_EEPROM */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200134
Stefan Roesea90921f2007-12-04 16:29:48 +0100135/* I2C SYSMON (LM75, AD7414 is almost compatible) */
136#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
137#define CONFIG_DTT_AD7414 1 /* use AD7414 */
138#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_DTT_MAX_TEMP 70
140#define CONFIG_SYS_DTT_LOW_TEMP -30
141#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roesea90921f2007-12-04 16:29:48 +0100142
Stefan Roese72675dc2008-06-06 15:55:21 +0200143/*
144 * Default environment variables
145 */
Stefan Roese84286382005-08-11 18:03:14 +0200146#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese72675dc2008-06-06 15:55:21 +0200147 CONFIG_AMCC_DEF_ENV \
148 CONFIG_AMCC_DEF_ENV_POWERPC \
149 CONFIG_AMCC_DEF_ENV_PPC_OLD \
150 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese84286382005-08-11 18:03:14 +0200151 "kernel_addr=fc000000\0" \
Stefan Roese56ced702006-05-15 15:11:20 +0200152 "ramdisk_addr=fc180000\0" \
Stefan Roese84286382005-08-11 18:03:14 +0200153 ""
Stefan Roese84286382005-08-11 18:03:14 +0200154
Ira Snyder4adb3022008-04-29 11:18:54 -0700155#define CONFIG_HAS_ETH0 1 /* add support for "ethaddr" */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200156#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
157#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
Stefan Roese72675dc2008-06-06 15:55:21 +0200158#define CONFIG_PHY1_ADDR 3
Stefan Roesec157d8e2005-08-01 16:41:48 +0200159
160/* Partitions */
161#define CONFIG_MAC_PARTITION
162#define CONFIG_DOS_PARTITION
163#define CONFIG_ISO_PARTITION
164
Stefan Roese846b0dd2005-08-08 12:42:22 +0200165#ifdef CONFIG_440EP
Stefan Roesec157d8e2005-08-01 16:41:48 +0200166/* USB */
Markus Klotzbuecher7b59b3c2006-11-27 11:44:58 +0100167#define CONFIG_USB_OHCI_NEW
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_OHCI_BE_CONTROLLER
Stefan Roesec157d8e2005-08-01 16:41:48 +0200169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
171#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
172#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_PERIPHERAL_BASE | 0x1000)
173#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
174#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
Markus Klotzbuecher53e336e2006-11-27 11:43:09 +0100175
Stefan Roese700200c2007-01-30 17:04:19 +0100176/* Comment this out to enable USB 1.1 device */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200177#define USB_2_0_DEVICE
Stefan Roese700200c2007-01-30 17:04:19 +0100178
Stefan Roese700200c2007-01-30 17:04:19 +0100179#define CONFIG_SUPPORT_VFAT
Stefan Roese700200c2007-01-30 17:04:19 +0100180#endif /* CONFIG_440EP */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200181
182#ifdef DEBUG
183#define CONFIG_PANIC_HANG
184#else
185#define CONFIG_HW_WATCHDOG /* watchdog */
186#endif
187
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500188/*
Stefan Roese72675dc2008-06-06 15:55:21 +0200189 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger079a1362007-07-10 10:12:10 -0500190 */
Stefan Roesea90921f2007-12-04 16:29:48 +0100191#define CONFIG_CMD_DTT
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500192#define CONFIG_CMD_PCI
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500193
194#ifdef CONFIG_440EP
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500195#endif
196
Stefan Roesec157d8e2005-08-01 16:41:48 +0200197/*-----------------------------------------------------------------------
198 * PCI stuff
199 *-----------------------------------------------------------------------
200 */
201/* General PCI */
Gabor Juhos842033e2013-05-30 07:06:12 +0000202#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese84286382005-08-11 18:03:14 +0200203#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
Stefan Roesec157d8e2005-08-01 16:41:48 +0200205
206/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_PCI_TARGET_INIT
208#define CONFIG_SYS_PCI_MASTER_INIT
Stefan Roesec157d8e2005-08-01 16:41:48 +0200209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
211#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200212
Stefan Roesec157d8e2005-08-01 16:41:48 +0200213/*-----------------------------------------------------------------------
Stefan Roese36adff32007-01-13 07:59:19 +0100214 * External Bus Controller (EBC) Setup
215 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
217#define CONFIG_SYS_CPLD 0x80000000
Stefan Roese36adff32007-01-13 07:59:19 +0100218
219/* Memory Bank 0 (NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_EBC_PB0AP 0x03017300
221#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000)
Stefan Roese36adff32007-01-13 07:59:19 +0100222
223/* Memory Bank 2 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_EBC_PB2AP 0x04814500
225#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD | 0x18000)
Stefan Roese36adff32007-01-13 07:59:19 +0100226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_BCSR5_PCI66EN 0x80
Stefan Roese5a5958b2007-10-15 11:29:33 +0200228
Stefan Roesec157d8e2005-08-01 16:41:48 +0200229#endif /* __CONFIG_H */