Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Thomas Chou <thomas@wytron.com.tw> |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
Patrick Delaunay | b953ec2 | 2021-04-27 11:02:19 +0200 | [diff] [blame] | 6 | #define LOG_CATEGORY UCLASS_TIMER |
| 7 | |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 8 | #include <common.h> |
Sean Anderson | a5d4f86 | 2020-10-04 21:39:52 -0400 | [diff] [blame] | 9 | #include <clk.h> |
Sean Anderson | 3576121 | 2020-09-28 10:52:22 -0400 | [diff] [blame] | 10 | #include <cpu.h> |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 11 | #include <dm.h> |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 12 | #include <asm/global_data.h> |
Mugunthan V N | c833697 | 2016-01-16 21:33:58 +0530 | [diff] [blame] | 13 | #include <dm/lists.h> |
Sean Anderson | a5d4f86 | 2020-10-04 21:39:52 -0400 | [diff] [blame] | 14 | #include <dm/device_compat.h> |
Mugunthan V N | c833697 | 2016-01-16 21:33:58 +0530 | [diff] [blame] | 15 | #include <dm/device-internal.h> |
Philipp Tomsich | b61e8b0 | 2017-09-11 22:04:10 +0200 | [diff] [blame] | 16 | #include <dm/root.h> |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 17 | #include <errno.h> |
Sean Anderson | a5d4f86 | 2020-10-04 21:39:52 -0400 | [diff] [blame] | 18 | #include <init.h> |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 19 | #include <timer.h> |
Simon Glass | 61b29b8 | 2020-02-03 07:36:15 -0700 | [diff] [blame] | 20 | #include <linux/err.h> |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 21 | |
Bin Meng | 579eb5a | 2015-11-13 00:11:15 -0800 | [diff] [blame] | 22 | DECLARE_GLOBAL_DATA_PTR; |
| 23 | |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 24 | /* |
Bin Meng | 435ae76 | 2015-11-13 00:11:14 -0800 | [diff] [blame] | 25 | * Implement a timer uclass to work with lib/time.c. The timer is usually |
Bin Meng | 9ca07eb | 2015-11-24 13:31:17 -0700 | [diff] [blame] | 26 | * a 32/64 bits free-running up counter. The get_rate() method is used to get |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 27 | * the input clock frequency of the timer. The get_count() method is used |
Bin Meng | 9ca07eb | 2015-11-24 13:31:17 -0700 | [diff] [blame] | 28 | * to get the current 64 bits count value. If the hardware is counting down, |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 29 | * the value should be inversed inside the method. There may be no real |
| 30 | * tick, and no timer interrupt. |
| 31 | */ |
| 32 | |
Simon Glass | 4f05182 | 2016-02-24 09:14:48 -0700 | [diff] [blame] | 33 | int notrace timer_get_count(struct udevice *dev, u64 *count) |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 34 | { |
| 35 | const struct timer_ops *ops = device_get_ops(dev); |
| 36 | |
| 37 | if (!ops->get_count) |
| 38 | return -ENOSYS; |
| 39 | |
Sean Anderson | 8af7bb9 | 2020-10-07 14:37:44 -0400 | [diff] [blame] | 40 | *count = ops->get_count(dev); |
| 41 | return 0; |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 42 | } |
| 43 | |
Simon Glass | 4f05182 | 2016-02-24 09:14:48 -0700 | [diff] [blame] | 44 | unsigned long notrace timer_get_rate(struct udevice *dev) |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 45 | { |
Simon Glass | 0fd3d91 | 2020-12-22 19:30:28 -0700 | [diff] [blame] | 46 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 47 | |
| 48 | return uc_priv->clock_rate; |
| 49 | } |
| 50 | |
Bin Meng | 579eb5a | 2015-11-13 00:11:15 -0800 | [diff] [blame] | 51 | static int timer_pre_probe(struct udevice *dev) |
| 52 | { |
Simon Glass | dcfc42b | 2021-08-07 07:24:06 -0600 | [diff] [blame] | 53 | if (CONFIG_IS_ENABLED(OF_REAL)) { |
| 54 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
| 55 | struct clk timer_clk; |
| 56 | int err; |
| 57 | ulong ret; |
Bin Meng | 579eb5a | 2015-11-13 00:11:15 -0800 | [diff] [blame] | 58 | |
Simon Glass | dcfc42b | 2021-08-07 07:24:06 -0600 | [diff] [blame] | 59 | /* |
| 60 | * It is possible that a timer device has a null ofnode |
| 61 | */ |
| 62 | if (!dev_has_ofnode(dev)) |
| 63 | return 0; |
Bin Meng | 7efb4a6 | 2019-07-05 09:23:15 -0700 | [diff] [blame] | 64 | |
Simon Glass | dcfc42b | 2021-08-07 07:24:06 -0600 | [diff] [blame] | 65 | err = clk_get_by_index(dev, 0, &timer_clk); |
| 66 | if (!err) { |
| 67 | ret = clk_get_rate(&timer_clk); |
| 68 | if (IS_ERR_VALUE(ret)) |
| 69 | return ret; |
| 70 | uc_priv->clock_rate = ret; |
| 71 | } else { |
| 72 | uc_priv->clock_rate = |
| 73 | dev_read_u32_default(dev, "clock-frequency", 0); |
| 74 | } |
Philipp Tomsich | b61e8b0 | 2017-09-11 22:04:10 +0200 | [diff] [blame] | 75 | } |
Bin Meng | 579eb5a | 2015-11-13 00:11:15 -0800 | [diff] [blame] | 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
Stephen Warren | 0a7edce | 2016-01-06 10:33:03 -0700 | [diff] [blame] | 80 | static int timer_post_probe(struct udevice *dev) |
| 81 | { |
| 82 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
| 83 | |
| 84 | if (!uc_priv->clock_rate) |
| 85 | return -EINVAL; |
| 86 | |
| 87 | return 0; |
| 88 | } |
| 89 | |
Simon Glass | 529d5f9 | 2021-03-15 18:11:18 +1300 | [diff] [blame] | 90 | #if CONFIG_IS_ENABLED(CPU) |
Sean Anderson | 3576121 | 2020-09-28 10:52:22 -0400 | [diff] [blame] | 91 | int timer_timebase_fallback(struct udevice *dev) |
| 92 | { |
| 93 | struct udevice *cpu; |
Simon Glass | 8a8d24b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 94 | struct cpu_plat *cpu_plat; |
Sean Anderson | 3576121 | 2020-09-28 10:52:22 -0400 | [diff] [blame] | 95 | struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); |
| 96 | |
| 97 | /* Did we get our clock rate from the device tree? */ |
| 98 | if (uc_priv->clock_rate) |
| 99 | return 0; |
| 100 | |
| 101 | /* Fall back to timebase-frequency */ |
| 102 | dev_dbg(dev, "missing clocks or clock-frequency property; falling back on timebase-frequency\n"); |
| 103 | cpu = cpu_get_current_dev(); |
| 104 | if (!cpu) |
| 105 | return -ENODEV; |
| 106 | |
Simon Glass | caa4daa | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 107 | cpu_plat = dev_get_parent_plat(cpu); |
Sean Anderson | 3576121 | 2020-09-28 10:52:22 -0400 | [diff] [blame] | 108 | if (!cpu_plat) |
| 109 | return -ENODEV; |
| 110 | |
| 111 | uc_priv->clock_rate = cpu_plat->timebase_freq; |
| 112 | return 0; |
| 113 | } |
| 114 | #endif |
| 115 | |
Bin Meng | 9ca07eb | 2015-11-24 13:31:17 -0700 | [diff] [blame] | 116 | u64 timer_conv_64(u32 count) |
| 117 | { |
| 118 | /* increment tbh if tbl has rolled over */ |
| 119 | if (count < gd->timebase_l) |
| 120 | gd->timebase_h++; |
| 121 | gd->timebase_l = count; |
| 122 | return ((u64)gd->timebase_h << 32) | gd->timebase_l; |
| 123 | } |
| 124 | |
Mugunthan V N | c833697 | 2016-01-16 21:33:58 +0530 | [diff] [blame] | 125 | int notrace dm_timer_init(void) |
| 126 | { |
Mugunthan V N | c833697 | 2016-01-16 21:33:58 +0530 | [diff] [blame] | 127 | struct udevice *dev = NULL; |
Philipp Tomsich | b61e8b0 | 2017-09-11 22:04:10 +0200 | [diff] [blame] | 128 | __maybe_unused ofnode node; |
Mugunthan V N | c833697 | 2016-01-16 21:33:58 +0530 | [diff] [blame] | 129 | int ret; |
| 130 | |
| 131 | if (gd->timer) |
| 132 | return 0; |
| 133 | |
Philipp Tomsich | af82315 | 2017-09-11 22:04:11 +0200 | [diff] [blame] | 134 | /* |
| 135 | * Directly access gd->dm_root to suppress error messages, if the |
| 136 | * virtual root driver does not yet exist. |
| 137 | */ |
| 138 | if (gd->dm_root == NULL) |
| 139 | return -EAGAIN; |
| 140 | |
Simon Glass | dcfc42b | 2021-08-07 07:24:06 -0600 | [diff] [blame] | 141 | if (CONFIG_IS_ENABLED(OF_REAL)) { |
| 142 | /* Check for a chosen timer to be used for tick */ |
| 143 | node = ofnode_get_chosen_node("tick-timer"); |
Philipp Tomsich | b61e8b0 | 2017-09-11 22:04:10 +0200 | [diff] [blame] | 144 | |
Simon Glass | dcfc42b | 2021-08-07 07:24:06 -0600 | [diff] [blame] | 145 | if (ofnode_valid(node) && |
| 146 | uclass_get_device_by_ofnode(UCLASS_TIMER, node, &dev)) { |
| 147 | /* |
| 148 | * If the timer is not marked to be bound before |
| 149 | * relocation, bind it anyway. |
| 150 | */ |
Tom Rini | 776bf6a | 2021-10-12 12:01:00 -0400 | [diff] [blame] | 151 | if (!lists_bind_fdt(dm_root(), node, &dev, NULL, false)) { |
Simon Glass | dcfc42b | 2021-08-07 07:24:06 -0600 | [diff] [blame] | 152 | ret = device_probe(dev); |
| 153 | if (ret) |
| 154 | return ret; |
| 155 | } |
Philipp Tomsich | b61e8b0 | 2017-09-11 22:04:10 +0200 | [diff] [blame] | 156 | } |
| 157 | } |
Philipp Tomsich | b61e8b0 | 2017-09-11 22:04:10 +0200 | [diff] [blame] | 158 | |
| 159 | if (!dev) { |
| 160 | /* Fall back to the first available timer */ |
Simon Glass | 3f603cb | 2016-02-11 13:23:26 -0700 | [diff] [blame] | 161 | ret = uclass_first_device_err(UCLASS_TIMER, &dev); |
Mugunthan V N | c833697 | 2016-01-16 21:33:58 +0530 | [diff] [blame] | 162 | if (ret) |
| 163 | return ret; |
Mugunthan V N | c833697 | 2016-01-16 21:33:58 +0530 | [diff] [blame] | 164 | } |
| 165 | |
| 166 | if (dev) { |
| 167 | gd->timer = dev; |
| 168 | return 0; |
| 169 | } |
| 170 | |
| 171 | return -ENODEV; |
| 172 | } |
| 173 | |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 174 | UCLASS_DRIVER(timer) = { |
| 175 | .id = UCLASS_TIMER, |
| 176 | .name = "timer", |
Bin Meng | 579eb5a | 2015-11-13 00:11:15 -0800 | [diff] [blame] | 177 | .pre_probe = timer_pre_probe, |
Mugunthan V N | a5d8011 | 2015-12-24 16:08:06 +0530 | [diff] [blame] | 178 | .flags = DM_UC_FLAG_SEQ_ALIAS, |
Stephen Warren | 0a7edce | 2016-01-06 10:33:03 -0700 | [diff] [blame] | 179 | .post_probe = timer_post_probe, |
Simon Glass | 41575d8 | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 180 | .per_device_auto = sizeof(struct timer_dev_priv), |
Thomas Chou | c8a7ba9 | 2015-10-09 13:46:34 +0800 | [diff] [blame] | 181 | }; |