blob: 1152bca03be6491b3e4deb94cedfaef9bb14d16e [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Poonam Aggrwal49249e12011-02-09 19:17:53 +00002/*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Poonam Aggrwal49249e12011-02-09 19:17:53 +00004 */
5
6/*
7 * P010 RDB board configuration file
8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Prabhakar Kushwaha74fa22e2013-04-16 13:27:44 +053013#include <asm/config_mpc85xx.h>
Dipen Dudhatd793e5a2011-07-28 14:47:28 -050014#define CONFIG_NAND_FSL_IFC
Poonam Aggrwal49249e12011-02-09 19:17:53 +000015
16#ifdef CONFIG_SDCARD
Ying Zhangc9e1f582014-01-24 15:50:09 +080017#define CONFIG_SPL_FLUSH_IMAGE
18#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhangc9e1f582014-01-24 15:50:09 +080019#define CONFIG_SPL_PAD_TO 0x18000
20#define CONFIG_SPL_MAX_SIZE (96 * 1024)
21#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10)
22#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
23#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
24#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10)
25#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Ying Zhangc9e1f582014-01-24 15:50:09 +080026#ifdef CONFIG_SPL_BUILD
27#define CONFIG_SPL_COMMON_INIT_DDR
28#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +000029#endif
30
31#ifdef CONFIG_SPIFLASH
Ying Zhangc9e1f582014-01-24 15:50:09 +080032#ifdef CONFIG_SECURE_BOOT
Poonam Aggrwal49249e12011-02-09 19:17:53 +000033#define CONFIG_RAMBOOT_SPIFLASH
Ruchika Gupta84e0fb42014-09-29 11:14:35 +053034#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Ying Zhangc9e1f582014-01-24 15:50:09 +080035#else
Ying Zhangc9e1f582014-01-24 15:50:09 +080036#define CONFIG_SPL_SPI_FLASH_MINIMAL
37#define CONFIG_SPL_FLUSH_IMAGE
38#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhangc9e1f582014-01-24 15:50:09 +080039#define CONFIG_SPL_PAD_TO 0x18000
40#define CONFIG_SPL_MAX_SIZE (96 * 1024)
41#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10)
42#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
43#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
44#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10)
45#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Ying Zhangc9e1f582014-01-24 15:50:09 +080046#ifdef CONFIG_SPL_BUILD
47#define CONFIG_SPL_COMMON_INIT_DDR
48#endif
49#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +000050#endif
51
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053052#ifdef CONFIG_NAND
Ying Zhangc9e1f582014-01-24 15:50:09 +080053#ifdef CONFIG_SECURE_BOOT
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053054#define CONFIG_SPL_INIT_MINIMAL
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053055#define CONFIG_SPL_FLUSH_IMAGE
56#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
57
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053058#define CONFIG_SPL_MAX_SIZE 8192
59#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
60#define CONFIG_SPL_RELOC_STACK 0x00100000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053061#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +053062#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
63#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
64#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
Ying Zhangc9e1f582014-01-24 15:50:09 +080065#else
Ying Zhangc9e1f582014-01-24 15:50:09 +080066#ifdef CONFIG_TPL_BUILD
Ying Zhangc9e1f582014-01-24 15:50:09 +080067#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhangc9e1f582014-01-24 15:50:09 +080068#define CONFIG_SPL_NAND_INIT
Ying Zhangc9e1f582014-01-24 15:50:09 +080069#define CONFIG_SPL_COMMON_INIT_DDR
70#define CONFIG_SPL_MAX_SIZE (128 << 10)
Tom Rinia6d68122019-01-22 17:09:24 -050071#define CONFIG_TPL_TEXT_BASE 0xD0001000
Ying Zhangc9e1f582014-01-24 15:50:09 +080072#define CONFIG_SYS_MPC85XX_NO_RESETVEC
73#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
74#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
75#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
76#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
77#elif defined(CONFIG_SPL_BUILD)
78#define CONFIG_SPL_INIT_MINIMAL
Ying Zhangc9e1f582014-01-24 15:50:09 +080079#define CONFIG_SPL_NAND_MINIMAL
80#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhangc9e1f582014-01-24 15:50:09 +080081#define CONFIG_SPL_MAX_SIZE 8192
82#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
83#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
84#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
85#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -050086#endif
Ying Zhangc9e1f582014-01-24 15:50:09 +080087#define CONFIG_SPL_PAD_TO 0x20000
88#define CONFIG_TPL_PAD_TO 0x20000
89#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhangc9e1f582014-01-24 15:50:09 +080090#endif
91#endif
Ruchika Gupta2f439e82011-06-08 22:52:48 -050092
93#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */
94#define CONFIG_RAMBOOT_NAND
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053095#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Ruchika Gupta2f439e82011-06-08 22:52:48 -050096#endif
97
Poonam Aggrwal49249e12011-02-09 19:17:53 +000098#ifndef CONFIG_RESET_VECTOR_ADDRESS
99#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
100#endif
101
Tom Rinia6d68122019-01-22 17:09:24 -0500102#ifdef CONFIG_TPL_BUILD
103#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
104#elif defined(CONFIG_SPL_BUILD)
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530105#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
106#else
107#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000108#endif
109
110/* High Level Configuration Options */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000111#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
112
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000113#if defined(CONFIG_PCI)
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400114#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
115#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000116#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +0000117#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000118#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
119
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000120/*
121 * PCI Windows
122 * Memory space is mapped 1-1, but I/O space must start from 0.
123 */
124/* controller 1, Slot 1, tgtid 1, Base address a000 */
125#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot"
126#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
127#ifdef CONFIG_PHYS_64BIT
128#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
129#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
130#else
131#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
132#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
133#endif
134#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
135#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
136#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
137#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
138#ifdef CONFIG_PHYS_64BIT
139#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
140#else
141#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
142#endif
143
144/* controller 2, Slot 2, tgtid 2, Base address 9000 */
York Sun76016862016-11-16 13:30:06 -0800145#if defined(CONFIG_TARGET_P1010RDB_PA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000146#define CONFIG_SYS_PCIE2_NAME "PCIe Slot"
York Sun76016862016-11-16 13:30:06 -0800147#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liue512c502013-09-13 14:46:03 +0800148#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot"
149#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000150#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
151#ifdef CONFIG_PHYS_64BIT
152#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
153#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
154#else
155#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
156#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
157#endif
158#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
159#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
160#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
161#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
162#ifdef CONFIG_PHYS_64BIT
163#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
164#else
165#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
166#endif
167
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000168#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000169#endif
170
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000171#define CONFIG_ENV_OVERWRITE
172
173#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */
174#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */
175
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000176#define CONFIG_HWCONFIG
177/*
178 * These can be toggled for performance analysis, otherwise use default.
179 */
180#define CONFIG_L2_CACHE /* toggle L2 cache */
181#define CONFIG_BTB /* toggle branch predition */
182
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000183
184#define CONFIG_ENABLE_36BIT_PHYS
185
186#ifdef CONFIG_PHYS_64BIT
187#define CONFIG_ADDR_MAP 1
188#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
189#endif
190
Zhao Qiangc3cc02a2013-11-26 13:59:15 +0800191#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000192#define CONFIG_SYS_MEMTEST_END 0x1fffffff
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000193
194/* DDR Setup */
York Sun1ba62f12012-02-29 12:36:51 +0000195#define CONFIG_SYS_DDR_RAW_TIMING
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000196#define CONFIG_DDR_SPD
197#define CONFIG_SYS_SPD_BUS_NUM 1
198#define SPD_EEPROM_ADDRESS 0x52
199
200#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
201
202#ifndef __ASSEMBLY__
203extern unsigned long get_sdram_size(void);
204#endif
205#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
206#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
207#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
208
209#define CONFIG_DIMM_SLOTS_PER_CTLR 1
210#define CONFIG_CHIP_SELECTS_PER_CTRL 1
211
212/* DDR3 Controller Settings */
213#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
214#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
215#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
216#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
217#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
218#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
219#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000220#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
221#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
222#define CONFIG_SYS_DDR_RCW_1 0x00000000
223#define CONFIG_SYS_DDR_RCW_2 0x00000000
Shengzhou Liue512c502013-09-13 14:46:03 +0800224#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */
225#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000226#define CONFIG_SYS_DDR_TIMING_4 0x00000001
227#define CONFIG_SYS_DDR_TIMING_5 0x03402400
228
Shengzhou Liue512c502013-09-13 14:46:03 +0800229#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
230#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
231#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000232#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF
233#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
Shengzhou Liue512c502013-09-13 14:46:03 +0800234#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
235#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000236#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100
Shengzhou Liue512c502013-09-13 14:46:03 +0800237#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000238
239/* settings for DDR3 at 667MT/s */
240#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000
241#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004
242#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544
243#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD
244#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000
245#define CONFIG_SYS_DDR_MODE_1_667 0x00441210
246#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
247#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000
248#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608
249
250#define CONFIG_SYS_CCSRBAR 0xffe00000
251#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
252
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500253/* Don't relocate CCSRBAR while in NAND_SPL */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530254#ifdef CONFIG_SPL_BUILD
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500255#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
256#endif
257
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000258/*
259 * Memory map
260 *
261 * 0x0000_0000 0x3fff_ffff DDR 1G cacheable
262 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable
263 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
264 *
265 * Localbus non-cacheable
266 * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable
267 * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
268 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
269 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
270 */
271
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000272/*
273 * IFC Definitions
274 */
275/* NOR Flash on IFC */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530276
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000277#define CONFIG_SYS_FLASH_BASE 0xee000000
278#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
279
280#ifdef CONFIG_PHYS_64BIT
281#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
282#else
283#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
284#endif
285
286#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
287 CSPR_PORT_SIZE_16 | \
288 CSPR_MSEL_NOR | \
289 CSPR_V)
290#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024)
291#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7)
292/* NOR Flash Timing Params */
293#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \
294 FTIM0_NOR_TEADC(0x5) | \
295 FTIM0_NOR_TEAHC(0x5)
296#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \
297 FTIM1_NOR_TRAD_NOR(0x0f)
298#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \
299 FTIM2_NOR_TCH(0x4) | \
300 FTIM2_NOR_TWP(0x1c)
301#define CONFIG_SYS_NOR_FTIM3 0x0
302
303#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
304#define CONFIG_SYS_FLASH_QUIET_TEST
305#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
306#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
307
308#undef CONFIG_SYS_FLASH_CHECKSUM
309#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
310#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
311
312/* CFI for NOR Flash */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000313#define CONFIG_SYS_FLASH_EMPTY_INFO
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000314
315/* NAND Flash on IFC */
316#define CONFIG_SYS_NAND_BASE 0xff800000
317#ifdef CONFIG_PHYS_64BIT
318#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
319#else
320#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
321#endif
322
Zhao Qiangac688072013-09-26 09:10:32 +0800323#define CONFIG_MTD_PARTITION
Zhao Qiangac688072013-09-26 09:10:32 +0800324
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000325#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
326 | CSPR_PORT_SIZE_8 \
327 | CSPR_MSEL_NAND \
328 | CSPR_V)
329#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
Shengzhou Liue512c502013-09-13 14:46:03 +0800330
York Sun76016862016-11-16 13:30:06 -0800331#if defined(CONFIG_TARGET_P1010RDB_PA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000332#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
333 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
334 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
335 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
336 | CSOR_NAND_PGS_512 /* Page Size = 512b */ \
337 | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \
338 | CSOR_NAND_PB(32)) /* 32 Pages Per Block */
Shengzhou Liue512c502013-09-13 14:46:03 +0800339#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
340
York Sun76016862016-11-16 13:30:06 -0800341#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liue512c502013-09-13 14:46:03 +0800342#define CONFIG_SYS_NAND_ONFI_DETECTION
343#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
344 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
345 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
346 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
347 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
348 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
349 | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
350#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
351#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000352
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500353#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
354#define CONFIG_SYS_MAX_NAND_DEVICE 1
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500355
York Sun76016862016-11-16 13:30:06 -0800356#if defined(CONFIG_TARGET_P1010RDB_PA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000357/* NAND Flash Timing Params */
358#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
359 FTIM0_NAND_TWP(0x0C) | \
360 FTIM0_NAND_TWCHT(0x04) | \
361 FTIM0_NAND_TWH(0x05)
362#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
363 FTIM1_NAND_TWBE(0x1d) | \
364 FTIM1_NAND_TRR(0x07) | \
365 FTIM1_NAND_TRP(0x0c)
366#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
367 FTIM2_NAND_TREH(0x05) | \
368 FTIM2_NAND_TWHRE(0x0f)
369#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
370
York Sun76016862016-11-16 13:30:06 -0800371#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liue512c502013-09-13 14:46:03 +0800372/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
373/* ONFI NAND Flash mode0 Timing Params */
374#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
375 FTIM0_NAND_TWP(0x18) | \
376 FTIM0_NAND_TWCHT(0x07) | \
377 FTIM0_NAND_TWH(0x0a))
378#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
379 FTIM1_NAND_TWBE(0x39) | \
380 FTIM1_NAND_TRR(0x0e) | \
381 FTIM1_NAND_TRP(0x18))
382#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
383 FTIM2_NAND_TREH(0x0a) | \
384 FTIM2_NAND_TWHRE(0x1e))
385#define CONFIG_SYS_NAND_FTIM3 0x0
386#endif
387
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000388#define CONFIG_SYS_NAND_DDR_LAW 11
389
390/* Set up IFC registers for boot location NOR/NAND */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530391#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500392#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
393#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
394#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
395#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
396#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
397#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
398#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
399#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
400#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
401#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
402#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
403#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
404#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
405#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
406#else
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000407#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
408#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
409#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
410#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
411#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
412#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
413#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
414#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
415#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
416#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
417#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
418#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
419#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
420#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500421#endif
422
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000423/* CPLD on IFC */
424#define CONFIG_SYS_CPLD_BASE 0xffb00000
425
426#ifdef CONFIG_PHYS_64BIT
427#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull
428#else
429#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
430#endif
431
432#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
433 | CSPR_PORT_SIZE_8 \
434 | CSPR_MSEL_GPCM \
435 | CSPR_V)
436#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
437#define CONFIG_SYS_CSOR3 0x0
438/* CPLD Timing parameters for IFC CS3 */
439#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
440 FTIM0_GPCM_TEADC(0x0e) | \
441 FTIM0_GPCM_TEAHC(0x0e))
442#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
443 FTIM1_GPCM_TRAD(0x1f))
444#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800445 FTIM2_GPCM_TCH(0x8) | \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000446 FTIM2_GPCM_TWP(0x1f))
447#define CONFIG_SYS_CS3_FTIM3 0x0
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000448
Aneesh Bansal76c9aaf2014-03-07 19:12:09 +0530449#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \
450 defined(CONFIG_RAMBOOT_NAND)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000451#define CONFIG_SYS_RAMBOOT
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000452#else
453#undef CONFIG_SYS_RAMBOOT
454#endif
455
Prabhakar Kushwaha74fa22e2013-04-16 13:27:44 +0530456#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Aneesh Bansal50c76362014-01-20 14:57:03 +0530457#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)
Prabhakar Kushwaha74fa22e2013-04-16 13:27:44 +0530458#define CONFIG_A003399_NOR_WORKAROUND
459#endif
460#endif
461
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000462#define CONFIG_SYS_INIT_RAM_LOCK
463#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
York Sunb39d1212016-04-06 13:22:10 -0700464#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000465
York Sunb39d1212016-04-06 13:22:10 -0700466#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000467 - GENERATED_GBL_DATA_SIZE)
468#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
469
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530470#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000471#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
472
Ying Zhangc9e1f582014-01-24 15:50:09 +0800473/*
474 * Config the L2 Cache as L2 SRAM
475 */
476#if defined(CONFIG_SPL_BUILD)
477#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
478#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
479#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
480#define CONFIG_SYS_L2_SIZE (256 << 10)
481#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
482#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
483#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
Ying Zhangc9e1f582014-01-24 15:50:09 +0800484#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
485#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10)
486#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024)
487#elif defined(CONFIG_NAND)
488#ifdef CONFIG_TPL_BUILD
489#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
490#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
491#define CONFIG_SYS_L2_SIZE (256 << 10)
492#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
493#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000
494#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
495#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
496#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
497#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
498#else
499#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000
500#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
501#define CONFIG_SYS_L2_SIZE (256 << 10)
502#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
503#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
504#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
505#endif
506#endif
507#endif
508
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000509/* Serial Port */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000510#undef CONFIG_SERIAL_SOFTWARE_FIFO
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000511#define CONFIG_SYS_NS16550_SERIAL
512#define CONFIG_SYS_NS16550_REG_SIZE 1
513#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhangc9e1f582014-01-24 15:50:09 +0800514#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500515#define CONFIG_NS16550_MIN_FUNCTIONS
516#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000517
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000518#define CONFIG_SYS_BAUDRATE_TABLE \
519 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
520
521#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
522#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
523
Heiko Schocher00f792e2012-10-24 13:48:22 +0200524/* I2C */
525#define CONFIG_SYS_I2C
526#define CONFIG_SYS_I2C_FSL
527#define CONFIG_SYS_FSL_I2C_SPEED 400000
528#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
529#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
530#define CONFIG_SYS_FSL_I2C2_SPEED 400000
531#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
532#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Shengzhou Liuad89da02013-09-13 14:46:02 +0800533#define I2C_PCA9557_ADDR1 0x18
Shengzhou Liue512c502013-09-13 14:46:03 +0800534#define I2C_PCA9557_ADDR2 0x19
Shengzhou Liuad89da02013-09-13 14:46:02 +0800535#define I2C_PCA9557_BUS_NUM 0
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000536
537/* I2C EEPROM */
York Sun76016862016-11-16 13:30:06 -0800538#if defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liue512c502013-09-13 14:46:03 +0800539#define CONFIG_ID_EEPROM
540#ifdef CONFIG_ID_EEPROM
541#define CONFIG_SYS_I2C_EEPROM_NXID
542#endif
543#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
544#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
545#define CONFIG_SYS_EEPROM_BUS_NUM 0
546#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
547#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000548/* enable read and write access to EEPROM */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000549#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
550#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
551#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
552
553/* RTC */
554#define CONFIG_RTC_PT7C4338
555#define CONFIG_SYS_I2C_RTC_ADDR 0x68
556
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000557/*
558 * SPI interface will not be available in case of NAND boot SPI CS0 will be
559 * used for SLIC
560 */
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530561#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000562/* eSPI - Enhanced SPI */
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500563#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000564
565#if defined(CONFIG_TSEC_ENET)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000566#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
567#define CONFIG_TSEC1 1
568#define CONFIG_TSEC1_NAME "eTSEC1"
569#define CONFIG_TSEC2 1
570#define CONFIG_TSEC2_NAME "eTSEC2"
571#define CONFIG_TSEC3 1
572#define CONFIG_TSEC3_NAME "eTSEC3"
573
574#define TSEC1_PHY_ADDR 1
575#define TSEC2_PHY_ADDR 0
576#define TSEC3_PHY_ADDR 2
577
578#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
579#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
580#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
581
582#define TSEC1_PHYIDX 0
583#define TSEC2_PHYIDX 0
584#define TSEC3_PHYIDX 0
585
586#define CONFIG_ETHPRIME "eTSEC1"
587
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000588/* TBI PHY configuration for SGMII mode */
589#define CONFIG_TSEC_TBICR_SETTINGS ( \
590 TBICR_PHY_RESET \
591 | TBICR_ANEG_ENABLE \
592 | TBICR_FULL_DUPLEX \
593 | TBICR_SPEED1_SET \
594 )
595
596#endif /* CONFIG_TSEC_ENET */
597
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000598/* SATA */
Zang Roy-R619119760b272012-11-26 00:05:38 +0000599#define CONFIG_FSL_SATA_V2
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000600
601#ifdef CONFIG_FSL_SATA
602#define CONFIG_SYS_SATA_MAX_DEVICE 2
603#define CONFIG_SATA1
604#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
605#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
606#define CONFIG_SATA2
607#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
608#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
609
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000610#define CONFIG_LBA48
611#endif /* #ifdef CONFIG_FSL_SATA */
612
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000613#ifdef CONFIG_MMC
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000614#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
615#endif
616
617#define CONFIG_HAS_FSL_DR_USB
618
619#if defined(CONFIG_HAS_FSL_DR_USB)
Tom Rini8850c5d2017-05-12 22:33:27 -0400620#ifdef CONFIG_USB_EHCI_HCD
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000621#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
622#define CONFIG_USB_EHCI_FSL
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000623#endif
624#endif
625
626/*
627 * Environment
628 */
Ying Zhangc9e1f582014-01-24 15:50:09 +0800629#if defined(CONFIG_SDCARD)
Fabio Estevam4394d0c2012-01-11 09:20:50 +0000630#define CONFIG_FSL_FIXED_MMC_LOCATION
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000631#define CONFIG_SYS_MMC_ENV_DEV 0
632#define CONFIG_ENV_SIZE 0x2000
Ying Zhangc9e1f582014-01-24 15:50:09 +0800633#elif defined(CONFIG_SPIFLASH)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000634#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
635#define CONFIG_ENV_SECT_SIZE 0x10000
636#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530637#elif defined(CONFIG_NAND)
Ying Zhangc9e1f582014-01-24 15:50:09 +0800638#ifdef CONFIG_TPL_BUILD
639#define CONFIG_ENV_SIZE 0x2000
640#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
641#else
York Sun76016862016-11-16 13:30:06 -0800642#if defined(CONFIG_TARGET_P1010RDB_PA)
Dipen Dudhatd793e5a2011-07-28 14:47:28 -0500643#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Shengzhou Liue512c502013-09-13 14:46:03 +0800644#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */
York Sun76016862016-11-16 13:30:06 -0800645#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liue512c502013-09-13 14:46:03 +0800646#define CONFIG_ENV_SIZE (16 * 1024)
647#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */
648#endif
Ying Zhangc9e1f582014-01-24 15:50:09 +0800649#endif
650#define CONFIG_ENV_OFFSET (1024 * 1024)
Prabhakar Kushwaha0fa934d2013-04-16 13:28:12 +0530651#elif defined(CONFIG_SYS_RAMBOOT)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000652#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
653#define CONFIG_ENV_SIZE 0x2000
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000654#else
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000655#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000656#define CONFIG_ENV_SIZE 0x2000
657#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
658#endif
659
660#define CONFIG_LOADS_ECHO /* echo on for serial download */
661#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
662
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000663#undef CONFIG_WATCHDOG /* watchdog disabled */
664
Tom Rini8850c5d2017-05-12 22:33:27 -0400665#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000666 || defined(CONFIG_FSL_SATA)
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000667#endif
668
669/*
670 * Miscellaneous configurable options
671 */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000672#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000673
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000674/*
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000675 * For booting Linux, the board info and command line data
676 * have to be in the first 64 MB of memory, since this is
677 * the maximum mapped by the Linux kernel during initialization.
678 */
679#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
680#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
681
682#if defined(CONFIG_CMD_KGDB)
683#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000684#endif
685
686/*
687 * Environment Configuration
688 */
689
690#if defined(CONFIG_TSEC_ENET)
691#define CONFIG_HAS_ETH0
692#define CONFIG_HAS_ETH1
693#define CONFIG_HAS_ETH2
694#endif
695
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000696#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000697#define CONFIG_BOOTFILE "uImage"
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000698#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
699
700/* default location for tftp and bootm */
701#define CONFIG_LOADADDR 1000000
702
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000703#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut5368c552012-09-23 17:41:24 +0200704 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000705 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200706 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000707 "loadaddr=1000000\0" \
708 "consoledev=ttyS0\0" \
709 "ramdiskaddr=2000000\0" \
710 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500711 "fdtaddr=1e00000\0" \
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000712 "fdtfile=p1010rdb.dtb\0" \
713 "bdev=sda1\0" \
714 "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \
715 "othbootargs=ramdisk_size=600000\0" \
716 "usbfatboot=setenv bootargs root=/dev/ram rw " \
717 "console=$consoledev,$baudrate $othbootargs; " \
718 "usb start;" \
719 "fatload usb 0:2 $loadaddr $bootfile;" \
720 "fatload usb 0:2 $fdtaddr $fdtfile;" \
721 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
722 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
723 "usbext2boot=setenv bootargs root=/dev/ram rw " \
724 "console=$consoledev,$baudrate $othbootargs; " \
725 "usb start;" \
726 "ext2load usb 0:4 $loadaddr $bootfile;" \
727 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
728 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
Shengzhou Liue512c502013-09-13 14:46:03 +0800729 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
730 CONFIG_BOOTMODE
731
York Sun76016862016-11-16 13:30:06 -0800732#if defined(CONFIG_TARGET_P1010RDB_PA)
Shengzhou Liue512c502013-09-13 14:46:03 +0800733#define CONFIG_BOOTMODE \
734 "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
735 "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \
736 "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \
737 "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \
738 "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \
739 "mw.b ffb00011 0; mw.b ffb00017 1; reset\0"
740
York Sun76016862016-11-16 13:30:06 -0800741#elif defined(CONFIG_TARGET_P1010RDB_PB)
Shengzhou Liue512c502013-09-13 14:46:03 +0800742#define CONFIG_BOOTMODE \
743 "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
744 "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \
745 "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \
746 "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \
747 "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \
748 "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \
749 "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \
750 "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \
751 "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \
752 "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0"
753#endif
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000754
755#define CONFIG_RAMBOOTCOMMAND \
756 "setenv bootargs root=/dev/ram rw " \
757 "console=$consoledev,$baudrate $othbootargs; " \
758 "tftp $ramdiskaddr $ramdiskfile;" \
759 "tftp $loadaddr $bootfile;" \
760 "tftp $fdtaddr $fdtfile;" \
761 "bootm $loadaddr $ramdiskaddr $fdtaddr"
762
763#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
764
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500765#include <asm/fsl_secure_boot.h>
Ruchika Gupta2f439e82011-06-08 22:52:48 -0500766
Poonam Aggrwal49249e12011-02-09 19:17:53 +0000767#endif /* __CONFIG_H */