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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ian Campbellcba69ee2014-05-05 11:52:26 +01002/*
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 *
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
9 *
10 * Some board init for the Allwinner A10-evb board.
Ian Campbellcba69ee2014-05-05 11:52:26 +010011 */
12
13#include <common.h>
Jagan Teki237050f2018-05-07 13:03:36 +053014#include <dm.h>
Simon Glassc7694dd2019-08-01 09:46:46 -060015#include <env.h>
Hans de Goedee79c7c82014-10-02 21:13:54 +020016#include <mmc.h>
Hans de Goede6944aff2015-10-03 15:18:33 +020017#include <axp_pmic.h>
Jagan Teki237050f2018-05-07 13:03:36 +053018#include <generic-phy.h>
19#include <phy-sun4i-usb.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010020#include <asm/arch/clock.h>
Jonathan Liub41d7d02014-06-14 08:59:09 +020021#include <asm/arch/cpu.h>
Luc Verhaegen2d7a0842014-08-13 07:55:07 +020022#include <asm/arch/display.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010023#include <asm/arch/dram.h>
Ian Campbelle24ea552014-05-05 14:42:31 +010024#include <asm/arch/gpio.h>
25#include <asm/arch/mmc.h>
Hans de Goede4a8c7c12016-07-09 09:56:56 +020026#include <asm/arch/spl.h>
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +020027#ifndef CONFIG_ARM64
28#include <asm/armv7.h>
29#endif
Hans de Goede4f7e01c2015-04-23 23:23:50 +020030#include <asm/gpio.h>
Jonathan Liub41d7d02014-06-14 08:59:09 +020031#include <asm/io.h>
Philipp Tomsicha740ee92018-11-25 19:22:18 +010032#include <u-boot/crc.h>
Simon Glassf3998fd2019-08-02 09:44:25 -060033#include <env_internal.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090034#include <linux/libfdt.h>
Hans de Goedef62bfa52015-08-15 11:55:26 +020035#include <nand.h>
Jonathan Liub41d7d02014-06-14 08:59:09 +020036#include <net.h>
Maxime Ripardf4c35232017-08-23 10:08:29 +020037#include <spl.h>
Jelle van der Waa0d8382a2016-02-23 18:47:19 +010038#include <sy8106a.h>
Simon Glass5d982852017-05-17 08:23:00 -060039#include <asm/setup.h>
Ian Campbellcba69ee2014-05-05 11:52:26 +010040
Hans de Goede55410082015-02-16 17:23:25 +010041#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
42/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
43int soft_i2c_gpio_sda;
44int soft_i2c_gpio_scl;
Hans de Goede4f7e01c2015-04-23 23:23:50 +020045
46static int soft_i2c_board_init(void)
47{
48 int ret;
49
50 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
51 if (soft_i2c_gpio_sda < 0) {
52 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
53 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
54 return soft_i2c_gpio_sda;
55 }
56 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
57 if (ret) {
58 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
59 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
60 return ret;
61 }
62
63 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
64 if (soft_i2c_gpio_scl < 0) {
65 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
66 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
67 return soft_i2c_gpio_scl;
68 }
69 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
70 if (ret) {
71 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
72 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
73 return ret;
74 }
75
76 return 0;
77}
78#else
79static int soft_i2c_board_init(void) { return 0; }
Hans de Goede55410082015-02-16 17:23:25 +010080#endif
81
Ian Campbellcba69ee2014-05-05 11:52:26 +010082DECLARE_GLOBAL_DATA_PTR;
83
Jernej Skrabecacbc7e02017-04-27 00:03:35 +020084void i2c_init_board(void)
85{
86#ifdef CONFIG_I2C0_ENABLE
87#if defined(CONFIG_MACH_SUN4I) || \
88 defined(CONFIG_MACH_SUN5I) || \
89 defined(CONFIG_MACH_SUN7I) || \
90 defined(CONFIG_MACH_SUN8I_R40)
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
92 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
93 clock_twi_onoff(0, 1);
94#elif defined(CONFIG_MACH_SUN6I)
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
96 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
97 clock_twi_onoff(0, 1);
98#elif defined(CONFIG_MACH_SUN8I)
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
100 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
101 clock_twi_onoff(0, 1);
Stefan Mavrodievda1ae592019-01-08 12:04:30 +0200102#elif defined(CONFIG_MACH_SUN50I)
103 sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
104 sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
105 clock_twi_onoff(0, 1);
Jernej Skrabecacbc7e02017-04-27 00:03:35 +0200106#endif
107#endif
108
109#ifdef CONFIG_I2C1_ENABLE
110#if defined(CONFIG_MACH_SUN4I) || \
111 defined(CONFIG_MACH_SUN7I) || \
112 defined(CONFIG_MACH_SUN8I_R40)
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
114 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
115 clock_twi_onoff(1, 1);
116#elif defined(CONFIG_MACH_SUN5I)
117 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
118 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
119 clock_twi_onoff(1, 1);
120#elif defined(CONFIG_MACH_SUN6I)
121 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
122 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
123 clock_twi_onoff(1, 1);
124#elif defined(CONFIG_MACH_SUN8I)
125 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
126 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
127 clock_twi_onoff(1, 1);
Stefan Mavrodievda1ae592019-01-08 12:04:30 +0200128#elif defined(CONFIG_MACH_SUN50I)
129 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
130 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
131 clock_twi_onoff(1, 1);
Jernej Skrabecacbc7e02017-04-27 00:03:35 +0200132#endif
133#endif
134
135#ifdef CONFIG_I2C2_ENABLE
136#if defined(CONFIG_MACH_SUN4I) || \
137 defined(CONFIG_MACH_SUN7I) || \
138 defined(CONFIG_MACH_SUN8I_R40)
139 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
140 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
141 clock_twi_onoff(2, 1);
142#elif defined(CONFIG_MACH_SUN5I)
143 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
144 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
145 clock_twi_onoff(2, 1);
146#elif defined(CONFIG_MACH_SUN6I)
147 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
148 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
149 clock_twi_onoff(2, 1);
150#elif defined(CONFIG_MACH_SUN8I)
151 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
152 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
153 clock_twi_onoff(2, 1);
Stefan Mavrodievda1ae592019-01-08 12:04:30 +0200154#elif defined(CONFIG_MACH_SUN50I)
155 sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
156 sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
157 clock_twi_onoff(2, 1);
Jernej Skrabecacbc7e02017-04-27 00:03:35 +0200158#endif
159#endif
160
161#ifdef CONFIG_I2C3_ENABLE
162#if defined(CONFIG_MACH_SUN6I)
163 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
164 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
165 clock_twi_onoff(3, 1);
166#elif defined(CONFIG_MACH_SUN7I) || \
167 defined(CONFIG_MACH_SUN8I_R40)
168 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
169 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
170 clock_twi_onoff(3, 1);
171#endif
172#endif
173
174#ifdef CONFIG_I2C4_ENABLE
175#if defined(CONFIG_MACH_SUN7I) || \
176 defined(CONFIG_MACH_SUN8I_R40)
177 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
178 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
179 clock_twi_onoff(4, 1);
180#endif
181#endif
182
183#ifdef CONFIG_R_I2C_ENABLE
Vasily Khoruzhick31a4ac42018-11-05 20:24:30 -0800184#ifdef CONFIG_MACH_SUN50I
185 clock_twi_onoff(5, 1);
186 sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
187 sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
188#else
Jernej Skrabecacbc7e02017-04-27 00:03:35 +0200189 clock_twi_onoff(5, 1);
190 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
191 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
192#endif
Vasily Khoruzhick31a4ac42018-11-05 20:24:30 -0800193#endif
Jernej Skrabecacbc7e02017-04-27 00:03:35 +0200194}
195
Maxime Ripardb39117c2018-01-23 21:17:03 +0100196#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
197enum env_location env_get_location(enum env_operation op, int prio)
198{
199 switch (prio) {
200 case 0:
201 return ENVL_FAT;
202
203 case 1:
204 return ENVL_MMC;
205
206 default:
207 return ENVL_UNKNOWN;
208 }
209}
210#endif
211
Andre Przywaraa7ae1592019-01-29 15:54:14 +0000212#ifdef CONFIG_DM_MMC
213static void mmc_pinmux_setup(int sdc);
214#endif
215
Ian Campbellcba69ee2014-05-05 11:52:26 +0100216/* add board specific code here */
217int board_init(void)
218{
Mylène Josserandf5fd7882017-04-02 12:59:10 +0200219 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
Ian Campbellcba69ee2014-05-05 11:52:26 +0100220
221 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
222
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200223#ifndef CONFIG_ARM64
Ian Campbellcba69ee2014-05-05 11:52:26 +0100224 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
225 debug("id_pfr1: 0x%08x\n", id_pfr1);
226 /* Generic Timer Extension available? */
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200227 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
228 uint32_t freq;
229
Ian Campbellcba69ee2014-05-05 11:52:26 +0100230 debug("Setting CNTFRQ\n");
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200231
232 /*
233 * CNTFRQ is a secure register, so we will crash if we try to
234 * write this from the non-secure world (read is OK, though).
235 * In case some bootcode has already set the correct value,
236 * we avoid the risk of writing to it.
237 */
238 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
Andre Przywarae4916e82017-02-16 01:20:19 +0000239 if (freq != COUNTER_FREQUENCY) {
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200240 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
Andre Przywarae4916e82017-02-16 01:20:19 +0000241 freq, COUNTER_FREQUENCY);
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200242#ifdef CONFIG_NON_SECURE
243 printf("arch timer frequency is wrong, but cannot adjust it\n");
244#else
245 asm volatile("mcr p15, 0, %0, c14, c0, 0"
Andre Przywarae4916e82017-02-16 01:20:19 +0000246 : : "r"(COUNTER_FREQUENCY));
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200247#endif
248 }
Ian Campbellcba69ee2014-05-05 11:52:26 +0100249 }
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200250#endif /* !CONFIG_ARM64 */
Ian Campbellcba69ee2014-05-05 11:52:26 +0100251
Hans de Goede2fcf0332015-04-25 17:25:14 +0200252 ret = axp_gpio_init();
253 if (ret)
254 return ret;
255
Hans de Goede9fbb0c32016-03-22 20:10:30 +0100256#ifdef CONFIG_SATAPWR
Mylène Josserandd7b560e2017-04-02 12:59:09 +0200257 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
258 gpio_request(satapwr_pin, "satapwr");
259 gpio_direction_output(satapwr_pin, 1);
Werner Böllmann8e2c2d42017-11-10 19:14:20 +0530260 /* Give attached sata device time to power-up to avoid link timeouts */
261 mdelay(500);
Hans de Goede9fbb0c32016-03-22 20:10:30 +0100262#endif
Hans de Goedefc8991c2016-03-17 13:53:03 +0100263#ifdef CONFIG_MACPWR
Mylène Josserandf5fd7882017-04-02 12:59:10 +0200264 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
265 gpio_request(macpwr_pin, "macpwr");
266 gpio_direction_output(macpwr_pin, 1);
Hans de Goedefc8991c2016-03-17 13:53:03 +0100267#endif
268
Jernej Skrabeca8f01cc2017-04-27 00:03:36 +0200269#ifdef CONFIG_DM_I2C
270 /*
271 * Temporary workaround for enabling I2C clocks until proper sunxi DM
272 * clk, reset and pinctrl drivers land.
273 */
274 i2c_init_board();
275#endif
276
Andre Przywaraa7ae1592019-01-29 15:54:14 +0000277#ifdef CONFIG_DM_MMC
278 /*
279 * Temporary workaround for enabling MMC clocks until a sunxi DM
280 * pinctrl driver lands.
281 */
282 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
283#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
284 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
285#endif
286#endif /* CONFIG_DM_MMC */
287
Hans de Goede4f7e01c2015-04-23 23:23:50 +0200288 /* Uses dm gpio code so do this here and not in i2c_init_board() */
289 return soft_i2c_board_init();
Ian Campbellcba69ee2014-05-05 11:52:26 +0100290}
291
Andre Przywaracff5c132018-10-25 17:23:04 +0800292/*
293 * On older SoCs the SPL is actually at address zero, so using NULL as
294 * an error value does not work.
295 */
296#define INVALID_SPL_HEADER ((void *)~0UL)
297
298static struct boot_file_head * get_spl_header(uint8_t req_version)
299{
300 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
301 uint8_t spl_header_version = spl->spl_signature[3];
302
303 /* Is there really the SPL header (still) there? */
304 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
305 return INVALID_SPL_HEADER;
306
307 if (spl_header_version < req_version) {
308 printf("sunxi SPL version mismatch: expected %u, got %u\n",
309 req_version, spl_header_version);
310 return INVALID_SPL_HEADER;
311 }
312
313 return spl;
314}
315
Ian Campbellcba69ee2014-05-05 11:52:26 +0100316int dram_init(void)
317{
Andre Przywara57766102018-10-25 17:23:07 +0800318 struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
319
320 if (spl == INVALID_SPL_HEADER)
321 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
322 PHYS_SDRAM_0_SIZE);
323 else
324 gd->ram_size = (phys_addr_t)spl->dram_size << 20;
325
326 if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
327 gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
Ian Campbellcba69ee2014-05-05 11:52:26 +0100328
329 return 0;
330}
331
Boris Brezillon4ccae812016-06-15 21:09:23 +0200332#if defined(CONFIG_NAND_SUNXI)
Karol Gugalaad008292015-07-23 14:33:01 +0200333static void nand_pinmux_setup(void)
334{
335 unsigned int pin;
Hans de Goede022a99d2015-08-15 13:17:49 +0200336
337 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
Karol Gugalaad008292015-07-23 14:33:01 +0200338 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
339
Hans de Goede022a99d2015-08-15 13:17:49 +0200340#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
341 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
Karol Gugalaad008292015-07-23 14:33:01 +0200342 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
Hans de Goede022a99d2015-08-15 13:17:49 +0200343#endif
344 /* sun4i / sun7i do have a PC23, but it is not used for nand,
345 * only sun7i has a PC24 */
346#ifdef CONFIG_MACH_SUN7I
Karol Gugalaad008292015-07-23 14:33:01 +0200347 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
Hans de Goede022a99d2015-08-15 13:17:49 +0200348#endif
Karol Gugalaad008292015-07-23 14:33:01 +0200349}
350
351static void nand_clock_setup(void)
352{
353 struct sunxi_ccm_reg *const ccm =
354 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
Hans de Goede31c21472015-08-15 11:58:03 +0200355
Karol Gugalaad008292015-07-23 14:33:01 +0200356 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
Miquel Raynalba1c98b2018-02-28 20:51:53 +0100357#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
358 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
359 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
360#endif
Karol Gugalaad008292015-07-23 14:33:01 +0200361 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
362}
Hans de Goedef62bfa52015-08-15 11:55:26 +0200363
364void board_nand_init(void)
365{
366 nand_pinmux_setup();
367 nand_clock_setup();
Boris Brezillon4ccae812016-06-15 21:09:23 +0200368#ifndef CONFIG_SPL_BUILD
369 sunxi_nand_init();
370#endif
Hans de Goedef62bfa52015-08-15 11:55:26 +0200371}
Karol Gugalaad008292015-07-23 14:33:01 +0200372#endif
373
Masahiro Yamada4aa2ba32017-05-09 20:31:39 +0900374#ifdef CONFIG_MMC
Ian Campbelle24ea552014-05-05 14:42:31 +0100375static void mmc_pinmux_setup(int sdc)
376{
377 unsigned int pin;
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100378 __maybe_unused int pins;
Ian Campbelle24ea552014-05-05 14:42:31 +0100379
380 switch (sdc) {
381 case 0:
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100382 /* SDC0: PF0-PF5 */
Ian Campbelle24ea552014-05-05 14:42:31 +0100383 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100384 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
Ian Campbelle24ea552014-05-05 14:42:31 +0100385 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
386 sunxi_gpio_set_drv(pin, 2);
387 }
388 break;
389
390 case 1:
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100391 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
392
Chen-Yu Tsai8094a4a2016-11-30 16:28:34 +0800393#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
394 defined(CONFIG_MACH_SUN8I_R40)
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100395 if (pins == SUNXI_GPIO_H) {
396 /* SDC1: PH22-PH-27 */
397 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
398 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
399 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
400 sunxi_gpio_set_drv(pin, 2);
401 }
402 } else {
403 /* SDC1: PG0-PG5 */
404 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
405 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
406 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
407 sunxi_gpio_set_drv(pin, 2);
408 }
409 }
410#elif defined(CONFIG_MACH_SUN5I)
411 /* SDC1: PG3-PG8 */
Hans de Goedebbff84b2014-10-03 16:44:57 +0200412 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100413 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
Ian Campbelle24ea552014-05-05 14:42:31 +0100414 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
415 sunxi_gpio_set_drv(pin, 2);
416 }
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100417#elif defined(CONFIG_MACH_SUN6I)
418 /* SDC1: PG0-PG5 */
419 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
420 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
421 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
422 sunxi_gpio_set_drv(pin, 2);
423 }
424#elif defined(CONFIG_MACH_SUN8I)
425 if (pins == SUNXI_GPIO_D) {
426 /* SDC1: PD2-PD7 */
427 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
428 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
429 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
430 sunxi_gpio_set_drv(pin, 2);
431 }
432 } else {
433 /* SDC1: PG0-PG5 */
434 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
435 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
436 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
437 sunxi_gpio_set_drv(pin, 2);
438 }
439 }
440#endif
Ian Campbelle24ea552014-05-05 14:42:31 +0100441 break;
442
443 case 2:
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100444 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
445
446#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
447 /* SDC2: PC6-PC11 */
Ian Campbelle24ea552014-05-05 14:42:31 +0100448 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
Paul Kocialkowski487b3272015-03-22 18:12:22 +0100449 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
Ian Campbelle24ea552014-05-05 14:42:31 +0100450 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
451 sunxi_gpio_set_drv(pin, 2);
452 }
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100453#elif defined(CONFIG_MACH_SUN5I)
454 if (pins == SUNXI_GPIO_E) {
455 /* SDC2: PE4-PE9 */
456 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
457 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
458 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
459 sunxi_gpio_set_drv(pin, 2);
460 }
461 } else {
462 /* SDC2: PC6-PC15 */
463 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
464 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
465 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
466 sunxi_gpio_set_drv(pin, 2);
467 }
468 }
469#elif defined(CONFIG_MACH_SUN6I)
470 if (pins == SUNXI_GPIO_A) {
471 /* SDC2: PA9-PA14 */
472 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
473 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
474 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
475 sunxi_gpio_set_drv(pin, 2);
476 }
477 } else {
478 /* SDC2: PC6-PC15, PC24 */
479 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
480 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
481 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
482 sunxi_gpio_set_drv(pin, 2);
483 }
Ian Campbelle24ea552014-05-05 14:42:31 +0100484
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100485 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
486 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
487 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
488 }
Chen-Yu Tsai8094a4a2016-11-30 16:28:34 +0800489#elif defined(CONFIG_MACH_SUN8I_R40)
490 /* SDC2: PC6-PC15, PC24 */
491 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
492 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
493 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
494 sunxi_gpio_set_drv(pin, 2);
495 }
496
497 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
498 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
499 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
Siarhei Siamashkad96ebc42016-03-29 17:29:10 +0200500#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100501 /* SDC2: PC5-PC6, PC8-PC16 */
502 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
503 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
Ian Campbelle24ea552014-05-05 14:42:31 +0100504 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
505 sunxi_gpio_set_drv(pin, 2);
506 }
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100507
508 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
509 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
510 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
511 sunxi_gpio_set_drv(pin, 2);
512 }
Icenowy Zheng42956f12018-07-21 16:20:29 +0800513#elif defined(CONFIG_MACH_SUN50I_H6)
514 /* SDC2: PC4-PC14 */
515 for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
516 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
517 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
518 sunxi_gpio_set_drv(pin, 2);
519 }
Philipp Tomsich3ebb4562016-10-28 18:21:33 +0800520#elif defined(CONFIG_MACH_SUN9I)
521 /* SDC2: PC6-PC16 */
522 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
523 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
524 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
525 sunxi_gpio_set_drv(pin, 2);
526 }
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100527#endif
528 break;
529
530 case 3:
531 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
532
Chen-Yu Tsai8094a4a2016-11-30 16:28:34 +0800533#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
534 defined(CONFIG_MACH_SUN8I_R40)
Paul Kocialkowski8deacca2015-03-22 18:12:23 +0100535 /* SDC3: PI4-PI9 */
536 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
537 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
538 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
539 sunxi_gpio_set_drv(pin, 2);
540 }
541#elif defined(CONFIG_MACH_SUN6I)
542 if (pins == SUNXI_GPIO_A) {
543 /* SDC3: PA9-PA14 */
544 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
545 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
546 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
547 sunxi_gpio_set_drv(pin, 2);
548 }
549 } else {
550 /* SDC3: PC6-PC15, PC24 */
551 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
552 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
553 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
554 sunxi_gpio_set_drv(pin, 2);
555 }
556
557 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
558 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
559 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
560 }
561#endif
Ian Campbelle24ea552014-05-05 14:42:31 +0100562 break;
563
564 default:
565 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
566 break;
567 }
568}
569
570int board_mmc_init(bd_t *bis)
571{
Hans de Goedee79c7c82014-10-02 21:13:54 +0200572 __maybe_unused struct mmc *mmc0, *mmc1;
Hans de Goedee79c7c82014-10-02 21:13:54 +0200573
Ian Campbelle24ea552014-05-05 14:42:31 +0100574 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
Hans de Goedee79c7c82014-10-02 21:13:54 +0200575 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
576 if (!mmc0)
577 return -1;
578
Hans de Goede2ccfac02014-10-02 20:43:50 +0200579#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
Ian Campbelle24ea552014-05-05 14:42:31 +0100580 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
Hans de Goedee79c7c82014-10-02 21:13:54 +0200581 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
582 if (!mmc1)
583 return -1;
584#endif
585
Ian Campbelle24ea552014-05-05 14:42:31 +0100586 return 0;
587}
588#endif
589
Ian Campbellcba69ee2014-05-05 11:52:26 +0100590#ifdef CONFIG_SPL_BUILD
Andre Przywara57766102018-10-25 17:23:07 +0800591
592static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
593{
594 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
595
596 if (spl == INVALID_SPL_HEADER)
597 return;
598
599 /* Promote the header version for U-Boot proper, if needed. */
600 if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
601 spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
602
603 spl->dram_size = dram_size >> 20;
604}
605
Ian Campbellcba69ee2014-05-05 11:52:26 +0100606void sunxi_board_init(void)
607{
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200608 int power_failed = 0;
Ian Campbellcba69ee2014-05-05 11:52:26 +0100609
Jelle van der Waa0d8382a2016-02-23 18:47:19 +0100610#ifdef CONFIG_SY8106A_POWER
611 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
612#endif
613
vishnupatekar95ab8fe2015-11-29 01:07:22 +0800614#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800615 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
616 defined CONFIG_AXP818_POWER
Hans de Goede6944aff2015-10-03 15:18:33 +0200617 power_failed = axp_init();
618
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800619#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
620 defined CONFIG_AXP818_POWER
Hans de Goede6944aff2015-10-03 15:18:33 +0200621 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
Hans de Goede24289202014-06-13 22:55:51 +0200622#endif
Hans de Goede6944aff2015-10-03 15:18:33 +0200623 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
624 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
vishnupatekar95ab8fe2015-11-29 01:07:22 +0800625#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
Hans de Goede6944aff2015-10-03 15:18:33 +0200626 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200627#endif
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800628#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
629 defined CONFIG_AXP818_POWER
Hans de Goede6944aff2015-10-03 15:18:33 +0200630 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
Oliver Schinagl5c7f10f2013-07-26 12:56:58 +0200631#endif
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200632
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800633#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
634 defined CONFIG_AXP818_POWER
Hans de Goede6944aff2015-10-03 15:18:33 +0200635 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
636#endif
637 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
Chen-Yu Tsaif3c50452016-01-12 14:42:40 +0800638#if !defined(CONFIG_AXP152_POWER)
Hans de Goede6944aff2015-10-03 15:18:33 +0200639 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
640#endif
641#ifdef CONFIG_AXP209_POWER
642 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
643#endif
644
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800645#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
646 defined(CONFIG_AXP818_POWER)
Chen-Yu Tsai3517a272016-01-12 14:42:37 +0800647 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
648 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800649#if !defined CONFIG_AXP809_POWER
Chen-Yu Tsai3517a272016-01-12 14:42:37 +0800650 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
651 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800652#endif
Hans de Goede6944aff2015-10-03 15:18:33 +0200653 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
654 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
655 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
656#endif
Chen-Yu Tsai38491d92016-03-30 00:26:48 +0800657
658#ifdef CONFIG_AXP818_POWER
659 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
660 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
661 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
Chen-Yu Tsai795857d2016-05-02 10:28:15 +0800662#endif
663
664#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
Chen-Yu Tsai15278cc2016-05-02 10:28:12 +0800665 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
Chen-Yu Tsai38491d92016-03-30 00:26:48 +0800666#endif
Hans de Goede6944aff2015-10-03 15:18:33 +0200667#endif
From: Karl Palsson44c214d2018-12-19 13:00:39 +0000668 printf("DRAM:");
669 gd->ram_size = sunxi_dram_init();
670 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
671 if (!gd->ram_size)
672 hang();
673
674 sunxi_spl_store_dram_size(gd->ram_size);
Andre Przywara57766102018-10-25 17:23:07 +0800675
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200676 /*
677 * Only clock up the CPU to full speed if we are reasonably
678 * assured it's being powered with suitable core voltage
679 */
680 if (!power_failed)
Iain Patone71b4222015-03-28 10:26:38 +0000681 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
Henrik Nordstrom14bc66b2014-06-13 22:55:50 +0200682 else
From: Karl Palsson44c214d2018-12-19 13:00:39 +0000683 printf("Failed to set core voltage! Can't set CPU frequency\n");
Ian Campbellcba69ee2014-05-05 11:52:26 +0100684}
685#endif
Jonathan Liub41d7d02014-06-14 08:59:09 +0200686
Paul Kocialkowskif1df7582015-03-22 18:07:13 +0100687#ifdef CONFIG_USB_GADGET
688int g_dnl_board_usb_cable_connected(void)
689{
Jagan Teki237050f2018-05-07 13:03:36 +0530690 struct udevice *dev;
691 struct phy phy;
692 int ret;
693
Jean-Jacques Hiblot01311622018-11-29 10:52:46 +0100694 ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
Jagan Teki237050f2018-05-07 13:03:36 +0530695 if (ret) {
696 pr_err("%s: Cannot find USB device\n", __func__);
697 return ret;
698 }
699
700 ret = generic_phy_get_by_name(dev, "usb", &phy);
701 if (ret) {
702 pr_err("failed to get %s USB PHY\n", dev->name);
703 return ret;
704 }
705
706 ret = generic_phy_init(&phy);
707 if (ret) {
708 pr_err("failed to init %s USB PHY\n", dev->name);
709 return ret;
710 }
711
712 ret = sun4i_usb_phy_vbus_detect(&phy);
713 if (ret == 1) {
714 pr_err("A charger is plugged into the OTG\n");
715 return -ENODEV;
716 }
717
718 return ret;
Paul Kocialkowskif1df7582015-03-22 18:07:13 +0100719}
720#endif
721
Paul Kocialkowski9f852212015-03-28 18:35:36 +0100722#ifdef CONFIG_SERIAL_TAG
723void get_board_serial(struct tag_serialnr *serialnr)
724{
725 char *serial_string;
726 unsigned long long serial;
727
Simon Glass00caae62017-08-03 12:22:12 -0600728 serial_string = env_get("serial#");
Paul Kocialkowski9f852212015-03-28 18:35:36 +0100729
730 if (serial_string) {
731 serial = simple_strtoull(serial_string, NULL, 16);
732
733 serialnr->high = (unsigned int) (serial >> 32);
734 serialnr->low = (unsigned int) (serial & 0xffffffff);
735 } else {
736 serialnr->high = 0;
737 serialnr->low = 0;
738 }
739}
740#endif
741
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200742/*
743 * Check the SPL header for the "sunxi" variant. If found: parse values
744 * that might have been passed by the loader ("fel" utility), and update
745 * the environment accordingly.
746 */
747static void parse_spl_header(const uint32_t spl_addr)
748{
Andre Przywaracff5c132018-10-25 17:23:04 +0800749 struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
Bernhard Nortmann320e0572016-06-09 07:37:35 +0200750
Andre Przywaracff5c132018-10-25 17:23:04 +0800751 if (spl == INVALID_SPL_HEADER)
Bernhard Nortmann320e0572016-06-09 07:37:35 +0200752 return;
Andre Przywaracff5c132018-10-25 17:23:04 +0800753
Bernhard Nortmann320e0572016-06-09 07:37:35 +0200754 if (!spl->fel_script_address)
755 return;
756
757 if (spl->fel_uEnv_length != 0) {
758 /*
759 * data is expected in uEnv.txt compatible format, so "env
760 * import -t" the string(s) at fel_script_address right away.
761 */
Andre Przywara5a74a392016-09-05 01:32:41 +0100762 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
Bernhard Nortmann320e0572016-06-09 07:37:35 +0200763 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
764 return;
765 }
766 /* otherwise assume .scr format (mkimage-type script) */
Simon Glass018f5302017-08-03 12:22:10 -0600767 env_set_hex("fel_scriptaddr", spl->fel_script_address);
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200768}
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200769
Hans de Goedef2219612016-06-26 13:34:42 +0200770/*
771 * Note this function gets called multiple times.
772 * It must not make any changes to env variables which already exist.
773 */
774static void setup_environment(const void *fdt)
Jonathan Liub41d7d02014-06-14 08:59:09 +0200775{
Paul Kocialkowski8c816572015-03-28 18:35:35 +0100776 char serial_string[17] = { 0 };
Hans de Goedecac5b1c2014-11-26 00:04:24 +0100777 unsigned int sid[4];
Paul Kocialkowski8c816572015-03-28 18:35:35 +0100778 uint8_t mac_addr[6];
Hans de Goedef2219612016-06-26 13:34:42 +0200779 char ethaddr[16];
780 int i, ret;
781
782 ret = sunxi_get_sid(sid);
Hans de Goede3f8ea3b2016-07-29 11:47:03 +0200783 if (ret == 0 && sid[0] != 0) {
784 /*
785 * The single words 1 - 3 of the SID have quite a few bits
786 * which are the same on many models, so we take a crc32
787 * of all 3 words, to get a more unique value.
788 *
789 * Note we only do this on newer SoCs as we cannot change
790 * the algorithm on older SoCs since those have been using
791 * fixed mac-addresses based on only using word 3 for a
792 * long time and changing a fixed mac-address with an
793 * u-boot update is not good.
794 */
795#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
796 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
797 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
798 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
799#endif
800
Hans de Goede97322c32016-07-27 17:58:06 +0200801 /* Ensure the NIC specific bytes of the mac are not all 0 */
802 if ((sid[3] & 0xffffff) == 0)
803 sid[3] |= 0x800000;
804
Hans de Goedef2219612016-06-26 13:34:42 +0200805 for (i = 0; i < 4; i++) {
806 sprintf(ethaddr, "ethernet%d", i);
807 if (!fdt_get_alias(fdt, ethaddr))
808 continue;
809
810 if (i == 0)
811 strcpy(ethaddr, "ethaddr");
812 else
813 sprintf(ethaddr, "eth%daddr", i);
814
Simon Glass00caae62017-08-03 12:22:12 -0600815 if (env_get(ethaddr))
Hans de Goedef2219612016-06-26 13:34:42 +0200816 continue;
817
818 /* Non OUI / registered MAC address */
819 mac_addr[0] = (i << 4) | 0x02;
820 mac_addr[1] = (sid[0] >> 0) & 0xff;
821 mac_addr[2] = (sid[3] >> 24) & 0xff;
822 mac_addr[3] = (sid[3] >> 16) & 0xff;
823 mac_addr[4] = (sid[3] >> 8) & 0xff;
824 mac_addr[5] = (sid[3] >> 0) & 0xff;
825
Simon Glassfd1e9592017-08-03 12:22:11 -0600826 eth_env_set_enetaddr(ethaddr, mac_addr);
Hans de Goedef2219612016-06-26 13:34:42 +0200827 }
828
Simon Glass00caae62017-08-03 12:22:12 -0600829 if (!env_get("serial#")) {
Hans de Goedef2219612016-06-26 13:34:42 +0200830 snprintf(serial_string, sizeof(serial_string),
831 "%08x%08x", sid[0], sid[3]);
832
Simon Glass382bee52017-08-03 12:22:09 -0600833 env_set("serial#", serial_string);
Hans de Goedef2219612016-06-26 13:34:42 +0200834 }
835 }
836}
837
Hans de Goedef2219612016-06-26 13:34:42 +0200838int misc_init_r(void)
839{
Maxime Ripardf4c35232017-08-23 10:08:29 +0200840 uint boot;
Jonathan Liub41d7d02014-06-14 08:59:09 +0200841
Simon Glass382bee52017-08-03 12:22:09 -0600842 env_set("fel_booted", NULL);
843 env_set("fel_scriptaddr", NULL);
Maxime Ripardde86fc32017-08-23 10:12:22 +0200844 env_set("mmc_bootdev", NULL);
Maxime Ripardf4c35232017-08-23 10:08:29 +0200845
846 boot = sunxi_get_boot_device();
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200847 /* determine if we are running in FEL mode */
Maxime Ripardf4c35232017-08-23 10:08:29 +0200848 if (boot == BOOT_DEVICE_BOARD) {
Simon Glass382bee52017-08-03 12:22:09 -0600849 env_set("fel_booted", "1");
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200850 parse_spl_header(SPL_ADDR);
Maxime Ripardde86fc32017-08-23 10:12:22 +0200851 /* or if we booted from MMC, and which one */
852 } else if (boot == BOOT_DEVICE_MMC1) {
853 env_set("mmc_bootdev", "0");
854 } else if (boot == BOOT_DEVICE_MMC2) {
855 env_set("mmc_bootdev", "1");
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200856 }
Bernhard Nortmannaf654d12015-09-17 18:52:52 +0200857
Hans de Goedef2219612016-06-26 13:34:42 +0200858 setup_environment(gd->fdt_blob);
Jonathan Liub41d7d02014-06-14 08:59:09 +0200859
Icenowy Zhenge6ee85a2017-09-28 22:16:38 +0800860#ifdef CONFIG_USB_ETHER
Maxime Ripard90dd2f12017-09-06 22:25:03 +0200861 usb_ether_init();
Icenowy Zhenge6ee85a2017-09-28 22:16:38 +0800862#endif
Maxime Ripard90dd2f12017-09-06 22:25:03 +0200863
Jonathan Liub41d7d02014-06-14 08:59:09 +0200864 return 0;
865}
Luc Verhaegen2d7a0842014-08-13 07:55:07 +0200866
Luc Verhaegen2d7a0842014-08-13 07:55:07 +0200867int ft_board_setup(void *blob, bd_t *bd)
868{
Hans de Goeded75111a2016-03-22 22:51:52 +0100869 int __maybe_unused r;
870
Hans de Goedef2219612016-06-26 13:34:42 +0200871 /*
872 * Call setup_environment again in case the boot fdt has
873 * ethernet aliases the u-boot copy does not have.
874 */
875 setup_environment(blob);
876
Luc Verhaegen2d7a0842014-08-13 07:55:07 +0200877#ifdef CONFIG_VIDEO_DT_SIMPLEFB
Hans de Goeded75111a2016-03-22 22:51:52 +0100878 r = sunxi_simplefb_setup(blob);
879 if (r)
880 return r;
Luc Verhaegen2d7a0842014-08-13 07:55:07 +0200881#endif
Hans de Goeded75111a2016-03-22 22:51:52 +0100882 return 0;
Luc Verhaegen2d7a0842014-08-13 07:55:07 +0200883}
Andre Przywara9ea3c352017-04-26 01:32:44 +0100884
885#ifdef CONFIG_SPL_LOAD_FIT
886int board_fit_config_name_match(const char *name)
887{
Andre Przywaracff5c132018-10-25 17:23:04 +0800888 struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
889 const char *cmp_str = (const char *)spl;
Andre Przywara9ea3c352017-04-26 01:32:44 +0100890
Andre Przywara54254ba2017-04-26 01:32:50 +0100891 /* Check if there is a DT name stored in the SPL header and use that. */
Andre Przywaracff5c132018-10-25 17:23:04 +0800892 if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
Andre Przywara54254ba2017-04-26 01:32:50 +0100893 cmp_str += spl->dt_name_offset;
894 } else {
Andre Przywara9ea3c352017-04-26 01:32:44 +0100895#ifdef CONFIG_DEFAULT_DEVICE_TREE
Andre Przywara54254ba2017-04-26 01:32:50 +0100896 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
Andre Przywara9ea3c352017-04-26 01:32:44 +0100897#else
Andre Przywara54254ba2017-04-26 01:32:50 +0100898 return 0;
Andre Przywara9ea3c352017-04-26 01:32:44 +0100899#endif
Andre Przywara54254ba2017-04-26 01:32:50 +0100900 };
Andre Przywara9ea3c352017-04-26 01:32:44 +0100901
Icenowy Zhengc6c2c852018-10-25 17:23:02 +0800902#ifdef CONFIG_PINE64_DT_SELECTION
Andre Przywara9ea3c352017-04-26 01:32:44 +0100903/* Differentiate the two Pine64 board DTs by their DRAM size. */
904 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
905 if ((gd->ram_size > 512 * 1024 * 1024))
906 return !strstr(name, "plus");
907 else
908 return !!strstr(name, "plus");
909 } else {
910 return strcmp(name, cmp_str);
911 }
Icenowy Zhengc6c2c852018-10-25 17:23:02 +0800912#endif
913 return strcmp(name, cmp_str);
Andre Przywara9ea3c352017-04-26 01:32:44 +0100914}
915#endif