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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00002/*
3 * (C) Copyright 2002 Wolfgang Grandegger, wg@denx.de.
4 *
5 * This driver for AMD PCnet network controllers is derived from the
6 * Linux driver pcnet32.c written 1996-1999 by Thomas Bogendoerfer.
wdenkc6097192002-11-03 00:24:07 +00007 */
8
9#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070010#include <cpu_func.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
wdenkc6097192002-11-03 00:24:07 +000012#include <malloc.h>
13#include <net.h>
Ben Warrene3090532008-08-31 10:08:43 -070014#include <netdev.h>
Simon Glass90526e92020-05-10 11:39:56 -060015#include <asm/cache.h>
wdenkc6097192002-11-03 00:24:07 +000016#include <asm/io.h>
17#include <pci.h>
Simon Glassc05ed002020-05-10 11:40:11 -060018#include <linux/delay.h>
wdenkc6097192002-11-03 00:24:07 +000019
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020020#define PCNET_DEBUG_LEVEL 0 /* 0=off, 1=init, 2=rx/tx */
wdenkc6097192002-11-03 00:24:07 +000021
Wolfgang Denk138b6082011-11-05 05:12:58 +000022#define PCNET_DEBUG1(fmt,args...) \
23 debug_cond(PCNET_DEBUG_LEVEL > 0, fmt ,##args)
24#define PCNET_DEBUG2(fmt,args...) \
25 debug_cond(PCNET_DEBUG_LEVEL > 1, fmt ,##args)
wdenkc6097192002-11-03 00:24:07 +000026
wdenkc6097192002-11-03 00:24:07 +000027/*
28 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
29 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
30 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
31 */
32#define PCNET_LOG_TX_BUFFERS 0
33#define PCNET_LOG_RX_BUFFERS 2
34
35#define TX_RING_SIZE (1 << (PCNET_LOG_TX_BUFFERS))
36#define TX_RING_LEN_BITS ((PCNET_LOG_TX_BUFFERS) << 12)
37
38#define RX_RING_SIZE (1 << (PCNET_LOG_RX_BUFFERS))
39#define RX_RING_LEN_BITS ((PCNET_LOG_RX_BUFFERS) << 4)
40
41#define PKT_BUF_SZ 1544
42
43/* The PCNET Rx and Tx ring descriptors. */
44struct pcnet_rx_head {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020045 u32 base;
46 s16 buf_length;
47 s16 status;
48 u32 msg_length;
49 u32 reserved;
wdenkc6097192002-11-03 00:24:07 +000050};
51
52struct pcnet_tx_head {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020053 u32 base;
54 s16 length;
55 s16 status;
56 u32 misc;
57 u32 reserved;
wdenkc6097192002-11-03 00:24:07 +000058};
59
60/* The PCNET 32-Bit initialization block, described in databook. */
61struct pcnet_init_block {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020062 u16 mode;
63 u16 tlen_rlen;
64 u8 phys_addr[6];
65 u16 reserved;
66 u32 filter[2];
67 /* Receive and transmit ring base, along with extra bits. */
68 u32 rx_ring;
69 u32 tx_ring;
70 u32 reserved2;
wdenkc6097192002-11-03 00:24:07 +000071};
72
Paul Burtonf1ae3822014-04-07 16:41:46 +010073struct pcnet_uncached_priv {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020074 struct pcnet_rx_head rx_ring[RX_RING_SIZE];
75 struct pcnet_tx_head tx_ring[TX_RING_SIZE];
76 struct pcnet_init_block init_block;
Paul Burtonf1ae3822014-04-07 16:41:46 +010077};
78
79typedef struct pcnet_priv {
80 struct pcnet_uncached_priv *uc;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020081 /* Receive Buffer space */
Paul Burtona354ddc2014-04-07 16:41:47 +010082 unsigned char (*rx_buf)[RX_RING_SIZE][PKT_BUF_SZ + 4];
Wolfgang Denk11ea26f2008-04-24 23:44:26 +020083 int cur_rx;
84 int cur_tx;
wdenkc6097192002-11-03 00:24:07 +000085} pcnet_priv_t;
86
87static pcnet_priv_t *lp;
88
89/* Offsets from base I/O address for WIO mode */
90#define PCNET_RDP 0x10
91#define PCNET_RAP 0x12
92#define PCNET_RESET 0x14
93#define PCNET_BDP 0x16
94
Paul Burton6011dab2013-11-08 11:18:43 +000095static u16 pcnet_read_csr(struct eth_device *dev, int index)
wdenkc6097192002-11-03 00:24:07 +000096{
Daniel Schwierzeck85105802020-05-03 19:43:32 +020097 void __iomem *base = (void __iomem *)dev->iobase;
98
99 writew(index, base + PCNET_RAP);
100 return readw(base + PCNET_RDP);
wdenkc6097192002-11-03 00:24:07 +0000101}
102
Paul Burton6011dab2013-11-08 11:18:43 +0000103static void pcnet_write_csr(struct eth_device *dev, int index, u16 val)
wdenkc6097192002-11-03 00:24:07 +0000104{
Daniel Schwierzeck85105802020-05-03 19:43:32 +0200105 void __iomem *base = (void __iomem *)dev->iobase;
106
107 writew(index, base + PCNET_RAP);
108 writew(val, base + PCNET_RDP);
wdenkc6097192002-11-03 00:24:07 +0000109}
110
Paul Burton6011dab2013-11-08 11:18:43 +0000111static u16 pcnet_read_bcr(struct eth_device *dev, int index)
wdenkc6097192002-11-03 00:24:07 +0000112{
Daniel Schwierzeck85105802020-05-03 19:43:32 +0200113 void __iomem *base = (void __iomem *)dev->iobase;
114
115 writew(index, base + PCNET_RAP);
116 return readw(base + PCNET_BDP);
wdenkc6097192002-11-03 00:24:07 +0000117}
118
Paul Burton6011dab2013-11-08 11:18:43 +0000119static void pcnet_write_bcr(struct eth_device *dev, int index, u16 val)
wdenkc6097192002-11-03 00:24:07 +0000120{
Daniel Schwierzeck85105802020-05-03 19:43:32 +0200121 void __iomem *base = (void __iomem *)dev->iobase;
122
123 writew(index, base + PCNET_RAP);
124 writew(val, base + PCNET_BDP);
wdenkc6097192002-11-03 00:24:07 +0000125}
126
Paul Burton6011dab2013-11-08 11:18:43 +0000127static void pcnet_reset(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000128{
Daniel Schwierzeck85105802020-05-03 19:43:32 +0200129 void __iomem *base = (void __iomem *)dev->iobase;
130
131 readw(base + PCNET_RESET);
wdenkc6097192002-11-03 00:24:07 +0000132}
133
Paul Burton6011dab2013-11-08 11:18:43 +0000134static int pcnet_check(struct eth_device *dev)
wdenkc6097192002-11-03 00:24:07 +0000135{
Daniel Schwierzeck85105802020-05-03 19:43:32 +0200136 void __iomem *base = (void __iomem *)dev->iobase;
137
138 writew(88, base + PCNET_RAP);
139 return readw(base + PCNET_RAP) == 88;
wdenkc6097192002-11-03 00:24:07 +0000140}
141
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200142static int pcnet_init (struct eth_device *dev, bd_t * bis);
Joe Hershbergerf92a1512012-05-22 18:09:56 +0000143static int pcnet_send(struct eth_device *dev, void *packet, int length);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200144static int pcnet_recv (struct eth_device *dev);
145static void pcnet_halt (struct eth_device *dev);
146static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
wdenkc6097192002-11-03 00:24:07 +0000147
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100148static inline pci_addr_t pcnet_virt_to_mem(const struct eth_device *dev,
Paul Burton4677d662016-05-26 14:49:34 +0100149 void *addr)
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100150{
Paul Burton442d2e02016-05-26 14:49:35 +0100151 pci_dev_t devbusfn = (pci_dev_t)(unsigned long)dev->priv;
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100152 void *virt_addr = addr;
153
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100154 return pci_virt_to_mem(devbusfn, virt_addr);
155}
wdenkc6097192002-11-03 00:24:07 +0000156
157static struct pci_device_id supported[] = {
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200158 {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE},
159 {}
wdenkc6097192002-11-03 00:24:07 +0000160};
161
162
Paul Burton6011dab2013-11-08 11:18:43 +0000163int pcnet_initialize(bd_t *bis)
wdenkc6097192002-11-03 00:24:07 +0000164{
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200165 pci_dev_t devbusfn;
166 struct eth_device *dev;
167 u16 command, status;
168 int dev_nr = 0;
Paul Burtonbed1ca32016-05-26 17:32:29 +0100169 u32 bar;
wdenkc6097192002-11-03 00:24:07 +0000170
Paul Burton6011dab2013-11-08 11:18:43 +0000171 PCNET_DEBUG1("\npcnet_initialize...\n");
wdenkc6097192002-11-03 00:24:07 +0000172
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200173 for (dev_nr = 0;; dev_nr++) {
wdenkc6097192002-11-03 00:24:07 +0000174
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200175 /*
176 * Find the PCnet PCI device(s).
177 */
Paul Burton6011dab2013-11-08 11:18:43 +0000178 devbusfn = pci_find_devices(supported, dev_nr);
179 if (devbusfn < 0)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200180 break;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200181
182 /*
183 * Allocate and pre-fill the device structure.
184 */
Paul Burton6011dab2013-11-08 11:18:43 +0000185 dev = (struct eth_device *)malloc(sizeof(*dev));
Nobuhiro Iwamatsu5ed0eec2010-10-19 14:03:45 +0900186 if (!dev) {
187 printf("pcnet: Can not allocate memory\n");
188 break;
189 }
190 memset(dev, 0, sizeof(*dev));
Paul Burton442d2e02016-05-26 14:49:35 +0100191 dev->priv = (void *)(unsigned long)devbusfn;
Paul Burton6011dab2013-11-08 11:18:43 +0000192 sprintf(dev->name, "pcnet#%d", dev_nr);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200193
194 /*
195 * Setup the PCI device.
196 */
Marek Vasut69529c92020-04-18 05:11:05 +0200197 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
198 dev->iobase = pci_mem_to_phys(devbusfn, bar);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200199 dev->iobase &= ~0xf;
200
Paul Burton442d2e02016-05-26 14:49:35 +0100201 PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
202 dev->name, devbusfn, (unsigned long)dev->iobase);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200203
Marek Vasut69529c92020-04-18 05:11:05 +0200204 command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
Paul Burton6011dab2013-11-08 11:18:43 +0000205 pci_write_config_word(devbusfn, PCI_COMMAND, command);
206 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200207 if ((status & command) != command) {
Paul Burton6011dab2013-11-08 11:18:43 +0000208 printf("%s: Couldn't enable IO access or Bus Mastering\n",
209 dev->name);
210 free(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200211 continue;
212 }
213
Paul Burton6011dab2013-11-08 11:18:43 +0000214 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200215
216 /*
217 * Probe the PCnet chip.
218 */
Paul Burton6011dab2013-11-08 11:18:43 +0000219 if (pcnet_probe(dev, bis, dev_nr) < 0) {
220 free(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200221 continue;
222 }
223
224 /*
225 * Setup device structure and register the driver.
226 */
227 dev->init = pcnet_init;
228 dev->halt = pcnet_halt;
229 dev->send = pcnet_send;
230 dev->recv = pcnet_recv;
231
Paul Burton6011dab2013-11-08 11:18:43 +0000232 eth_register(dev);
wdenkc6097192002-11-03 00:24:07 +0000233 }
234
Paul Burton6011dab2013-11-08 11:18:43 +0000235 udelay(10 * 1000);
wdenkc6097192002-11-03 00:24:07 +0000236
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200237 return dev_nr;
wdenkc6097192002-11-03 00:24:07 +0000238}
239
Paul Burton6011dab2013-11-08 11:18:43 +0000240static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
wdenkc6097192002-11-03 00:24:07 +0000241{
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200242 int chip_version;
243 char *chipname;
244
wdenkc6097192002-11-03 00:24:07 +0000245#ifdef PCNET_HAS_PROM
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200246 int i;
wdenkc6097192002-11-03 00:24:07 +0000247#endif
248
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200249 /* Reset the PCnet controller */
Paul Burton6011dab2013-11-08 11:18:43 +0000250 pcnet_reset(dev);
wdenkc6097192002-11-03 00:24:07 +0000251
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200252 /* Check if register access is working */
Paul Burton6011dab2013-11-08 11:18:43 +0000253 if (pcnet_read_csr(dev, 0) != 4 || !pcnet_check(dev)) {
254 printf("%s: CSR register access check failed\n", dev->name);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200255 return -1;
256 }
wdenkc6097192002-11-03 00:24:07 +0000257
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200258 /* Identify the chip */
259 chip_version =
Paul Burton6011dab2013-11-08 11:18:43 +0000260 pcnet_read_csr(dev, 88) | (pcnet_read_csr(dev, 89) << 16);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200261 if ((chip_version & 0xfff) != 0x003)
262 return -1;
263 chip_version = (chip_version >> 12) & 0xffff;
264 switch (chip_version) {
265 case 0x2621:
266 chipname = "PCnet/PCI II 79C970A"; /* PCI */
267 break;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200268 case 0x2625:
269 chipname = "PCnet/FAST III 79C973"; /* PCI */
270 break;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200271 case 0x2627:
272 chipname = "PCnet/FAST III 79C975"; /* PCI */
273 break;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200274 default:
Paul Burton6011dab2013-11-08 11:18:43 +0000275 printf("%s: PCnet version %#x not supported\n",
276 dev->name, chip_version);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200277 return -1;
278 }
wdenkc6097192002-11-03 00:24:07 +0000279
Paul Burton6011dab2013-11-08 11:18:43 +0000280 PCNET_DEBUG1("AMD %s\n", chipname);
wdenkc6097192002-11-03 00:24:07 +0000281
282#ifdef PCNET_HAS_PROM
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200283 /*
284 * In most chips, after a chip reset, the ethernet address is read from
285 * the station address PROM at the base address and programmed into the
286 * "Physical Address Registers" CSR12-14.
287 */
288 for (i = 0; i < 3; i++) {
289 unsigned int val;
290
Paul Burton6011dab2013-11-08 11:18:43 +0000291 val = pcnet_read_csr(dev, i + 12) & 0x0ffff;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200292 /* There may be endianness issues here. */
293 dev->enetaddr[2 * i] = val & 0x0ff;
294 dev->enetaddr[2 * i + 1] = (val >> 8) & 0x0ff;
295 }
wdenkc6097192002-11-03 00:24:07 +0000296#endif /* PCNET_HAS_PROM */
297
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200298 return 0;
wdenkc6097192002-11-03 00:24:07 +0000299}
300
Paul Burton6011dab2013-11-08 11:18:43 +0000301static int pcnet_init(struct eth_device *dev, bd_t *bis)
wdenkc6097192002-11-03 00:24:07 +0000302{
Paul Burtonf1ae3822014-04-07 16:41:46 +0100303 struct pcnet_uncached_priv *uc;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200304 int i, val;
Paul Burton442d2e02016-05-26 14:49:35 +0100305 unsigned long addr;
wdenkc6097192002-11-03 00:24:07 +0000306
Paul Burton6011dab2013-11-08 11:18:43 +0000307 PCNET_DEBUG1("%s: pcnet_init...\n", dev->name);
wdenkc6097192002-11-03 00:24:07 +0000308
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200309 /* Switch pcnet to 32bit mode */
Paul Burton6011dab2013-11-08 11:18:43 +0000310 pcnet_write_bcr(dev, 20, 2);
wdenkc6097192002-11-03 00:24:07 +0000311
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200312 /* Set/reset autoselect bit */
Paul Burton6011dab2013-11-08 11:18:43 +0000313 val = pcnet_read_bcr(dev, 2) & ~2;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200314 val |= 2;
Paul Burton6011dab2013-11-08 11:18:43 +0000315 pcnet_write_bcr(dev, 2, val);
wdenkc6097192002-11-03 00:24:07 +0000316
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200317 /* Enable auto negotiate, setup, disable fd */
Paul Burton6011dab2013-11-08 11:18:43 +0000318 val = pcnet_read_bcr(dev, 32) & ~0x98;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200319 val |= 0x20;
Paul Burton6011dab2013-11-08 11:18:43 +0000320 pcnet_write_bcr(dev, 32, val);
wdenkc6097192002-11-03 00:24:07 +0000321
wdenkc6097192002-11-03 00:24:07 +0000322 /*
Paul Burton62715a22013-11-08 11:18:46 +0000323 * Enable NOUFLO on supported controllers, with the transmit
324 * start point set to the full packet. This will cause entire
325 * packets to be buffered by the ethernet controller before
326 * transmission, eliminating underflows which are common on
327 * slower devices. Controllers which do not support NOUFLO will
328 * simply be left with a larger transmit FIFO threshold.
329 */
330 val = pcnet_read_bcr(dev, 18);
331 val |= 1 << 11;
332 pcnet_write_bcr(dev, 18, val);
333 val = pcnet_read_csr(dev, 80);
334 val |= 0x3 << 10;
335 pcnet_write_csr(dev, 80, val);
336
337 /*
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200338 * We only maintain one structure because the drivers will never
339 * be used concurrently. In 32bit mode the RX and TX ring entries
340 * must be aligned on 16-byte boundaries.
wdenkc6097192002-11-03 00:24:07 +0000341 */
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200342 if (lp == NULL) {
Paul Burton442d2e02016-05-26 14:49:35 +0100343 addr = (unsigned long)malloc(sizeof(pcnet_priv_t) + 0x10);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200344 addr = (addr + 0xf) & ~0xf;
Paul Burton6011dab2013-11-08 11:18:43 +0000345 lp = (pcnet_priv_t *)addr;
Paul Burtonf1ae3822014-04-07 16:41:46 +0100346
Paul Burton442d2e02016-05-26 14:49:35 +0100347 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
348 sizeof(*lp->uc));
Paul Burtonf1ae3822014-04-07 16:41:46 +0100349 flush_dcache_range(addr, addr + sizeof(*lp->uc));
Marek Vasut3c0bcb92020-04-18 02:32:19 +0200350 addr = (unsigned long)map_physmem(addr,
351 roundup(sizeof(*lp->uc), ARCH_DMA_MINALIGN),
352 MAP_NOCACHE);
Paul Burtonf1ae3822014-04-07 16:41:46 +0100353 lp->uc = (struct pcnet_uncached_priv *)addr;
Paul Burtona354ddc2014-04-07 16:41:47 +0100354
Paul Burton442d2e02016-05-26 14:49:35 +0100355 addr = (unsigned long)memalign(ARCH_DMA_MINALIGN,
356 sizeof(*lp->rx_buf));
Paul Burtona354ddc2014-04-07 16:41:47 +0100357 flush_dcache_range(addr, addr + sizeof(*lp->rx_buf));
358 lp->rx_buf = (void *)addr;
wdenkc6097192002-11-03 00:24:07 +0000359 }
wdenkc6097192002-11-03 00:24:07 +0000360
Paul Burtonf1ae3822014-04-07 16:41:46 +0100361 uc = lp->uc;
362
363 uc->init_block.mode = cpu_to_le16(0x0000);
364 uc->init_block.filter[0] = 0x00000000;
365 uc->init_block.filter[1] = 0x00000000;
wdenkc6097192002-11-03 00:24:07 +0000366
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200367 /*
368 * Initialize the Rx ring.
369 */
370 lp->cur_rx = 0;
371 for (i = 0; i < RX_RING_SIZE; i++) {
Paul Burton4677d662016-05-26 14:49:34 +0100372 addr = pcnet_virt_to_mem(dev, (*lp->rx_buf)[i]);
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100373 uc->rx_ring[i].base = cpu_to_le32(addr);
Paul Burtonf1ae3822014-04-07 16:41:46 +0100374 uc->rx_ring[i].buf_length = cpu_to_le16(-PKT_BUF_SZ);
375 uc->rx_ring[i].status = cpu_to_le16(0x8000);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200376 PCNET_DEBUG1
377 ("Rx%d: base=0x%x buf_length=0x%hx status=0x%hx\n", i,
Paul Burtonf1ae3822014-04-07 16:41:46 +0100378 uc->rx_ring[i].base, uc->rx_ring[i].buf_length,
379 uc->rx_ring[i].status);
wdenkc6097192002-11-03 00:24:07 +0000380 }
wdenkc6097192002-11-03 00:24:07 +0000381
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200382 /*
383 * Initialize the Tx ring. The Tx buffer address is filled in as
384 * needed, but we do need to clear the upper ownership bit.
385 */
386 lp->cur_tx = 0;
387 for (i = 0; i < TX_RING_SIZE; i++) {
Paul Burtonf1ae3822014-04-07 16:41:46 +0100388 uc->tx_ring[i].base = 0;
389 uc->tx_ring[i].status = 0;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200390 }
391
392 /*
393 * Setup Init Block.
394 */
Paul Burtonf1ae3822014-04-07 16:41:46 +0100395 PCNET_DEBUG1("Init block at 0x%p: MAC", &lp->uc->init_block);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200396
397 for (i = 0; i < 6; i++) {
Paul Burtonf1ae3822014-04-07 16:41:46 +0100398 lp->uc->init_block.phys_addr[i] = dev->enetaddr[i];
399 PCNET_DEBUG1(" %02x", lp->uc->init_block.phys_addr[i]);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200400 }
401
Paul Burtonf1ae3822014-04-07 16:41:46 +0100402 uc->init_block.tlen_rlen = cpu_to_le16(TX_RING_LEN_BITS |
Paul Burton6011dab2013-11-08 11:18:43 +0000403 RX_RING_LEN_BITS);
Paul Burton4677d662016-05-26 14:49:34 +0100404 addr = pcnet_virt_to_mem(dev, uc->rx_ring);
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100405 uc->init_block.rx_ring = cpu_to_le32(addr);
Paul Burton4677d662016-05-26 14:49:34 +0100406 addr = pcnet_virt_to_mem(dev, uc->tx_ring);
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100407 uc->init_block.tx_ring = cpu_to_le32(addr);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200408
Paul Burton6011dab2013-11-08 11:18:43 +0000409 PCNET_DEBUG1("\ntlen_rlen=0x%x rx_ring=0x%x tx_ring=0x%x\n",
Paul Burtonf1ae3822014-04-07 16:41:46 +0100410 uc->init_block.tlen_rlen,
411 uc->init_block.rx_ring, uc->init_block.tx_ring);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200412
413 /*
414 * Tell the controller where the Init Block is located.
415 */
Paul Burtonf1ae3822014-04-07 16:41:46 +0100416 barrier();
Paul Burton4677d662016-05-26 14:49:34 +0100417 addr = pcnet_virt_to_mem(dev, &lp->uc->init_block);
Paul Burton6011dab2013-11-08 11:18:43 +0000418 pcnet_write_csr(dev, 1, addr & 0xffff);
419 pcnet_write_csr(dev, 2, (addr >> 16) & 0xffff);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200420
Paul Burton6011dab2013-11-08 11:18:43 +0000421 pcnet_write_csr(dev, 4, 0x0915);
422 pcnet_write_csr(dev, 0, 0x0001); /* start */
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200423
424 /* Wait for Init Done bit */
425 for (i = 10000; i > 0; i--) {
Paul Burton6011dab2013-11-08 11:18:43 +0000426 if (pcnet_read_csr(dev, 0) & 0x0100)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200427 break;
Paul Burton6011dab2013-11-08 11:18:43 +0000428 udelay(10);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200429 }
430 if (i <= 0) {
Paul Burton6011dab2013-11-08 11:18:43 +0000431 printf("%s: TIMEOUT: controller init failed\n", dev->name);
432 pcnet_reset(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200433 return -1;
434 }
435
436 /*
437 * Finally start network controller operation.
438 */
Paul Burton6011dab2013-11-08 11:18:43 +0000439 pcnet_write_csr(dev, 0, 0x0002);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200440
441 return 0;
wdenkc6097192002-11-03 00:24:07 +0000442}
443
Joe Hershbergerf92a1512012-05-22 18:09:56 +0000444static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
wdenkc6097192002-11-03 00:24:07 +0000445{
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200446 int i, status;
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100447 u32 addr;
Paul Burtonf1ae3822014-04-07 16:41:46 +0100448 struct pcnet_tx_head *entry = &lp->uc->tx_ring[lp->cur_tx];
wdenkc6097192002-11-03 00:24:07 +0000449
Paul Burton6011dab2013-11-08 11:18:43 +0000450 PCNET_DEBUG2("Tx%d: %d bytes from 0x%p ", lp->cur_tx, pkt_len,
451 packet);
wdenkc6097192002-11-03 00:24:07 +0000452
Paul Burtonf3ac8662013-11-08 11:18:45 +0000453 flush_dcache_range((unsigned long)packet,
454 (unsigned long)packet + pkt_len);
455
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200456 /* Wait for completion by testing the OWN bit */
457 for (i = 1000; i > 0; i--) {
Paul Burton6fb49e42014-04-07 16:41:48 +0100458 status = readw(&entry->status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200459 if ((status & 0x8000) == 0)
460 break;
Paul Burton6011dab2013-11-08 11:18:43 +0000461 udelay(100);
462 PCNET_DEBUG2(".");
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200463 }
464 if (i <= 0) {
Paul Burton6011dab2013-11-08 11:18:43 +0000465 printf("%s: TIMEOUT: Tx%d failed (status = 0x%x)\n",
466 dev->name, lp->cur_tx, status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200467 pkt_len = 0;
468 goto failure;
469 }
wdenkc6097192002-11-03 00:24:07 +0000470
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200471 /*
472 * Setup Tx ring. Caution: the write order is important here,
473 * set the status with the "ownership" bits last.
474 */
Paul Burton4677d662016-05-26 14:49:34 +0100475 addr = pcnet_virt_to_mem(dev, packet);
Paul Burton6fb49e42014-04-07 16:41:48 +0100476 writew(-pkt_len, &entry->length);
477 writel(0, &entry->misc);
Daniel Schwierzeckdf50b3b2016-01-12 21:48:24 +0100478 writel(addr, &entry->base);
Paul Burton6fb49e42014-04-07 16:41:48 +0100479 writew(0x8300, &entry->status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200480
481 /* Trigger an immediate send poll. */
Paul Burton6011dab2013-11-08 11:18:43 +0000482 pcnet_write_csr(dev, 0, 0x0008);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200483
484 failure:
485 if (++lp->cur_tx >= TX_RING_SIZE)
486 lp->cur_tx = 0;
487
Paul Burton6011dab2013-11-08 11:18:43 +0000488 PCNET_DEBUG2("done\n");
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200489 return pkt_len;
wdenkc6097192002-11-03 00:24:07 +0000490}
491
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200492static int pcnet_recv (struct eth_device *dev)
493{
494 struct pcnet_rx_head *entry;
Paul Burtona354ddc2014-04-07 16:41:47 +0100495 unsigned char *buf;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200496 int pkt_len = 0;
Paul Burton6fb49e42014-04-07 16:41:48 +0100497 u16 status, err_status;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200498
499 while (1) {
Paul Burtonf1ae3822014-04-07 16:41:46 +0100500 entry = &lp->uc->rx_ring[lp->cur_rx];
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200501 /*
502 * If we own the next entry, it's a new packet. Send it up.
503 */
Paul Burton6fb49e42014-04-07 16:41:48 +0100504 status = readw(&entry->status);
Paul Burton6011dab2013-11-08 11:18:43 +0000505 if ((status & 0x8000) != 0)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200506 break;
Paul Burton6fb49e42014-04-07 16:41:48 +0100507 err_status = status >> 8;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200508
Paul Burton6fb49e42014-04-07 16:41:48 +0100509 if (err_status != 0x03) { /* There was an error. */
Paul Burton6011dab2013-11-08 11:18:43 +0000510 printf("%s: Rx%d", dev->name, lp->cur_rx);
Paul Burton6fb49e42014-04-07 16:41:48 +0100511 PCNET_DEBUG1(" (status=0x%x)", err_status);
512 if (err_status & 0x20)
Paul Burton6011dab2013-11-08 11:18:43 +0000513 printf(" Frame");
Paul Burton6fb49e42014-04-07 16:41:48 +0100514 if (err_status & 0x10)
Paul Burton6011dab2013-11-08 11:18:43 +0000515 printf(" Overflow");
Paul Burton6fb49e42014-04-07 16:41:48 +0100516 if (err_status & 0x08)
Paul Burton6011dab2013-11-08 11:18:43 +0000517 printf(" CRC");
Paul Burton6fb49e42014-04-07 16:41:48 +0100518 if (err_status & 0x04)
Paul Burton6011dab2013-11-08 11:18:43 +0000519 printf(" Fifo");
520 printf(" Error\n");
Paul Burton6fb49e42014-04-07 16:41:48 +0100521 status &= 0x03ff;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200522
523 } else {
Paul Burton6fb49e42014-04-07 16:41:48 +0100524 pkt_len = (readl(&entry->msg_length) & 0xfff) - 4;
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200525 if (pkt_len < 60) {
Paul Burton6011dab2013-11-08 11:18:43 +0000526 printf("%s: Rx%d: invalid packet length %d\n",
527 dev->name, lp->cur_rx, pkt_len);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200528 } else {
Paul Burtona354ddc2014-04-07 16:41:47 +0100529 buf = (*lp->rx_buf)[lp->cur_rx];
530 invalidate_dcache_range((unsigned long)buf,
531 (unsigned long)buf + pkt_len);
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500532 net_process_received_packet(buf, pkt_len);
Paul Burton6011dab2013-11-08 11:18:43 +0000533 PCNET_DEBUG2("Rx%d: %d bytes from 0x%p\n",
Paul Burtona354ddc2014-04-07 16:41:47 +0100534 lp->cur_rx, pkt_len, buf);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200535 }
536 }
Paul Burton6fb49e42014-04-07 16:41:48 +0100537
538 status |= 0x8000;
539 writew(status, &entry->status);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200540
541 if (++lp->cur_rx >= RX_RING_SIZE)
542 lp->cur_rx = 0;
543 }
544 return pkt_len;
545}
546
Paul Burton6011dab2013-11-08 11:18:43 +0000547static void pcnet_halt(struct eth_device *dev)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200548{
549 int i;
550
Paul Burton6011dab2013-11-08 11:18:43 +0000551 PCNET_DEBUG1("%s: pcnet_halt...\n", dev->name);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200552
553 /* Reset the PCnet controller */
Paul Burton6011dab2013-11-08 11:18:43 +0000554 pcnet_reset(dev);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200555
556 /* Wait for Stop bit */
557 for (i = 1000; i > 0; i--) {
Paul Burton6011dab2013-11-08 11:18:43 +0000558 if (pcnet_read_csr(dev, 0) & 0x4)
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200559 break;
Paul Burton6011dab2013-11-08 11:18:43 +0000560 udelay(10);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200561 }
Paul Burton6011dab2013-11-08 11:18:43 +0000562 if (i <= 0)
563 printf("%s: TIMEOUT: controller reset failed\n", dev->name);
Wolfgang Denk11ea26f2008-04-24 23:44:26 +0200564}