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Dzmitry Sankouski90496af2021-10-17 13:44:30 +03001// SPDX-License-Identifier: BSD-3-Clause
2/*
3 * Clock drivers for Qualcomm SDM845
4 *
5 * (C) Copyright 2017 Jorge Ramirez Ortiz <jorge.ramirez-ortiz@linaro.org>
6 * (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
7 *
8 * Based on Little Kernel driver, simplified
9 */
10
11#include <common.h>
12#include <clk-uclass.h>
13#include <dm.h>
Caleb Connolly6985e302023-11-07 12:41:02 +000014#include <linux/delay.h>
Dzmitry Sankouski90496af2021-10-17 13:44:30 +030015#include <errno.h>
16#include <asm/io.h>
17#include <linux/bitops.h>
Sumit Gargffa79282022-07-12 12:42:06 +053018#include <dt-bindings/clock/qcom,gcc-sdm845.h>
Konrad Dybciod9935732023-11-07 12:41:01 +000019
Caleb Connolly5bb0df62023-11-07 12:40:59 +000020#include "clock-qcom.h"
Dzmitry Sankouski90496af2021-10-17 13:44:30 +030021
Caleb Connollyc94f9e92023-11-07 12:41:03 +000022#define SE9_AHB_CBCR 0x25004
23#define SE9_UART_APPS_CBCR 0x29004
24#define SE9_UART_APPS_CMD_RCGR 0x18148
25#define SE9_UART_APPS_CFG_RCGR 0x1814C
26#define SE9_UART_APPS_M 0x18150
27#define SE9_UART_APPS_N 0x18154
28#define SE9_UART_APPS_D 0x18158
29
Dzmitry Sankouski90496af2021-10-17 13:44:30 +030030#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
31
32struct freq_tbl {
33 uint freq;
34 uint src;
35 u8 pre_div;
36 u16 m;
37 u16 n;
38};
39
40static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
41 F(7372800, CFG_CLK_SRC_GPLL0_EVEN, 1, 384, 15625),
42 F(14745600, CFG_CLK_SRC_GPLL0_EVEN, 1, 768, 15625),
43 F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
44 F(29491200, CFG_CLK_SRC_GPLL0_EVEN, 1, 1536, 15625),
45 F(32000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 75),
46 F(48000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 25),
47 F(64000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 16, 75),
48 F(80000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 4, 15),
49 F(96000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 8, 25),
50 F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
51 F(102400000, CFG_CLK_SRC_GPLL0_EVEN, 1, 128, 375),
52 F(112000000, CFG_CLK_SRC_GPLL0_EVEN, 1, 28, 75),
53 F(117964800, CFG_CLK_SRC_GPLL0_EVEN, 1, 6144, 15625),
54 F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
55 F(128000000, CFG_CLK_SRC_GPLL0, 1, 16, 75),
56 { }
57};
58
59static const struct bcr_regs uart2_regs = {
60 .cfg_rcgr = SE9_UART_APPS_CFG_RCGR,
61 .cmd_rcgr = SE9_UART_APPS_CMD_RCGR,
62 .M = SE9_UART_APPS_M,
63 .N = SE9_UART_APPS_N,
64 .D = SE9_UART_APPS_D,
65};
66
67const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
68{
69 if (!f)
70 return NULL;
71
72 if (!f->freq)
73 return f;
74
75 for (; f->freq; f++)
76 if (rate <= f->freq)
77 return f;
78
79 /* Default to our fastest rate */
80 return f - 1;
81}
82
Caleb Connollyc94f9e92023-11-07 12:41:03 +000083static ulong sdm845_clk_set_rate(struct clk *clk, ulong rate)
Dzmitry Sankouski90496af2021-10-17 13:44:30 +030084{
85 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
Caleb Connolly6985e302023-11-07 12:41:02 +000086 const struct freq_tbl *freq;
Dzmitry Sankouski90496af2021-10-17 13:44:30 +030087
88 switch (clk->id) {
Caleb Connolly6985e302023-11-07 12:41:02 +000089 case GCC_QUPV3_WRAP1_S1_CLK: /* UART9 */
90 freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
91 clk_rcg_set_rate_mnd(priv->base, &uart2_regs,
Caleb Connolly97d7ed32023-11-07 12:41:04 +000092 freq->pre_div, freq->m, freq->n, freq->src, 16);
Caleb Connolly6985e302023-11-07 12:41:02 +000093 return freq->freq;
Dzmitry Sankouski90496af2021-10-17 13:44:30 +030094 default:
95 return 0;
96 }
97}
Sumit Gargc9e384e2022-08-04 19:57:14 +053098
Caleb Connolly6985e302023-11-07 12:41:02 +000099static const struct gate_clk sdm845_clks[] = {
100 GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, 0x00000400),
101 GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, 0x00000800),
102 GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, 0x00001000),
103 GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x5200c, 0x00002000),
104 GATE_CLK(GCC_QUPV3_WRAP0_S4_CLK, 0x5200c, 0x00004000),
105 GATE_CLK(GCC_QUPV3_WRAP0_S5_CLK, 0x5200c, 0x00008000),
106 GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x5200c, 0x00010000),
107 GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x5200c, 0x00020000),
108 GATE_CLK(GCC_QUPV3_WRAP1_S0_CLK, 0x5200c, 0x00400000),
109 GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x5200c, 0x00800000),
110 GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x5200c, 0x02000000),
111 GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, 0x04000000),
112 GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, 0x08000000),
113 GATE_CLK(GCC_QUPV3_WRAP1_S6_CLK, 0x5200c, 0x10000000),
114 GATE_CLK(GCC_QUPV3_WRAP1_S7_CLK, 0x5200c, 0x20000000),
115 GATE_CLK(GCC_QUPV3_WRAP_0_M_AHB_CLK, 0x5200c, 0x00000040),
116 GATE_CLK(GCC_QUPV3_WRAP_0_S_AHB_CLK, 0x5200c, 0x00000080),
117 GATE_CLK(GCC_QUPV3_WRAP_1_M_AHB_CLK, 0x5200c, 0x00100000),
118 GATE_CLK(GCC_QUPV3_WRAP_1_S_AHB_CLK, 0x5200c, 0x00200000),
119 GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, 0x00000001),
120 GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, 0x00000001),
121 GATE_CLK(GCC_SDCC4_AHB_CLK, 0x16008, 0x00000001),
122 GATE_CLK(GCC_SDCC4_APPS_CLK, 0x16004, 0x00000001),
123 GATE_CLK(GCC_UFS_CARD_AHB_CLK, 0x75010, 0x00000001),
124 GATE_CLK(GCC_UFS_CARD_AXI_CLK, 0x7500c, 0x00000001),
125 GATE_CLK(GCC_UFS_CARD_CLKREF_CLK, 0x8c004, 0x00000001),
126 GATE_CLK(GCC_UFS_CARD_ICE_CORE_CLK, 0x75058, 0x00000001),
127 GATE_CLK(GCC_UFS_CARD_PHY_AUX_CLK, 0x7508c, 0x00000001),
128 GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_0_CLK, 0x75018, 0x00000001),
129 GATE_CLK(GCC_UFS_CARD_RX_SYMBOL_1_CLK, 0x750a8, 0x00000001),
130 GATE_CLK(GCC_UFS_CARD_TX_SYMBOL_0_CLK, 0x75014, 0x00000001),
131 GATE_CLK(GCC_UFS_CARD_UNIPRO_CORE_CLK, 0x75054, 0x00000001),
132 GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, 0x00000001),
133 GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77010, 0x00000001),
134 GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x7700c, 0x00000001),
135 GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77058, 0x00000001),
136 GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7708c, 0x00000001),
137 GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77018, 0x00000001),
138 GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770a8, 0x00000001),
139 GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77014, 0x00000001),
140 GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77054, 0x00000001),
141 GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x0f00c, 0x00000001),
142 GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x0f014, 0x00000001),
143 GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x0f010, 0x00000001),
144 GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x1000c, 0x00000001),
145 GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x10014, 0x00000001),
146 GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x10010, 0x00000001),
147 GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c008, 0x00000001),
148 GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x0f04c, 0x00000001),
149 GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x0f050, 0x00000001),
150 GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0x0f054, 0x00000001),
151 GATE_CLK(GCC_USB3_SEC_CLKREF_CLK, 0x8c028, 0x00000001),
152 GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x1004c, 0x00000001),
153 GATE_CLK(GCC_USB3_SEC_PHY_PIPE_CLK, 0x10054, 0x00000001),
154 GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x10050, 0x00000001),
155 GATE_CLK(GCC_USB_PHY_CFG_AHB2PHY_CLK, 0x6a004, 0x00000001),
156};
157
Caleb Connollyc94f9e92023-11-07 12:41:03 +0000158static int sdm845_clk_enable(struct clk *clk)
Sumit Gargc9e384e2022-08-04 19:57:14 +0530159{
Caleb Connolly6985e302023-11-07 12:41:02 +0000160 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
161
162 debug("%s: clk %s\n", __func__, sdm845_clks[clk->id].name);
163
164 qcom_gate_clk_en(priv, clk->id);
165
Sumit Gargc9e384e2022-08-04 19:57:14 +0530166 return 0;
167}
Konrad Dybciod9935732023-11-07 12:41:01 +0000168
169static const struct qcom_reset_map sdm845_gcc_resets[] = {
170 [GCC_QUPV3_WRAPPER_0_BCR] = { 0x17000 },
171 [GCC_QUPV3_WRAPPER_1_BCR] = { 0x18000 },
172 [GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
173 [GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
174 [GCC_SDCC2_BCR] = { 0x14000 },
175 [GCC_SDCC4_BCR] = { 0x16000 },
176 [GCC_UFS_CARD_BCR] = { 0x75000 },
177 [GCC_UFS_PHY_BCR] = { 0x77000 },
178 [GCC_USB30_PRIM_BCR] = { 0xf000 },
179 [GCC_USB30_SEC_BCR] = { 0x10000 },
180 [GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
181 [GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
182 [GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
183 [GCC_USB3_PHY_SEC_BCR] = { 0x5000c },
184 [GCC_USB3PHY_PHY_SEC_BCR] = { 0x50010 },
185 [GCC_USB3_DP_PHY_SEC_BCR] = { 0x50014 },
186 [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
187};
188
Caleb Connollyc94f9e92023-11-07 12:41:03 +0000189static struct msm_clk_data sdm845_clk_data = {
Konrad Dybciod9935732023-11-07 12:41:01 +0000190 .resets = sdm845_gcc_resets,
191 .num_resets = ARRAY_SIZE(sdm845_gcc_resets),
Caleb Connolly6985e302023-11-07 12:41:02 +0000192 .clks = sdm845_clks,
193 .num_clks = ARRAY_SIZE(sdm845_clks),
Caleb Connollyc94f9e92023-11-07 12:41:03 +0000194
195 .enable = sdm845_clk_enable,
196 .set_rate = sdm845_clk_set_rate,
Konrad Dybciod9935732023-11-07 12:41:01 +0000197};
198
199static const struct udevice_id gcc_sdm845_of_match[] = {
200 {
201 .compatible = "qcom,gcc-sdm845",
Caleb Connollyc94f9e92023-11-07 12:41:03 +0000202 .data = (ulong)&sdm845_clk_data,
Konrad Dybciod9935732023-11-07 12:41:01 +0000203 },
204 { }
205};
206
207U_BOOT_DRIVER(gcc_sdm845) = {
208 .name = "gcc_sdm845",
209 .id = UCLASS_NOP,
210 .of_match = gcc_sdm845_of_match,
211 .bind = qcom_cc_bind,
212 .flags = DM_FLAG_PRE_RELOC,
213};