blob: 3bafea3a95834b37e6a83e4f103c0f93b831cccb [file] [log] [blame]
Stefan Roese4037ed32007-02-20 10:43:34 +01001/*
2 * cpu/ppc4xx/44x_spd_ddr2.c
3 * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
4 * DDR2 controller (non Denali Core). Those are 440SP/SPe.
5 *
Stefan Roese845c6c92008-01-05 09:12:41 +01006 * (C) Copyright 2007-2008
Stefan Roese4037ed32007-02-20 10:43:34 +01007 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * COPYRIGHT AMCC CORPORATION 2004
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 *
29 */
30
31/* define DEBUG for debugging output (obviously ;-)) */
32#if 0
33#define DEBUG
34#endif
35
36#include <common.h>
Stefan Roeseba58e4c2007-03-01 21:11:36 +010037#include <command.h>
Stefan Roese4037ed32007-02-20 10:43:34 +010038#include <ppc4xx.h>
39#include <i2c.h>
40#include <asm/io.h>
41#include <asm/processor.h>
42#include <asm/mmu.h>
43
44#if defined(CONFIG_SPD_EEPROM) && \
45 (defined(CONFIG_440SP) || defined(CONFIG_440SPE))
46
Stefan Roeseba58e4c2007-03-01 21:11:36 +010047/*-----------------------------------------------------------------------------+
48 * Defines
49 *-----------------------------------------------------------------------------*/
Stefan Roese4037ed32007-02-20 10:43:34 +010050#ifndef TRUE
Wolfgang Denk74357112007-02-27 14:26:04 +010051#define TRUE 1
Stefan Roese4037ed32007-02-20 10:43:34 +010052#endif
53#ifndef FALSE
Wolfgang Denk74357112007-02-27 14:26:04 +010054#define FALSE 0
Stefan Roese4037ed32007-02-20 10:43:34 +010055#endif
56
57#define SDRAM_DDR1 1
58#define SDRAM_DDR2 2
59#define SDRAM_NONE 0
60
Wolfgang Denk1636d1c2007-06-22 23:59:00 +020061#define MAXDIMMS 2
62#define MAXRANKS 4
Stefan Roese4037ed32007-02-20 10:43:34 +010063#define MAXBXCF 4
64#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */
65
66#define ONE_BILLION 1000000000
67
68#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
69
Stefan Roeseba58e4c2007-03-01 21:11:36 +010070#define CMD_NOP (7 << 19)
71#define CMD_PRECHARGE (2 << 19)
72#define CMD_REFRESH (1 << 19)
73#define CMD_EMR (0 << 19)
74#define CMD_READ (5 << 19)
75#define CMD_WRITE (4 << 19)
Stefan Roese4037ed32007-02-20 10:43:34 +010076
Stefan Roeseba58e4c2007-03-01 21:11:36 +010077#define SELECT_MR (0 << 16)
78#define SELECT_EMR (1 << 16)
79#define SELECT_EMR2 (2 << 16)
80#define SELECT_EMR3 (3 << 16)
81
82/* MR */
83#define DLL_RESET 0x00000100
84
85#define WRITE_RECOV_2 (1 << 9)
86#define WRITE_RECOV_3 (2 << 9)
87#define WRITE_RECOV_4 (3 << 9)
88#define WRITE_RECOV_5 (4 << 9)
89#define WRITE_RECOV_6 (5 << 9)
90
91#define BURST_LEN_4 0x00000002
92
93/* EMR */
94#define ODT_0_OHM 0x00000000
95#define ODT_50_OHM 0x00000044
96#define ODT_75_OHM 0x00000004
97#define ODT_150_OHM 0x00000040
98
99#define ODS_FULL 0x00000000
100#define ODS_REDUCED 0x00000002
101
102/* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
103#define ODT_EB0R (0x80000000 >> 8)
104#define ODT_EB0W (0x80000000 >> 7)
105#define CALC_ODT_R(n) (ODT_EB0R << (n << 1))
106#define CALC_ODT_W(n) (ODT_EB0W << (n << 1))
107#define CALC_ODT_RW(n) (CALC_ODT_R(n) | CALC_ODT_W(n))
108
Stefan Roese4037ed32007-02-20 10:43:34 +0100109/* Defines for the Read Cycle Delay test */
Stefan Roese94f54702007-03-31 08:46:08 +0200110#define NUMMEMTESTS 8
111#define NUMMEMWORDS 8
Stefan Roese6ed14ad2007-07-16 09:57:00 +0200112#define NUMLOOPS 64 /* memory test loops */
Stefan Roese4037ed32007-02-20 10:43:34 +0100113
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100114/*
115 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
116 * region. Right now the cache should still be disabled in U-Boot because of the
117 * EMAC driver, that need it's buffer descriptor to be located in non cached
118 * memory.
119 *
120 * If at some time this restriction doesn't apply anymore, just define
Stefan Roeseea2e1422007-10-31 20:57:11 +0100121 * CONFIG_4xx_DCACHE in the board config file and this code should setup
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100122 * everything correctly.
123 */
Stefan Roeseea2e1422007-10-31 20:57:11 +0100124#ifdef CONFIG_4xx_DCACHE
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100125#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
126#else
127#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
128#endif
129
Heiko Schochera5d71e22007-06-25 19:11:37 +0200130/*
131 * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
132 */
133void __spd_ddr_init_hang (void)
134{
135 hang ();
136}
137void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
138
Stefan Roese6ed14ad2007-07-16 09:57:00 +0200139/*
140 * To provide an interface for board specific config values in this common
141 * DDR setup code, we implement he "weak" default functions here. They return
142 * the default value back to the caller.
143 *
144 * Please see include/configs/yucca.h for an example fora board specific
145 * implementation.
146 */
147u32 __ddr_wrdtr(u32 default_val)
148{
149 return default_val;
150}
151u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
152
153u32 __ddr_clktr(u32 default_val)
154{
155 return default_val;
156}
157u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
158
Heiko Schocher566a4942007-06-22 19:11:54 +0200159
Stefan Roese4037ed32007-02-20 10:43:34 +0100160/* Private Structure Definitions */
161
162/* enum only to ease code for cas latency setting */
163typedef enum ddr_cas_id {
164 DDR_CAS_2 = 20,
165 DDR_CAS_2_5 = 25,
166 DDR_CAS_3 = 30,
167 DDR_CAS_4 = 40,
168 DDR_CAS_5 = 50
169} ddr_cas_id_t;
170
171/*-----------------------------------------------------------------------------+
172 * Prototypes
173 *-----------------------------------------------------------------------------*/
174static unsigned long sdram_memsize(void);
Stefan Roese4037ed32007-02-20 10:43:34 +0100175static void get_spd_info(unsigned long *dimm_populated,
176 unsigned char *iic0_dimm_addr,
177 unsigned long num_dimm_banks);
178static void check_mem_type(unsigned long *dimm_populated,
179 unsigned char *iic0_dimm_addr,
180 unsigned long num_dimm_banks);
181static void check_frequency(unsigned long *dimm_populated,
182 unsigned char *iic0_dimm_addr,
183 unsigned long num_dimm_banks);
184static void check_rank_number(unsigned long *dimm_populated,
185 unsigned char *iic0_dimm_addr,
186 unsigned long num_dimm_banks);
187static void check_voltage_type(unsigned long *dimm_populated,
188 unsigned char *iic0_dimm_addr,
189 unsigned long num_dimm_banks);
190static void program_memory_queue(unsigned long *dimm_populated,
191 unsigned char *iic0_dimm_addr,
192 unsigned long num_dimm_banks);
193static void program_codt(unsigned long *dimm_populated,
194 unsigned char *iic0_dimm_addr,
195 unsigned long num_dimm_banks);
196static void program_mode(unsigned long *dimm_populated,
197 unsigned char *iic0_dimm_addr,
198 unsigned long num_dimm_banks,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100199 ddr_cas_id_t *selected_cas,
200 int *write_recovery);
Stefan Roese4037ed32007-02-20 10:43:34 +0100201static void program_tr(unsigned long *dimm_populated,
202 unsigned char *iic0_dimm_addr,
203 unsigned long num_dimm_banks);
204static void program_rtr(unsigned long *dimm_populated,
205 unsigned char *iic0_dimm_addr,
206 unsigned long num_dimm_banks);
207static void program_bxcf(unsigned long *dimm_populated,
208 unsigned char *iic0_dimm_addr,
209 unsigned long num_dimm_banks);
210static void program_copt1(unsigned long *dimm_populated,
211 unsigned char *iic0_dimm_addr,
212 unsigned long num_dimm_banks);
213static void program_initplr(unsigned long *dimm_populated,
214 unsigned char *iic0_dimm_addr,
215 unsigned long num_dimm_banks,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100216 ddr_cas_id_t selected_cas,
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100217 int write_recovery);
Stefan Roese4037ed32007-02-20 10:43:34 +0100218static unsigned long is_ecc_enabled(void);
Stefan Roesedf294492007-03-08 10:06:09 +0100219#ifdef CONFIG_DDR_ECC
Stefan Roese4037ed32007-02-20 10:43:34 +0100220static void program_ecc(unsigned long *dimm_populated,
221 unsigned char *iic0_dimm_addr,
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100222 unsigned long num_dimm_banks,
223 unsigned long tlb_word2_i_value);
Stefan Roese4037ed32007-02-20 10:43:34 +0100224static void program_ecc_addr(unsigned long start_address,
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100225 unsigned long num_bytes,
226 unsigned long tlb_word2_i_value);
Stefan Roesedf294492007-03-08 10:06:09 +0100227#endif
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100228static void program_DQS_calibration(unsigned long *dimm_populated,
229 unsigned char *iic0_dimm_addr,
230 unsigned long num_dimm_banks);
Stefan Roese4037ed32007-02-20 10:43:34 +0100231#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
Wolfgang Denk74357112007-02-27 14:26:04 +0100232static void test(void);
Stefan Roese4037ed32007-02-20 10:43:34 +0100233#else
Wolfgang Denk74357112007-02-27 14:26:04 +0100234static void DQS_calibration_process(void);
Stefan Roese4037ed32007-02-20 10:43:34 +0100235#endif
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100236static void ppc440sp_sdram_register_dump(void);
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100237int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
238void dcbz_area(u32 start_address, u32 num_bytes);
239void dflush(void);
Stefan Roese4037ed32007-02-20 10:43:34 +0100240
241static u32 mfdcr_any(u32 dcr)
242{
243 u32 val;
244
245 switch (dcr) {
246 case SDRAM_R0BAS + 0:
247 val = mfdcr(SDRAM_R0BAS + 0);
248 break;
249 case SDRAM_R0BAS + 1:
250 val = mfdcr(SDRAM_R0BAS + 1);
251 break;
252 case SDRAM_R0BAS + 2:
253 val = mfdcr(SDRAM_R0BAS + 2);
254 break;
255 case SDRAM_R0BAS + 3:
256 val = mfdcr(SDRAM_R0BAS + 3);
257 break;
258 default:
259 printf("DCR %d not defined in case statement!!!\n", dcr);
260 val = 0; /* just to satisfy the compiler */
261 }
262
263 return val;
264}
265
266static void mtdcr_any(u32 dcr, u32 val)
267{
268 switch (dcr) {
269 case SDRAM_R0BAS + 0:
270 mtdcr(SDRAM_R0BAS + 0, val);
271 break;
272 case SDRAM_R0BAS + 1:
273 mtdcr(SDRAM_R0BAS + 1, val);
274 break;
275 case SDRAM_R0BAS + 2:
276 mtdcr(SDRAM_R0BAS + 2, val);
277 break;
278 case SDRAM_R0BAS + 3:
279 mtdcr(SDRAM_R0BAS + 3, val);
280 break;
281 default:
282 printf("DCR %d not defined in case statement!!!\n", dcr);
283 }
284}
285
Stefan Roese4037ed32007-02-20 10:43:34 +0100286static unsigned char spd_read(uchar chip, uint addr)
287{
288 unsigned char data[2];
289
290 if (i2c_probe(chip) == 0)
291 if (i2c_read(chip, addr, 1, data, 1) == 0)
292 return data[0];
293
294 return 0;
295}
296
297/*-----------------------------------------------------------------------------+
298 * sdram_memsize
299 *-----------------------------------------------------------------------------*/
300static unsigned long sdram_memsize(void)
301{
302 unsigned long mem_size;
303 unsigned long mcopt2;
304 unsigned long mcstat;
305 unsigned long mb0cf;
306 unsigned long sdsz;
307 unsigned long i;
308
309 mem_size = 0;
310
311 mfsdram(SDRAM_MCOPT2, mcopt2);
312 mfsdram(SDRAM_MCSTAT, mcstat);
313
314 /* DDR controller must be enabled and not in self-refresh. */
315 /* Otherwise memsize is zero. */
316 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
317 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
318 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
319 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100320 for (i = 0; i < MAXBXCF; i++) {
Stefan Roese4037ed32007-02-20 10:43:34 +0100321 mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
322 /* Banks enabled */
323 if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
324 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
325
326 switch(sdsz) {
327 case SDRAM_RXBAS_SDSZ_8:
328 mem_size+=8;
329 break;
330 case SDRAM_RXBAS_SDSZ_16:
331 mem_size+=16;
332 break;
333 case SDRAM_RXBAS_SDSZ_32:
334 mem_size+=32;
335 break;
336 case SDRAM_RXBAS_SDSZ_64:
337 mem_size+=64;
338 break;
339 case SDRAM_RXBAS_SDSZ_128:
340 mem_size+=128;
341 break;
342 case SDRAM_RXBAS_SDSZ_256:
343 mem_size+=256;
344 break;
345 case SDRAM_RXBAS_SDSZ_512:
346 mem_size+=512;
347 break;
348 case SDRAM_RXBAS_SDSZ_1024:
349 mem_size+=1024;
350 break;
351 case SDRAM_RXBAS_SDSZ_2048:
352 mem_size+=2048;
353 break;
354 case SDRAM_RXBAS_SDSZ_4096:
355 mem_size+=4096;
356 break;
357 default:
358 mem_size=0;
359 break;
360 }
361 }
362 }
363 }
364
365 mem_size *= 1024 * 1024;
366 return(mem_size);
367}
368
369/*-----------------------------------------------------------------------------+
370 * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller.
371 * Note: This routine runs from flash with a stack set up in the chip's
372 * sram space. It is important that the routine does not require .sbss, .bss or
373 * .data sections. It also cannot call routines that require these sections.
374 *-----------------------------------------------------------------------------*/
375/*-----------------------------------------------------------------------------
Wolfgang Denk74357112007-02-27 14:26:04 +0100376 * Function: initdram
Stefan Roese4037ed32007-02-20 10:43:34 +0100377 * Description: Configures SDRAM memory banks for DDR operation.
Wolfgang Denk74357112007-02-27 14:26:04 +0100378 * Auto Memory Configuration option reads the DDR SDRAM EEPROMs
379 * via the IIC bus and then configures the DDR SDRAM memory
380 * banks appropriately. If Auto Memory Configuration is
381 * not used, it is assumed that no DIMM is plugged
Stefan Roese4037ed32007-02-20 10:43:34 +0100382 *-----------------------------------------------------------------------------*/
383long int initdram(int board_type)
384{
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100385 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
Stefan Roese4037ed32007-02-20 10:43:34 +0100386 unsigned char spd0[MAX_SPD_BYTES];
387 unsigned char spd1[MAX_SPD_BYTES];
388 unsigned char *dimm_spd[MAXDIMMS];
389 unsigned long dimm_populated[MAXDIMMS];
Stefan Roese9adfc9f2008-01-15 10:11:02 +0100390 unsigned long num_dimm_banks; /* on board dimm banks */
Stefan Roese4037ed32007-02-20 10:43:34 +0100391 unsigned long val;
Stefan Roese9adfc9f2008-01-15 10:11:02 +0100392 ddr_cas_id_t selected_cas = DDR_CAS_5; /* preset to silence compiler */
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100393 int write_recovery;
Stefan Roese4037ed32007-02-20 10:43:34 +0100394 unsigned long dram_size = 0;
395
396 num_dimm_banks = sizeof(iic0_dimm_addr);
397
398 /*------------------------------------------------------------------
399 * Set up an array of SPD matrixes.
400 *-----------------------------------------------------------------*/
401 dimm_spd[0] = spd0;
402 dimm_spd[1] = spd1;
403
404 /*------------------------------------------------------------------
Stefan Roese4037ed32007-02-20 10:43:34 +0100405 * Reset the DDR-SDRAM controller.
406 *-----------------------------------------------------------------*/
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100407 mtsdr(SDR0_SRST, (0x80000000 >> 10));
Stefan Roese4037ed32007-02-20 10:43:34 +0100408 mtsdr(SDR0_SRST, 0x00000000);
409
410 /*
411 * Make sure I2C controller is initialized
412 * before continuing.
413 */
414
415 /* switch to correct I2C bus */
416 I2C_SET_BUS(CFG_SPD_BUS_NUM);
417 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
418
419 /*------------------------------------------------------------------
420 * Clear out the serial presence detect buffers.
421 * Perform IIC reads from the dimm. Fill in the spds.
422 * Check to see if the dimm slots are populated
423 *-----------------------------------------------------------------*/
424 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
425
426 /*------------------------------------------------------------------
427 * Check the memory type for the dimms plugged.
428 *-----------------------------------------------------------------*/
429 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
430
431 /*------------------------------------------------------------------
432 * Check the frequency supported for the dimms plugged.
433 *-----------------------------------------------------------------*/
434 check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
435
436 /*------------------------------------------------------------------
437 * Check the total rank number.
438 *-----------------------------------------------------------------*/
439 check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
440
441 /*------------------------------------------------------------------
442 * Check the voltage type for the dimms plugged.
443 *-----------------------------------------------------------------*/
444 check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
445
446 /*------------------------------------------------------------------
447 * Program SDRAM controller options 2 register
448 * Except Enabling of the memory controller.
449 *-----------------------------------------------------------------*/
450 mfsdram(SDRAM_MCOPT2, val);
451 mtsdram(SDRAM_MCOPT2,
452 (val &
453 ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
454 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
455 SDRAM_MCOPT2_ISIE_MASK))
456 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
457 SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
458 SDRAM_MCOPT2_ISIE_ENABLE));
459
460 /*------------------------------------------------------------------
461 * Program SDRAM controller options 1 register
462 * Note: Does not enable the memory controller.
463 *-----------------------------------------------------------------*/
464 program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
465
466 /*------------------------------------------------------------------
467 * Set the SDRAM Controller On Die Termination Register
468 *-----------------------------------------------------------------*/
469 program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
470
471 /*------------------------------------------------------------------
472 * Program SDRAM refresh register.
473 *-----------------------------------------------------------------*/
474 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
475
476 /*------------------------------------------------------------------
477 * Program SDRAM mode register.
478 *-----------------------------------------------------------------*/
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100479 program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
480 &selected_cas, &write_recovery);
Stefan Roese4037ed32007-02-20 10:43:34 +0100481
482 /*------------------------------------------------------------------
483 * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
484 *-----------------------------------------------------------------*/
485 mfsdram(SDRAM_WRDTR, val);
486 mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
Stefan Roese6ed14ad2007-07-16 09:57:00 +0200487 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
Stefan Roese4037ed32007-02-20 10:43:34 +0100488
489 /*------------------------------------------------------------------
490 * Set the SDRAM Clock Timing Register
491 *-----------------------------------------------------------------*/
492 mfsdram(SDRAM_CLKTR, val);
Stefan Roese6ed14ad2007-07-16 09:57:00 +0200493 mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
494 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
Stefan Roese4037ed32007-02-20 10:43:34 +0100495
496 /*------------------------------------------------------------------
497 * Program the BxCF registers.
498 *-----------------------------------------------------------------*/
499 program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
500
501 /*------------------------------------------------------------------
502 * Program SDRAM timing registers.
503 *-----------------------------------------------------------------*/
504 program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
505
506 /*------------------------------------------------------------------
507 * Set the Extended Mode register
508 *-----------------------------------------------------------------*/
509 mfsdram(SDRAM_MEMODE, val);
510 mtsdram(SDRAM_MEMODE,
511 (val & ~(SDRAM_MEMODE_DIC_MASK | SDRAM_MEMODE_DLL_MASK |
512 SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
513 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
Stefan Roesedf294492007-03-08 10:06:09 +0100514 | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
Stefan Roese4037ed32007-02-20 10:43:34 +0100515
516 /*------------------------------------------------------------------
517 * Program Initialization preload registers.
518 *-----------------------------------------------------------------*/
519 program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100520 selected_cas, write_recovery);
Stefan Roese4037ed32007-02-20 10:43:34 +0100521
522 /*------------------------------------------------------------------
523 * Delay to ensure 200usec have elapsed since reset.
524 *-----------------------------------------------------------------*/
525 udelay(400);
526
527 /*------------------------------------------------------------------
528 * Set the memory queue core base addr.
529 *-----------------------------------------------------------------*/
530 program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
531
532 /*------------------------------------------------------------------
533 * Program SDRAM controller options 2 register
534 * Enable the memory controller.
535 *-----------------------------------------------------------------*/
536 mfsdram(SDRAM_MCOPT2, val);
537 mtsdram(SDRAM_MCOPT2,
538 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
539 SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
540 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
541
542 /*------------------------------------------------------------------
543 * Wait for SDRAM_CFG0_DC_EN to complete.
544 *-----------------------------------------------------------------*/
545 do {
546 mfsdram(SDRAM_MCSTAT, val);
547 } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
548
549 /* get installed memory size */
550 dram_size = sdram_memsize();
551
552 /* and program tlb entries for this size (dynamic) */
Stefan Roese6ed14ad2007-07-16 09:57:00 +0200553
554 /*
555 * Program TLB entries with caches enabled, for best performace
556 * while auto-calibrating and ECC generation
557 */
558 program_tlb(0, 0, dram_size, 0);
Stefan Roese4037ed32007-02-20 10:43:34 +0100559
560 /*------------------------------------------------------------------
561 * DQS calibration.
562 *-----------------------------------------------------------------*/
563 program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
564
Stefan Roesedf294492007-03-08 10:06:09 +0100565#ifdef CONFIG_DDR_ECC
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100566 /*------------------------------------------------------------------
567 * If ecc is enabled, initialize the parity bits.
568 *-----------------------------------------------------------------*/
Stefan Roese6ed14ad2007-07-16 09:57:00 +0200569 program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
Stefan Roesedf294492007-03-08 10:06:09 +0100570#endif
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100571
Stefan Roese6ed14ad2007-07-16 09:57:00 +0200572 /*
573 * Now after initialization (auto-calibration and ECC generation)
574 * remove the TLB entries with caches enabled and program again with
575 * desired cache functionality
576 */
577 remove_tlb(0, dram_size);
578 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
579
Stefan Roese4037ed32007-02-20 10:43:34 +0100580 ppc440sp_sdram_register_dump();
Stefan Roese4037ed32007-02-20 10:43:34 +0100581
582 return dram_size;
583}
584
585static void get_spd_info(unsigned long *dimm_populated,
586 unsigned char *iic0_dimm_addr,
587 unsigned long num_dimm_banks)
588{
589 unsigned long dimm_num;
590 unsigned long dimm_found;
591 unsigned char num_of_bytes;
592 unsigned char total_size;
593
594 dimm_found = FALSE;
595 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
596 num_of_bytes = 0;
597 total_size = 0;
598
599 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
600 debug("\nspd_read(0x%x) returned %d\n",
601 iic0_dimm_addr[dimm_num], num_of_bytes);
602 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
603 debug("spd_read(0x%x) returned %d\n",
604 iic0_dimm_addr[dimm_num], total_size);
605
606 if ((num_of_bytes != 0) && (total_size != 0)) {
607 dimm_populated[dimm_num] = TRUE;
608 dimm_found = TRUE;
609 debug("DIMM slot %lu: populated\n", dimm_num);
610 } else {
611 dimm_populated[dimm_num] = FALSE;
612 debug("DIMM slot %lu: Not populated\n", dimm_num);
613 }
614 }
615
616 if (dimm_found == FALSE) {
617 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +0200618 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100619 }
620}
621
Stefan Roese4037ed32007-02-20 10:43:34 +0100622void board_add_ram_info(int use_default)
623{
Stefan Roese087dfdb2007-10-21 08:12:41 +0200624 PPC4xx_SYS_INFO board_cfg;
Stefan Roese94f54702007-03-31 08:46:08 +0200625 u32 val;
626
Wolfgang Denk74357112007-02-27 14:26:04 +0100627 if (is_ecc_enabled())
Stefan Roesecabee752007-03-31 13:15:06 +0200628 puts(" (ECC");
Wolfgang Denk74357112007-02-27 14:26:04 +0100629 else
Stefan Roesecabee752007-03-31 13:15:06 +0200630 puts(" (ECC not");
631
632 get_sys_info(&board_cfg);
633
634 mfsdr(SDR0_DDR0, val);
635 val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
636 printf(" enabled, %d MHz", (val * 2) / 1000000);
Stefan Roese94f54702007-03-31 08:46:08 +0200637
638 mfsdram(SDRAM_MMODE, val);
639 val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
Stefan Roesecabee752007-03-31 13:15:06 +0200640 printf(", CL%d)", val);
Stefan Roese4037ed32007-02-20 10:43:34 +0100641}
Stefan Roese4037ed32007-02-20 10:43:34 +0100642
643/*------------------------------------------------------------------
644 * For the memory DIMMs installed, this routine verifies that they
645 * really are DDR specific DIMMs.
646 *-----------------------------------------------------------------*/
647static void check_mem_type(unsigned long *dimm_populated,
648 unsigned char *iic0_dimm_addr,
649 unsigned long num_dimm_banks)
650{
651 unsigned long dimm_num;
652 unsigned long dimm_type;
653
654 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
655 if (dimm_populated[dimm_num] == TRUE) {
656 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
657 switch (dimm_type) {
658 case 1:
659 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
660 "slot %d.\n", (unsigned int)dimm_num);
661 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
662 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +0200663 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100664 break;
665 case 2:
666 printf("ERROR: EDO DIMM detected in slot %d.\n",
667 (unsigned int)dimm_num);
668 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
669 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +0200670 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100671 break;
672 case 3:
673 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
674 (unsigned int)dimm_num);
675 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
676 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +0200677 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100678 break;
679 case 4:
680 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
681 (unsigned int)dimm_num);
682 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
683 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +0200684 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100685 break;
686 case 5:
687 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
688 (unsigned int)dimm_num);
689 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
690 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +0200691 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100692 break;
693 case 6:
694 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
695 (unsigned int)dimm_num);
696 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
697 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +0200698 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100699 break;
700 case 7:
701 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
702 dimm_populated[dimm_num] = SDRAM_DDR1;
703 break;
704 case 8:
705 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
706 dimm_populated[dimm_num] = SDRAM_DDR2;
707 break;
708 default:
709 printf("ERROR: Unknown DIMM detected in slot %d.\n",
710 (unsigned int)dimm_num);
711 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
712 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +0200713 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100714 break;
715 }
716 }
717 }
718 for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
719 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
720 && (dimm_populated[dimm_num] != SDRAM_NONE)
721 && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
722 printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +0200723 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100724 }
725 }
726}
727
728/*------------------------------------------------------------------
729 * For the memory DIMMs installed, this routine verifies that
730 * frequency previously calculated is supported.
731 *-----------------------------------------------------------------*/
732static void check_frequency(unsigned long *dimm_populated,
733 unsigned char *iic0_dimm_addr,
734 unsigned long num_dimm_banks)
735{
736 unsigned long dimm_num;
737 unsigned long tcyc_reg;
738 unsigned long cycle_time;
739 unsigned long calc_cycle_time;
740 unsigned long sdram_freq;
741 unsigned long sdr_ddrpll;
Stefan Roese087dfdb2007-10-21 08:12:41 +0200742 PPC4xx_SYS_INFO board_cfg;
Stefan Roese4037ed32007-02-20 10:43:34 +0100743
744 /*------------------------------------------------------------------
745 * Get the board configuration info.
746 *-----------------------------------------------------------------*/
747 get_sys_info(&board_cfg);
748
Stefan Roesedf294492007-03-08 10:06:09 +0100749 mfsdr(SDR0_DDR0, sdr_ddrpll);
Stefan Roese4037ed32007-02-20 10:43:34 +0100750 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
751
752 /*
753 * calc_cycle_time is calculated from DDR frequency set by board/chip
754 * and is expressed in multiple of 10 picoseconds
755 * to match the way DIMM cycle time is calculated below.
756 */
757 calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
758
759 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
760 if (dimm_populated[dimm_num] != SDRAM_NONE) {
761 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
762 /*
763 * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
764 * the higher order nibble (bits 4-7) designates the cycle time
765 * to a granularity of 1ns;
766 * the value presented by the lower order nibble (bits 0-3)
767 * has a granularity of .1ns and is added to the value designated
768 * by the higher nibble. In addition, four lines of the lower order
769 * nibble are assigned to support +.25,+.33, +.66 and +.75.
770 */
771 /* Convert from hex to decimal */
772 if ((tcyc_reg & 0x0F) == 0x0D)
773 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
774 else if ((tcyc_reg & 0x0F) == 0x0C)
775 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
776 else if ((tcyc_reg & 0x0F) == 0x0B)
777 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
778 else if ((tcyc_reg & 0x0F) == 0x0A)
779 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
780 else
781 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
782 ((tcyc_reg & 0x0F)*10);
Stefan Roese94f54702007-03-31 08:46:08 +0200783 debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
Stefan Roese4037ed32007-02-20 10:43:34 +0100784
785 if (cycle_time > (calc_cycle_time + 10)) {
786 /*
787 * the provided sdram cycle_time is too small
788 * for the available DIMM cycle_time.
789 * The additionnal 100ps is here to accept a small incertainty.
790 */
791 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
792 "slot %d \n while calculated cycle time is %d ps.\n",
793 (unsigned int)(cycle_time*10),
794 (unsigned int)dimm_num,
795 (unsigned int)(calc_cycle_time*10));
796 printf("Replace the DIMM, or change DDR frequency via "
797 "strapping bits.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +0200798 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100799 }
800 }
801 }
802}
803
804/*------------------------------------------------------------------
805 * For the memory DIMMs installed, this routine verifies two
806 * ranks/banks maximum are availables.
807 *-----------------------------------------------------------------*/
808static void check_rank_number(unsigned long *dimm_populated,
809 unsigned char *iic0_dimm_addr,
810 unsigned long num_dimm_banks)
811{
812 unsigned long dimm_num;
813 unsigned long dimm_rank;
814 unsigned long total_rank = 0;
815
816 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
817 if (dimm_populated[dimm_num] != SDRAM_NONE) {
818 dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
819 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
820 dimm_rank = (dimm_rank & 0x0F) +1;
821 else
822 dimm_rank = dimm_rank & 0x0F;
823
824
825 if (dimm_rank > MAXRANKS) {
826 printf("ERROR: DRAM DIMM detected with %d ranks in "
827 "slot %d is not supported.\n", dimm_rank, dimm_num);
828 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
829 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +0200830 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100831 } else
832 total_rank += dimm_rank;
833 }
834 if (total_rank > MAXRANKS) {
835 printf("ERROR: DRAM DIMM detected with a total of %d ranks "
836 "for all slots.\n", (unsigned int)total_rank);
837 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
838 printf("Remove one of the DIMM modules.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +0200839 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100840 }
841 }
842}
843
844/*------------------------------------------------------------------
845 * only support 2.5V modules.
846 * This routine verifies this.
847 *-----------------------------------------------------------------*/
848static void check_voltage_type(unsigned long *dimm_populated,
849 unsigned char *iic0_dimm_addr,
850 unsigned long num_dimm_banks)
851{
852 unsigned long dimm_num;
853 unsigned long voltage_type;
854
855 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
856 if (dimm_populated[dimm_num] != SDRAM_NONE) {
857 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
858 switch (voltage_type) {
859 case 0x00:
860 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
861 printf("This DIMM is 5.0 Volt/TTL.\n");
862 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
863 (unsigned int)dimm_num);
Heiko Schochera5d71e22007-06-25 19:11:37 +0200864 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100865 break;
866 case 0x01:
867 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
868 printf("This DIMM is LVTTL.\n");
869 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
870 (unsigned int)dimm_num);
Heiko Schochera5d71e22007-06-25 19:11:37 +0200871 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100872 break;
873 case 0x02:
874 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
875 printf("This DIMM is 1.5 Volt.\n");
876 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
877 (unsigned int)dimm_num);
Heiko Schochera5d71e22007-06-25 19:11:37 +0200878 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100879 break;
880 case 0x03:
881 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
882 printf("This DIMM is 3.3 Volt/TTL.\n");
883 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
884 (unsigned int)dimm_num);
Heiko Schochera5d71e22007-06-25 19:11:37 +0200885 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100886 break;
887 case 0x04:
888 /* 2.5 Voltage only for DDR1 */
889 break;
890 case 0x05:
891 /* 1.8 Voltage only for DDR2 */
892 break;
893 default:
894 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
895 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
896 (unsigned int)dimm_num);
Heiko Schochera5d71e22007-06-25 19:11:37 +0200897 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +0100898 break;
899 }
900 }
901 }
902}
903
904/*-----------------------------------------------------------------------------+
905 * program_copt1.
906 *-----------------------------------------------------------------------------*/
907static void program_copt1(unsigned long *dimm_populated,
908 unsigned char *iic0_dimm_addr,
909 unsigned long num_dimm_banks)
910{
911 unsigned long dimm_num;
912 unsigned long mcopt1;
913 unsigned long ecc_enabled;
914 unsigned long ecc = 0;
915 unsigned long data_width = 0;
916 unsigned long dimm_32bit;
917 unsigned long dimm_64bit;
918 unsigned long registered = 0;
919 unsigned long attribute = 0;
920 unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
921 unsigned long bankcount;
922 unsigned long ddrtype;
923 unsigned long val;
924
Stefan Roesedf294492007-03-08 10:06:09 +0100925#ifdef CONFIG_DDR_ECC
Stefan Roese4037ed32007-02-20 10:43:34 +0100926 ecc_enabled = TRUE;
Stefan Roesedf294492007-03-08 10:06:09 +0100927#else
928 ecc_enabled = FALSE;
929#endif
Stefan Roese4037ed32007-02-20 10:43:34 +0100930 dimm_32bit = FALSE;
931 dimm_64bit = FALSE;
932 buf0 = FALSE;
933 buf1 = FALSE;
934
935 /*------------------------------------------------------------------
936 * Set memory controller options reg 1, SDRAM_MCOPT1.
937 *-----------------------------------------------------------------*/
938 mfsdram(SDRAM_MCOPT1, val);
939 mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
940 SDRAM_MCOPT1_PMU_MASK | SDRAM_MCOPT1_DMWD_MASK |
941 SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
942 SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
943 SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
944 SDRAM_MCOPT1_DREF_MASK);
945
946 mcopt1 |= SDRAM_MCOPT1_QDEP;
947 mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
948 mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
949 mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
950 mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
951 mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
952
953 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
954 if (dimm_populated[dimm_num] != SDRAM_NONE) {
955 /* test ecc support */
956 ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
957 if (ecc != 0x02) /* ecc not supported */
958 ecc_enabled = FALSE;
959
960 /* test bank count */
961 bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
962 if (bankcount == 0x04) /* bank count = 4 */
963 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
964 else /* bank count = 8 */
965 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
966
967 /* test DDR type */
968 ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
969 /* test for buffered/unbuffered, registered, differential clocks */
970 registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
971 attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
972
973 /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
974 if (dimm_num == 0) {
975 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
976 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
977 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
978 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
979 if (registered == 1) { /* DDR2 always buffered */
980 /* TODO: what about above comments ? */
981 mcopt1 |= SDRAM_MCOPT1_RDEN;
982 buf0 = TRUE;
983 } else {
984 /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
985 if ((attribute & 0x02) == 0x00) {
986 /* buffered not supported */
987 buf0 = FALSE;
988 } else {
989 mcopt1 |= SDRAM_MCOPT1_RDEN;
990 buf0 = TRUE;
991 }
992 }
993 }
994 else if (dimm_num == 1) {
995 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
996 mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
997 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
998 mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
999 if (registered == 1) {
1000 /* DDR2 always buffered */
1001 mcopt1 |= SDRAM_MCOPT1_RDEN;
1002 buf1 = TRUE;
1003 } else {
1004 if ((attribute & 0x02) == 0x00) {
1005 /* buffered not supported */
1006 buf1 = FALSE;
1007 } else {
1008 mcopt1 |= SDRAM_MCOPT1_RDEN;
1009 buf1 = TRUE;
1010 }
1011 }
1012 }
1013
1014 /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1015 data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1016 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1017
1018 switch (data_width) {
1019 case 72:
1020 case 64:
1021 dimm_64bit = TRUE;
1022 break;
1023 case 40:
1024 case 32:
1025 dimm_32bit = TRUE;
1026 break;
1027 default:
1028 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
1029 data_width);
1030 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1031 break;
1032 }
1033 }
1034 }
1035
1036 /* verify matching properties */
1037 if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1038 if (buf0 != buf1) {
1039 printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +02001040 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01001041 }
1042 }
1043
1044 if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1045 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +02001046 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01001047 }
1048 else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1049 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1050 } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1051 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1052 } else {
1053 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +02001054 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01001055 }
1056
1057 if (ecc_enabled == TRUE)
1058 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1059 else
1060 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1061
1062 mtsdram(SDRAM_MCOPT1, mcopt1);
1063}
1064
1065/*-----------------------------------------------------------------------------+
1066 * program_codt.
1067 *-----------------------------------------------------------------------------*/
1068static void program_codt(unsigned long *dimm_populated,
1069 unsigned char *iic0_dimm_addr,
1070 unsigned long num_dimm_banks)
1071{
1072 unsigned long codt;
1073 unsigned long modt0 = 0;
1074 unsigned long modt1 = 0;
1075 unsigned long modt2 = 0;
1076 unsigned long modt3 = 0;
1077 unsigned char dimm_num;
1078 unsigned char dimm_rank;
1079 unsigned char total_rank = 0;
1080 unsigned char total_dimm = 0;
1081 unsigned char dimm_type = 0;
1082 unsigned char firstSlot = 0;
1083
1084 /*------------------------------------------------------------------
1085 * Set the SDRAM Controller On Die Termination Register
1086 *-----------------------------------------------------------------*/
1087 mfsdram(SDRAM_CODT, codt);
1088 codt |= (SDRAM_CODT_IO_NMODE
1089 & (~SDRAM_CODT_DQS_SINGLE_END
1090 & ~SDRAM_CODT_CKSE_SINGLE_END
1091 & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1092 & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1093
1094 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1095 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1096 dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1097 if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1098 dimm_rank = (dimm_rank & 0x0F) + 1;
1099 dimm_type = SDRAM_DDR2;
1100 } else {
1101 dimm_rank = dimm_rank & 0x0F;
1102 dimm_type = SDRAM_DDR1;
1103 }
1104
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001105 total_rank += dimm_rank;
1106 total_dimm++;
Stefan Roese4037ed32007-02-20 10:43:34 +01001107 if ((dimm_num == 0) && (total_dimm == 1))
1108 firstSlot = TRUE;
1109 else
1110 firstSlot = FALSE;
1111 }
1112 }
1113 if (dimm_type == SDRAM_DDR2) {
1114 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1115 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1116 if (total_rank == 1) {
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001117 codt |= CALC_ODT_R(0);
1118 modt0 = CALC_ODT_W(0);
Stefan Roese4037ed32007-02-20 10:43:34 +01001119 modt1 = 0x00000000;
1120 modt2 = 0x00000000;
1121 modt3 = 0x00000000;
1122 }
1123 if (total_rank == 2) {
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001124 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1125 modt0 = CALC_ODT_W(0);
1126 modt1 = CALC_ODT_W(0);
Stefan Roese4037ed32007-02-20 10:43:34 +01001127 modt2 = 0x00000000;
1128 modt3 = 0x00000000;
1129 }
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001130 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
Stefan Roese4037ed32007-02-20 10:43:34 +01001131 if (total_rank == 1) {
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001132 codt |= CALC_ODT_R(2);
1133 modt0 = 0x00000000;
Stefan Roese4037ed32007-02-20 10:43:34 +01001134 modt1 = 0x00000000;
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001135 modt2 = CALC_ODT_W(2);
Stefan Roese4037ed32007-02-20 10:43:34 +01001136 modt3 = 0x00000000;
1137 }
1138 if (total_rank == 2) {
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001139 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1140 modt0 = 0x00000000;
1141 modt1 = 0x00000000;
1142 modt2 = CALC_ODT_W(2);
1143 modt3 = CALC_ODT_W(2);
Stefan Roese4037ed32007-02-20 10:43:34 +01001144 }
1145 }
1146 if (total_dimm == 2) {
1147 if (total_rank == 2) {
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001148 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1149 modt0 = CALC_ODT_RW(2);
Stefan Roese4037ed32007-02-20 10:43:34 +01001150 modt1 = 0x00000000;
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001151 modt2 = CALC_ODT_RW(0);
Stefan Roese4037ed32007-02-20 10:43:34 +01001152 modt3 = 0x00000000;
1153 }
1154 if (total_rank == 4) {
Stefan Roese7187db72007-06-01 13:45:00 +02001155 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1156 CALC_ODT_R(2) | CALC_ODT_R(3);
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001157 modt0 = CALC_ODT_RW(2);
1158 modt1 = 0x00000000;
1159 modt2 = CALC_ODT_RW(0);
1160 modt3 = 0x00000000;
Stefan Roese4037ed32007-02-20 10:43:34 +01001161 }
1162 }
Wolfgang Denk647d3c32007-03-04 01:36:05 +01001163 } else {
Stefan Roese4037ed32007-02-20 10:43:34 +01001164 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1165 modt0 = 0x00000000;
1166 modt1 = 0x00000000;
1167 modt2 = 0x00000000;
1168 modt3 = 0x00000000;
1169
1170 if (total_dimm == 1) {
1171 if (total_rank == 1)
1172 codt |= 0x00800000;
1173 if (total_rank == 2)
1174 codt |= 0x02800000;
1175 }
1176 if (total_dimm == 2) {
1177 if (total_rank == 2)
1178 codt |= 0x08800000;
1179 if (total_rank == 4)
1180 codt |= 0x2a800000;
1181 }
1182 }
1183
1184 debug("nb of dimm %d\n", total_dimm);
1185 debug("nb of rank %d\n", total_rank);
1186 if (total_dimm == 1)
1187 debug("dimm in slot %d\n", firstSlot);
1188
1189 mtsdram(SDRAM_CODT, codt);
1190 mtsdram(SDRAM_MODT0, modt0);
1191 mtsdram(SDRAM_MODT1, modt1);
1192 mtsdram(SDRAM_MODT2, modt2);
1193 mtsdram(SDRAM_MODT3, modt3);
1194}
1195
1196/*-----------------------------------------------------------------------------+
1197 * program_initplr.
1198 *-----------------------------------------------------------------------------*/
1199static void program_initplr(unsigned long *dimm_populated,
1200 unsigned char *iic0_dimm_addr,
1201 unsigned long num_dimm_banks,
Wolfgang Denkad5bb452007-03-06 18:08:43 +01001202 ddr_cas_id_t selected_cas,
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001203 int write_recovery)
Stefan Roese4037ed32007-02-20 10:43:34 +01001204{
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001205 u32 cas = 0;
1206 u32 odt = 0;
1207 u32 ods = 0;
1208 u32 mr;
1209 u32 wr;
1210 u32 emr;
1211 u32 emr2;
1212 u32 emr3;
1213 int dimm_num;
1214 int total_dimm = 0;
Stefan Roese4037ed32007-02-20 10:43:34 +01001215
1216 /******************************************************
1217 ** Assumption: if more than one DIMM, all DIMMs are the same
Wolfgang Denk74357112007-02-27 14:26:04 +01001218 ** as already checked in check_memory_type
Stefan Roese4037ed32007-02-20 10:43:34 +01001219 ******************************************************/
1220
1221 if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1222 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1223 mtsdram(SDRAM_INITPLR1, 0x81900400);
1224 mtsdram(SDRAM_INITPLR2, 0x81810000);
1225 mtsdram(SDRAM_INITPLR3, 0xff800162);
1226 mtsdram(SDRAM_INITPLR4, 0x81900400);
1227 mtsdram(SDRAM_INITPLR5, 0x86080000);
1228 mtsdram(SDRAM_INITPLR6, 0x86080000);
1229 mtsdram(SDRAM_INITPLR7, 0x81000062);
1230 } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1231 switch (selected_cas) {
Stefan Roese4037ed32007-02-20 10:43:34 +01001232 case DDR_CAS_3:
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001233 cas = 3 << 4;
Stefan Roese4037ed32007-02-20 10:43:34 +01001234 break;
1235 case DDR_CAS_4:
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001236 cas = 4 << 4;
Stefan Roese4037ed32007-02-20 10:43:34 +01001237 break;
1238 case DDR_CAS_5:
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001239 cas = 5 << 4;
Stefan Roese4037ed32007-02-20 10:43:34 +01001240 break;
1241 default:
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001242 printf("ERROR: ucode error on selected_cas value %d", selected_cas);
Heiko Schochera5d71e22007-06-25 19:11:37 +02001243 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01001244 break;
1245 }
1246
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001247#if 0
1248 /*
1249 * ToDo - Still a problem with the write recovery:
1250 * On the Corsair CM2X512-5400C4 module, setting write recovery
1251 * in the INITPLR reg to the value calculated in program_mode()
1252 * results in not correctly working DDR2 memory (crash after
1253 * relocation).
1254 *
1255 * So for now, set the write recovery to 3. This seems to work
1256 * on the Corair module too.
1257 *
1258 * 2007-03-01, sr
1259 */
1260 switch (write_recovery) {
1261 case 3:
1262 wr = WRITE_RECOV_3;
1263 break;
1264 case 4:
1265 wr = WRITE_RECOV_4;
1266 break;
1267 case 5:
1268 wr = WRITE_RECOV_5;
1269 break;
1270 case 6:
1271 wr = WRITE_RECOV_6;
1272 break;
1273 default:
1274 printf("ERROR: write recovery not support (%d)", write_recovery);
Heiko Schochera5d71e22007-06-25 19:11:37 +02001275 spd_ddr_init_hang ();
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001276 break;
1277 }
1278#else
1279 wr = WRITE_RECOV_3; /* test-only, see description above */
1280#endif
1281
1282 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1283 if (dimm_populated[dimm_num] != SDRAM_NONE)
1284 total_dimm++;
1285 if (total_dimm == 1) {
1286 odt = ODT_150_OHM;
1287 ods = ODS_FULL;
1288 } else if (total_dimm == 2) {
1289 odt = ODT_75_OHM;
1290 ods = ODS_REDUCED;
1291 } else {
1292 printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
Heiko Schochera5d71e22007-06-25 19:11:37 +02001293 spd_ddr_init_hang ();
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001294 }
1295
1296 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1297 emr = CMD_EMR | SELECT_EMR | odt | ods;
1298 emr2 = CMD_EMR | SELECT_EMR2;
1299 emr3 = CMD_EMR | SELECT_EMR3;
1300 mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */
1301 udelay(1000);
1302 mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1303 mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */
1304 mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */
1305 mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */
1306 mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */
1307 udelay(1000);
1308 mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */
1309 mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1310 mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1311 mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1312 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */
1313 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */
1314 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */
1315 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */
Stefan Roese4037ed32007-02-20 10:43:34 +01001316 } else {
1317 printf("ERROR: ucode error as unknown DDR type in program_initplr");
Heiko Schochera5d71e22007-06-25 19:11:37 +02001318 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01001319 }
1320}
1321
1322/*------------------------------------------------------------------
1323 * This routine programs the SDRAM_MMODE register.
1324 * the selected_cas is an output parameter, that will be passed
1325 * by caller to call the above program_initplr( )
1326 *-----------------------------------------------------------------*/
1327static void program_mode(unsigned long *dimm_populated,
1328 unsigned char *iic0_dimm_addr,
1329 unsigned long num_dimm_banks,
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001330 ddr_cas_id_t *selected_cas,
1331 int *write_recovery)
Stefan Roese4037ed32007-02-20 10:43:34 +01001332{
1333 unsigned long dimm_num;
1334 unsigned long sdram_ddr1;
1335 unsigned long t_wr_ns;
1336 unsigned long t_wr_clk;
1337 unsigned long cas_bit;
1338 unsigned long cas_index;
1339 unsigned long sdram_freq;
1340 unsigned long ddr_check;
1341 unsigned long mmode;
1342 unsigned long tcyc_reg;
1343 unsigned long cycle_2_0_clk;
1344 unsigned long cycle_2_5_clk;
1345 unsigned long cycle_3_0_clk;
1346 unsigned long cycle_4_0_clk;
1347 unsigned long cycle_5_0_clk;
1348 unsigned long max_2_0_tcyc_ns_x_100;
1349 unsigned long max_2_5_tcyc_ns_x_100;
1350 unsigned long max_3_0_tcyc_ns_x_100;
1351 unsigned long max_4_0_tcyc_ns_x_100;
1352 unsigned long max_5_0_tcyc_ns_x_100;
1353 unsigned long cycle_time_ns_x_100[3];
Stefan Roese087dfdb2007-10-21 08:12:41 +02001354 PPC4xx_SYS_INFO board_cfg;
Stefan Roese4037ed32007-02-20 10:43:34 +01001355 unsigned char cas_2_0_available;
1356 unsigned char cas_2_5_available;
1357 unsigned char cas_3_0_available;
1358 unsigned char cas_4_0_available;
1359 unsigned char cas_5_0_available;
1360 unsigned long sdr_ddrpll;
1361
1362 /*------------------------------------------------------------------
1363 * Get the board configuration info.
1364 *-----------------------------------------------------------------*/
1365 get_sys_info(&board_cfg);
1366
Stefan Roesedf294492007-03-08 10:06:09 +01001367 mfsdr(SDR0_DDR0, sdr_ddrpll);
Stefan Roese4037ed32007-02-20 10:43:34 +01001368 sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
Stefan Roesecabee752007-03-31 13:15:06 +02001369 debug("sdram_freq=%d\n", sdram_freq);
Stefan Roese4037ed32007-02-20 10:43:34 +01001370
1371 /*------------------------------------------------------------------
1372 * Handle the timing. We need to find the worst case timing of all
1373 * the dimm modules installed.
1374 *-----------------------------------------------------------------*/
1375 t_wr_ns = 0;
1376 cas_2_0_available = TRUE;
1377 cas_2_5_available = TRUE;
1378 cas_3_0_available = TRUE;
1379 cas_4_0_available = TRUE;
1380 cas_5_0_available = TRUE;
1381 max_2_0_tcyc_ns_x_100 = 10;
1382 max_2_5_tcyc_ns_x_100 = 10;
1383 max_3_0_tcyc_ns_x_100 = 10;
1384 max_4_0_tcyc_ns_x_100 = 10;
1385 max_5_0_tcyc_ns_x_100 = 10;
1386 sdram_ddr1 = TRUE;
1387
1388 /* loop through all the DIMM slots on the board */
1389 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1390 /* If a dimm is installed in a particular slot ... */
1391 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1392 if (dimm_populated[dimm_num] == SDRAM_DDR1)
1393 sdram_ddr1 = TRUE;
1394 else
1395 sdram_ddr1 = FALSE;
1396
1397 /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /* not used in this loop. */
1398 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
Stefan Roesecabee752007-03-31 13:15:06 +02001399 debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
Stefan Roese4037ed32007-02-20 10:43:34 +01001400
1401 /* For a particular DIMM, grab the three CAS values it supports */
1402 for (cas_index = 0; cas_index < 3; cas_index++) {
1403 switch (cas_index) {
1404 case 0:
1405 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1406 break;
1407 case 1:
1408 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1409 break;
1410 default:
1411 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1412 break;
1413 }
1414
1415 if ((tcyc_reg & 0x0F) >= 10) {
1416 if ((tcyc_reg & 0x0F) == 0x0D) {
1417 /* Convert from hex to decimal */
Stefan Roesecabee752007-03-31 13:15:06 +02001418 cycle_time_ns_x_100[cas_index] =
1419 (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
Stefan Roese4037ed32007-02-20 10:43:34 +01001420 } else {
1421 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1422 "in slot %d\n", (unsigned int)dimm_num);
Heiko Schochera5d71e22007-06-25 19:11:37 +02001423 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01001424 }
1425 } else {
1426 /* Convert from hex to decimal */
Stefan Roesecabee752007-03-31 13:15:06 +02001427 cycle_time_ns_x_100[cas_index] =
1428 (((tcyc_reg & 0xF0) >> 4) * 100) +
Stefan Roese4037ed32007-02-20 10:43:34 +01001429 ((tcyc_reg & 0x0F)*10);
1430 }
Stefan Roesecabee752007-03-31 13:15:06 +02001431 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1432 cycle_time_ns_x_100[cas_index]);
Stefan Roese4037ed32007-02-20 10:43:34 +01001433 }
1434
1435 /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1436 /* supported for a particular DIMM. */
1437 cas_index = 0;
1438
1439 if (sdram_ddr1) {
1440 /*
1441 * DDR devices use the following bitmask for CAS latency:
1442 * Bit 7 6 5 4 3 2 1 0
1443 * TBD 4.0 3.5 3.0 2.5 2.0 1.5 1.0
1444 */
Stefan Roesecabee752007-03-31 13:15:06 +02001445 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1446 (cycle_time_ns_x_100[cas_index] != 0)) {
1447 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1448 cycle_time_ns_x_100[cas_index]);
Stefan Roese4037ed32007-02-20 10:43:34 +01001449 cas_index++;
1450 } else {
1451 if (cas_index != 0)
1452 cas_index++;
1453 cas_4_0_available = FALSE;
1454 }
1455
Stefan Roesecabee752007-03-31 13:15:06 +02001456 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1457 (cycle_time_ns_x_100[cas_index] != 0)) {
1458 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1459 cycle_time_ns_x_100[cas_index]);
Stefan Roese4037ed32007-02-20 10:43:34 +01001460 cas_index++;
1461 } else {
1462 if (cas_index != 0)
1463 cas_index++;
1464 cas_3_0_available = FALSE;
1465 }
1466
Stefan Roesecabee752007-03-31 13:15:06 +02001467 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1468 (cycle_time_ns_x_100[cas_index] != 0)) {
1469 max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1470 cycle_time_ns_x_100[cas_index]);
Stefan Roese4037ed32007-02-20 10:43:34 +01001471 cas_index++;
1472 } else {
1473 if (cas_index != 0)
1474 cas_index++;
1475 cas_2_5_available = FALSE;
1476 }
1477
Stefan Roesecabee752007-03-31 13:15:06 +02001478 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1479 (cycle_time_ns_x_100[cas_index] != 0)) {
1480 max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1481 cycle_time_ns_x_100[cas_index]);
Stefan Roese4037ed32007-02-20 10:43:34 +01001482 cas_index++;
1483 } else {
1484 if (cas_index != 0)
1485 cas_index++;
1486 cas_2_0_available = FALSE;
1487 }
1488 } else {
1489 /*
1490 * DDR2 devices use the following bitmask for CAS latency:
1491 * Bit 7 6 5 4 3 2 1 0
1492 * TBD 6.0 5.0 4.0 3.0 2.0 TBD TBD
1493 */
Stefan Roesecabee752007-03-31 13:15:06 +02001494 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1495 (cycle_time_ns_x_100[cas_index] != 0)) {
1496 max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1497 cycle_time_ns_x_100[cas_index]);
Stefan Roese4037ed32007-02-20 10:43:34 +01001498 cas_index++;
1499 } else {
1500 if (cas_index != 0)
1501 cas_index++;
1502 cas_5_0_available = FALSE;
1503 }
1504
Stefan Roesecabee752007-03-31 13:15:06 +02001505 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1506 (cycle_time_ns_x_100[cas_index] != 0)) {
1507 max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1508 cycle_time_ns_x_100[cas_index]);
Stefan Roese4037ed32007-02-20 10:43:34 +01001509 cas_index++;
1510 } else {
1511 if (cas_index != 0)
1512 cas_index++;
1513 cas_4_0_available = FALSE;
1514 }
1515
Stefan Roesecabee752007-03-31 13:15:06 +02001516 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1517 (cycle_time_ns_x_100[cas_index] != 0)) {
1518 max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1519 cycle_time_ns_x_100[cas_index]);
Stefan Roese4037ed32007-02-20 10:43:34 +01001520 cas_index++;
1521 } else {
1522 if (cas_index != 0)
1523 cas_index++;
1524 cas_3_0_available = FALSE;
1525 }
1526 }
1527 }
1528 }
1529
1530 /*------------------------------------------------------------------
1531 * Set the SDRAM mode, SDRAM_MMODE
1532 *-----------------------------------------------------------------*/
1533 mfsdram(SDRAM_MMODE, mmode);
1534 mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1535
Stefan Roesedf294492007-03-08 10:06:09 +01001536 /* add 10 here because of rounding problems */
1537 cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1538 cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1539 cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1540 cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1541 cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
Stefan Roesecabee752007-03-31 13:15:06 +02001542 debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1543 debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1544 debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
Stefan Roese4037ed32007-02-20 10:43:34 +01001545
1546 if (sdram_ddr1 == TRUE) { /* DDR1 */
1547 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1548 mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1549 *selected_cas = DDR_CAS_2;
1550 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1551 mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1552 *selected_cas = DDR_CAS_2_5;
1553 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1554 mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1555 *selected_cas = DDR_CAS_3;
1556 } else {
1557 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1558 printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1559 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +02001560 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01001561 }
1562 } else { /* DDR2 */
Stefan Roese94f54702007-03-31 08:46:08 +02001563 debug("cas_3_0_available=%d\n", cas_3_0_available);
1564 debug("cas_4_0_available=%d\n", cas_4_0_available);
1565 debug("cas_5_0_available=%d\n", cas_5_0_available);
Stefan Roese4037ed32007-02-20 10:43:34 +01001566 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1567 mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1568 *selected_cas = DDR_CAS_3;
1569 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1570 mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1571 *selected_cas = DDR_CAS_4;
1572 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1573 mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1574 *selected_cas = DDR_CAS_5;
1575 } else {
1576 printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1577 printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
Stefan Roesedf294492007-03-08 10:06:09 +01001578 printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1579 printf("cas3=%d cas4=%d cas5=%d\n",
1580 cas_3_0_available, cas_4_0_available, cas_5_0_available);
1581 printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
1582 sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
Heiko Schochera5d71e22007-06-25 19:11:37 +02001583 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01001584 }
1585 }
1586
1587 if (sdram_ddr1 == TRUE)
1588 mmode |= SDRAM_MMODE_WR_DDR1;
1589 else {
1590
1591 /* loop through all the DIMM slots on the board */
1592 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1593 /* If a dimm is installed in a particular slot ... */
1594 if (dimm_populated[dimm_num] != SDRAM_NONE)
1595 t_wr_ns = max(t_wr_ns,
1596 spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1597 }
1598
1599 /*
1600 * convert from nanoseconds to ddr clocks
1601 * round up if necessary
1602 */
1603 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1604 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1605 if (sdram_freq != ddr_check)
1606 t_wr_clk++;
1607
1608 switch (t_wr_clk) {
1609 case 0:
1610 case 1:
1611 case 2:
1612 case 3:
1613 mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1614 break;
1615 case 4:
1616 mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1617 break;
1618 case 5:
1619 mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1620 break;
1621 default:
1622 mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1623 break;
1624 }
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001625 *write_recovery = t_wr_clk;
Stefan Roese4037ed32007-02-20 10:43:34 +01001626 }
1627
Stefan Roeseba58e4c2007-03-01 21:11:36 +01001628 debug("CAS latency = %d\n", *selected_cas);
1629 debug("Write recovery = %d\n", *write_recovery);
1630
Stefan Roese4037ed32007-02-20 10:43:34 +01001631 mtsdram(SDRAM_MMODE, mmode);
1632}
1633
1634/*-----------------------------------------------------------------------------+
1635 * program_rtr.
1636 *-----------------------------------------------------------------------------*/
1637static void program_rtr(unsigned long *dimm_populated,
1638 unsigned char *iic0_dimm_addr,
1639 unsigned long num_dimm_banks)
1640{
Stefan Roese087dfdb2007-10-21 08:12:41 +02001641 PPC4xx_SYS_INFO board_cfg;
Stefan Roese4037ed32007-02-20 10:43:34 +01001642 unsigned long max_refresh_rate;
1643 unsigned long dimm_num;
1644 unsigned long refresh_rate_type;
1645 unsigned long refresh_rate;
1646 unsigned long rint;
1647 unsigned long sdram_freq;
1648 unsigned long sdr_ddrpll;
1649 unsigned long val;
1650
1651 /*------------------------------------------------------------------
1652 * Get the board configuration info.
1653 *-----------------------------------------------------------------*/
1654 get_sys_info(&board_cfg);
1655
1656 /*------------------------------------------------------------------
1657 * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1658 *-----------------------------------------------------------------*/
Stefan Roesedf294492007-03-08 10:06:09 +01001659 mfsdr(SDR0_DDR0, sdr_ddrpll);
Stefan Roese4037ed32007-02-20 10:43:34 +01001660 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1661
1662 max_refresh_rate = 0;
1663 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1664 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1665
1666 refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1667 refresh_rate_type &= 0x7F;
1668 switch (refresh_rate_type) {
1669 case 0:
1670 refresh_rate = 15625;
1671 break;
1672 case 1:
1673 refresh_rate = 3906;
1674 break;
1675 case 2:
1676 refresh_rate = 7812;
1677 break;
1678 case 3:
1679 refresh_rate = 31250;
1680 break;
1681 case 4:
1682 refresh_rate = 62500;
1683 break;
1684 case 5:
1685 refresh_rate = 125000;
1686 break;
1687 default:
1688 refresh_rate = 0;
1689 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1690 (unsigned int)dimm_num);
1691 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +02001692 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01001693 break;
1694 }
1695
1696 max_refresh_rate = max(max_refresh_rate, refresh_rate);
1697 }
1698 }
1699
1700 rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1701 mfsdram(SDRAM_RTR, val);
1702 mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1703 (SDRAM_RTR_RINT_ENCODE(rint)));
1704}
1705
1706/*------------------------------------------------------------------
1707 * This routine programs the SDRAM_TRx registers.
1708 *-----------------------------------------------------------------*/
1709static void program_tr(unsigned long *dimm_populated,
1710 unsigned char *iic0_dimm_addr,
1711 unsigned long num_dimm_banks)
1712{
1713 unsigned long dimm_num;
1714 unsigned long sdram_ddr1;
1715 unsigned long t_rp_ns;
1716 unsigned long t_rcd_ns;
1717 unsigned long t_rrd_ns;
1718 unsigned long t_ras_ns;
1719 unsigned long t_rc_ns;
1720 unsigned long t_rfc_ns;
1721 unsigned long t_wpc_ns;
1722 unsigned long t_wtr_ns;
1723 unsigned long t_rpc_ns;
1724 unsigned long t_rp_clk;
1725 unsigned long t_rcd_clk;
1726 unsigned long t_rrd_clk;
1727 unsigned long t_ras_clk;
1728 unsigned long t_rc_clk;
1729 unsigned long t_rfc_clk;
1730 unsigned long t_wpc_clk;
1731 unsigned long t_wtr_clk;
1732 unsigned long t_rpc_clk;
1733 unsigned long sdtr1, sdtr2, sdtr3;
1734 unsigned long ddr_check;
1735 unsigned long sdram_freq;
1736 unsigned long sdr_ddrpll;
1737
Stefan Roese087dfdb2007-10-21 08:12:41 +02001738 PPC4xx_SYS_INFO board_cfg;
Stefan Roese4037ed32007-02-20 10:43:34 +01001739
1740 /*------------------------------------------------------------------
1741 * Get the board configuration info.
1742 *-----------------------------------------------------------------*/
1743 get_sys_info(&board_cfg);
1744
Stefan Roesedf294492007-03-08 10:06:09 +01001745 mfsdr(SDR0_DDR0, sdr_ddrpll);
Stefan Roese4037ed32007-02-20 10:43:34 +01001746 sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1747
1748 /*------------------------------------------------------------------
1749 * Handle the timing. We need to find the worst case timing of all
1750 * the dimm modules installed.
1751 *-----------------------------------------------------------------*/
1752 t_rp_ns = 0;
1753 t_rrd_ns = 0;
1754 t_rcd_ns = 0;
1755 t_ras_ns = 0;
1756 t_rc_ns = 0;
1757 t_rfc_ns = 0;
1758 t_wpc_ns = 0;
1759 t_wtr_ns = 0;
1760 t_rpc_ns = 0;
1761 sdram_ddr1 = TRUE;
1762
1763 /* loop through all the DIMM slots on the board */
1764 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1765 /* If a dimm is installed in a particular slot ... */
1766 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1767 if (dimm_populated[dimm_num] == SDRAM_DDR2)
1768 sdram_ddr1 = TRUE;
1769 else
1770 sdram_ddr1 = FALSE;
1771
1772 t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1773 t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1774 t_rp_ns = max(t_rp_ns, spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1775 t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1776 t_rc_ns = max(t_rc_ns, spd_read(iic0_dimm_addr[dimm_num], 41));
1777 t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1778 }
1779 }
1780
1781 /*------------------------------------------------------------------
1782 * Set the SDRAM Timing Reg 1, SDRAM_TR1
1783 *-----------------------------------------------------------------*/
1784 mfsdram(SDRAM_SDTR1, sdtr1);
1785 sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1786 SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1787
1788 /* default values */
1789 sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1790 sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1791
1792 /* normal operations */
1793 sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1794 sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1795
1796 mtsdram(SDRAM_SDTR1, sdtr1);
1797
1798 /*------------------------------------------------------------------
1799 * Set the SDRAM Timing Reg 2, SDRAM_TR2
1800 *-----------------------------------------------------------------*/
1801 mfsdram(SDRAM_SDTR2, sdtr2);
1802 sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK | SDRAM_SDTR2_WTR_MASK |
1803 SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1804 SDRAM_SDTR2_RPC_MASK | SDRAM_SDTR2_RP_MASK |
1805 SDRAM_SDTR2_RRD_MASK);
1806
1807 /*
1808 * convert t_rcd from nanoseconds to ddr clocks
1809 * round up if necessary
1810 */
1811 t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1812 ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1813 if (sdram_freq != ddr_check)
1814 t_rcd_clk++;
1815
1816 switch (t_rcd_clk) {
1817 case 0:
1818 case 1:
1819 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1820 break;
1821 case 2:
1822 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1823 break;
1824 case 3:
1825 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1826 break;
1827 case 4:
1828 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1829 break;
1830 default:
1831 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1832 break;
1833 }
1834
1835 if (sdram_ddr1 == TRUE) { /* DDR1 */
1836 if (sdram_freq < 200000000) {
1837 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1838 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1839 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1840 } else {
1841 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1842 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1843 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1844 }
1845 } else { /* DDR2 */
1846 /* loop through all the DIMM slots on the board */
1847 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1848 /* If a dimm is installed in a particular slot ... */
1849 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1850 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1851 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1852 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1853 }
1854 }
1855
1856 /*
1857 * convert from nanoseconds to ddr clocks
1858 * round up if necessary
1859 */
1860 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1861 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1862 if (sdram_freq != ddr_check)
1863 t_wpc_clk++;
1864
1865 switch (t_wpc_clk) {
1866 case 0:
1867 case 1:
1868 case 2:
1869 sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1870 break;
1871 case 3:
1872 sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1873 break;
1874 case 4:
1875 sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1876 break;
1877 case 5:
1878 sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1879 break;
1880 default:
1881 sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1882 break;
1883 }
1884
1885 /*
1886 * convert from nanoseconds to ddr clocks
1887 * round up if necessary
1888 */
1889 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1890 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1891 if (sdram_freq != ddr_check)
1892 t_wtr_clk++;
1893
1894 switch (t_wtr_clk) {
1895 case 0:
1896 case 1:
1897 sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1898 break;
1899 case 2:
1900 sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1901 break;
1902 case 3:
1903 sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1904 break;
1905 default:
1906 sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1907 break;
1908 }
1909
1910 /*
1911 * convert from nanoseconds to ddr clocks
1912 * round up if necessary
1913 */
1914 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1915 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1916 if (sdram_freq != ddr_check)
1917 t_rpc_clk++;
1918
1919 switch (t_rpc_clk) {
1920 case 0:
1921 case 1:
1922 case 2:
1923 sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1924 break;
1925 case 3:
1926 sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1927 break;
1928 default:
1929 sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1930 break;
1931 }
1932 }
1933
1934 /* default value */
1935 sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1936
1937 /*
1938 * convert t_rrd from nanoseconds to ddr clocks
1939 * round up if necessary
1940 */
1941 t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1942 ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1943 if (sdram_freq != ddr_check)
1944 t_rrd_clk++;
1945
1946 if (t_rrd_clk == 3)
1947 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1948 else
1949 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1950
1951 /*
1952 * convert t_rp from nanoseconds to ddr clocks
1953 * round up if necessary
1954 */
1955 t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1956 ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1957 if (sdram_freq != ddr_check)
1958 t_rp_clk++;
1959
1960 switch (t_rp_clk) {
1961 case 0:
1962 case 1:
1963 case 2:
1964 case 3:
1965 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1966 break;
1967 case 4:
1968 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1969 break;
1970 case 5:
1971 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1972 break;
1973 case 6:
1974 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1975 break;
1976 default:
1977 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1978 break;
1979 }
1980
1981 mtsdram(SDRAM_SDTR2, sdtr2);
1982
1983 /*------------------------------------------------------------------
1984 * Set the SDRAM Timing Reg 3, SDRAM_TR3
1985 *-----------------------------------------------------------------*/
1986 mfsdram(SDRAM_SDTR3, sdtr3);
1987 sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK | SDRAM_SDTR3_RC_MASK |
1988 SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
1989
1990 /*
1991 * convert t_ras from nanoseconds to ddr clocks
1992 * round up if necessary
1993 */
1994 t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
1995 ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
1996 if (sdram_freq != ddr_check)
1997 t_ras_clk++;
1998
1999 sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2000
2001 /*
2002 * convert t_rc from nanoseconds to ddr clocks
2003 * round up if necessary
2004 */
2005 t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2006 ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2007 if (sdram_freq != ddr_check)
2008 t_rc_clk++;
2009
2010 sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2011
2012 /* default xcs value */
2013 sdtr3 |= SDRAM_SDTR3_XCS;
2014
2015 /*
2016 * convert t_rfc from nanoseconds to ddr clocks
2017 * round up if necessary
2018 */
2019 t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2020 ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2021 if (sdram_freq != ddr_check)
2022 t_rfc_clk++;
2023
2024 sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2025
2026 mtsdram(SDRAM_SDTR3, sdtr3);
2027}
2028
2029/*-----------------------------------------------------------------------------+
2030 * program_bxcf.
2031 *-----------------------------------------------------------------------------*/
2032static void program_bxcf(unsigned long *dimm_populated,
2033 unsigned char *iic0_dimm_addr,
2034 unsigned long num_dimm_banks)
2035{
2036 unsigned long dimm_num;
2037 unsigned long num_col_addr;
2038 unsigned long num_ranks;
2039 unsigned long num_banks;
2040 unsigned long mode;
2041 unsigned long ind_rank;
2042 unsigned long ind;
2043 unsigned long ind_bank;
2044 unsigned long bank_0_populated;
2045
2046 /*------------------------------------------------------------------
2047 * Set the BxCF regs. First, wipe out the bank config registers.
2048 *-----------------------------------------------------------------*/
Stefan Roese087dfdb2007-10-21 08:12:41 +02002049 mtsdram(SDRAM_MB0CF, 0x00000000);
2050 mtsdram(SDRAM_MB1CF, 0x00000000);
2051 mtsdram(SDRAM_MB2CF, 0x00000000);
2052 mtsdram(SDRAM_MB3CF, 0x00000000);
Stefan Roese4037ed32007-02-20 10:43:34 +01002053
2054 mode = SDRAM_BXCF_M_BE_ENABLE;
2055
2056 bank_0_populated = 0;
2057
2058 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2059 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2060 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2061 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2062 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2063 num_ranks = (num_ranks & 0x0F) +1;
2064 else
2065 num_ranks = num_ranks & 0x0F;
2066
2067 num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2068
2069 for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2070 if (num_banks == 4)
2071 ind = 0;
2072 else
2073 ind = 5;
2074 switch (num_col_addr) {
2075 case 0x08:
2076 mode |= (SDRAM_BXCF_M_AM_0 + ind);
2077 break;
2078 case 0x09:
2079 mode |= (SDRAM_BXCF_M_AM_1 + ind);
2080 break;
2081 case 0x0A:
2082 mode |= (SDRAM_BXCF_M_AM_2 + ind);
2083 break;
2084 case 0x0B:
2085 mode |= (SDRAM_BXCF_M_AM_3 + ind);
2086 break;
2087 case 0x0C:
2088 mode |= (SDRAM_BXCF_M_AM_4 + ind);
2089 break;
2090 default:
2091 printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2092 (unsigned int)dimm_num);
2093 printf("ERROR: Unsupported value for number of "
2094 "column addresses: %d.\n", (unsigned int)num_col_addr);
2095 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +02002096 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01002097 }
2098 }
2099
2100 if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2101 bank_0_populated = 1;
2102
2103 for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
Stefan Roese087dfdb2007-10-21 08:12:41 +02002104 mtsdram(SDRAM_MB0CF +
2105 ((dimm_num + bank_0_populated + ind_rank) << 2),
2106 mode);
Stefan Roese4037ed32007-02-20 10:43:34 +01002107 }
2108 }
2109 }
2110}
2111
2112/*------------------------------------------------------------------
2113 * program memory queue.
2114 *-----------------------------------------------------------------*/
2115static void program_memory_queue(unsigned long *dimm_populated,
2116 unsigned char *iic0_dimm_addr,
2117 unsigned long num_dimm_banks)
2118{
2119 unsigned long dimm_num;
2120 unsigned long rank_base_addr;
2121 unsigned long rank_reg;
2122 unsigned long rank_size_bytes;
2123 unsigned long rank_size_id;
2124 unsigned long num_ranks;
2125 unsigned long baseadd_size;
2126 unsigned long i;
2127 unsigned long bank_0_populated = 0;
2128
2129 /*------------------------------------------------------------------
2130 * Reset the rank_base_address.
2131 *-----------------------------------------------------------------*/
2132 rank_reg = SDRAM_R0BAS;
2133
2134 rank_base_addr = 0x00000000;
2135
2136 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2137 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2138 num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2139 if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2140 num_ranks = (num_ranks & 0x0F) + 1;
2141 else
2142 num_ranks = num_ranks & 0x0F;
2143
2144 rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2145
2146 /*------------------------------------------------------------------
2147 * Set the sizes
2148 *-----------------------------------------------------------------*/
2149 baseadd_size = 0;
Stefan Roesedf294492007-03-08 10:06:09 +01002150 rank_size_bytes = 4 * 1024 * 1024 * rank_size_id;
Stefan Roese4037ed32007-02-20 10:43:34 +01002151 switch (rank_size_id) {
2152 case 0x02:
2153 baseadd_size |= SDRAM_RXBAS_SDSZ_8;
2154 break;
2155 case 0x04:
2156 baseadd_size |= SDRAM_RXBAS_SDSZ_16;
2157 break;
2158 case 0x08:
2159 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2160 break;
2161 case 0x10:
2162 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2163 break;
2164 case 0x20:
2165 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2166 break;
2167 case 0x40:
2168 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2169 break;
2170 case 0x80:
2171 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2172 break;
2173 default:
2174 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2175 (unsigned int)dimm_num);
2176 printf("ERROR: Unsupported value for the banksize: %d.\n",
2177 (unsigned int)rank_size_id);
2178 printf("Replace the DIMM module with a supported DIMM.\n\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +02002179 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01002180 }
2181
2182 if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2183 bank_0_populated = 1;
2184
2185 for (i = 0; i < num_ranks; i++) {
2186 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
Stefan Roesedf294492007-03-08 10:06:09 +01002187 (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2188 baseadd_size));
Stefan Roese4037ed32007-02-20 10:43:34 +01002189 rank_base_addr += rank_size_bytes;
2190 }
2191 }
2192 }
2193}
2194
2195/*-----------------------------------------------------------------------------+
2196 * is_ecc_enabled.
2197 *-----------------------------------------------------------------------------*/
2198static unsigned long is_ecc_enabled(void)
2199{
2200 unsigned long dimm_num;
2201 unsigned long ecc;
2202 unsigned long val;
2203
2204 ecc = 0;
2205 /* loop through all the DIMM slots on the board */
2206 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2207 mfsdram(SDRAM_MCOPT1, val);
2208 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2209 }
2210
Stefan Roesedf294492007-03-08 10:06:09 +01002211 return ecc;
Stefan Roese4037ed32007-02-20 10:43:34 +01002212}
2213
Stefan Roese94f54702007-03-31 08:46:08 +02002214static void blank_string(int size)
2215{
2216 int i;
2217
2218 for (i=0; i<size; i++)
2219 putc('\b');
2220 for (i=0; i<size; i++)
2221 putc(' ');
2222 for (i=0; i<size; i++)
2223 putc('\b');
2224}
2225
Stefan Roesedf294492007-03-08 10:06:09 +01002226#ifdef CONFIG_DDR_ECC
Stefan Roese4037ed32007-02-20 10:43:34 +01002227/*-----------------------------------------------------------------------------+
2228 * program_ecc.
2229 *-----------------------------------------------------------------------------*/
2230static void program_ecc(unsigned long *dimm_populated,
2231 unsigned char *iic0_dimm_addr,
Stefan Roeseba58e4c2007-03-01 21:11:36 +01002232 unsigned long num_dimm_banks,
2233 unsigned long tlb_word2_i_value)
Stefan Roese4037ed32007-02-20 10:43:34 +01002234{
2235 unsigned long mcopt1;
2236 unsigned long mcopt2;
2237 unsigned long mcstat;
2238 unsigned long dimm_num;
2239 unsigned long ecc;
2240
2241 ecc = 0;
2242 /* loop through all the DIMM slots on the board */
2243 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2244 /* If a dimm is installed in a particular slot ... */
2245 if (dimm_populated[dimm_num] != SDRAM_NONE)
2246 ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2247 }
2248 if (ecc == 0)
2249 return;
2250
2251 mfsdram(SDRAM_MCOPT1, mcopt1);
2252 mfsdram(SDRAM_MCOPT2, mcopt2);
2253
2254 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2255 /* DDR controller must be enabled and not in self-refresh. */
2256 mfsdram(SDRAM_MCSTAT, mcstat);
2257 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2258 && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2259 && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2260 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2261
Stefan Roeseba58e4c2007-03-01 21:11:36 +01002262 program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
Stefan Roese4037ed32007-02-20 10:43:34 +01002263 }
2264 }
2265
2266 return;
2267}
2268
Stefan Roesedf294492007-03-08 10:06:09 +01002269static void wait_ddr_idle(void)
2270{
2271 u32 val;
2272
2273 do {
2274 mfsdram(SDRAM_MCSTAT, val);
2275 } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2276}
2277
Stefan Roese4037ed32007-02-20 10:43:34 +01002278/*-----------------------------------------------------------------------------+
2279 * program_ecc_addr.
2280 *-----------------------------------------------------------------------------*/
2281static void program_ecc_addr(unsigned long start_address,
Stefan Roeseba58e4c2007-03-01 21:11:36 +01002282 unsigned long num_bytes,
2283 unsigned long tlb_word2_i_value)
Stefan Roese4037ed32007-02-20 10:43:34 +01002284{
2285 unsigned long current_address;
2286 unsigned long end_address;
2287 unsigned long address_increment;
2288 unsigned long mcopt1;
Stefan Roese94f54702007-03-31 08:46:08 +02002289 char str[] = "ECC generation -";
2290 char slash[] = "\\|/-\\|/-";
2291 int loop = 0;
2292 int loopi = 0;
Stefan Roese4037ed32007-02-20 10:43:34 +01002293
2294 current_address = start_address;
2295 mfsdram(SDRAM_MCOPT1, mcopt1);
2296 if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2297 mtsdram(SDRAM_MCOPT1,
2298 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2299 sync();
2300 eieio();
2301 wait_ddr_idle();
2302
Stefan Roeseba58e4c2007-03-01 21:11:36 +01002303 puts(str);
2304 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2305 /* ECC bit set method for non-cached memory */
2306 if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2307 address_increment = 4;
2308 else
2309 address_increment = 8;
2310 end_address = current_address + num_bytes;
Stefan Roese4037ed32007-02-20 10:43:34 +01002311
Stefan Roeseba58e4c2007-03-01 21:11:36 +01002312 while (current_address < end_address) {
2313 *((unsigned long *)current_address) = 0x00000000;
2314 current_address += address_increment;
Stefan Roese94f54702007-03-31 08:46:08 +02002315
2316 if ((loop++ % (2 << 20)) == 0) {
2317 putc('\b');
2318 putc(slash[loopi++ % 8]);
2319 }
Stefan Roeseba58e4c2007-03-01 21:11:36 +01002320 }
Stefan Roese94f54702007-03-31 08:46:08 +02002321
Stefan Roeseba58e4c2007-03-01 21:11:36 +01002322 } else {
2323 /* ECC bit set method for cached memory */
2324 dcbz_area(start_address, num_bytes);
2325 dflush();
Stefan Roese4037ed32007-02-20 10:43:34 +01002326 }
Stefan Roese94f54702007-03-31 08:46:08 +02002327
2328 blank_string(strlen(str));
Stefan Roeseba58e4c2007-03-01 21:11:36 +01002329
Stefan Roese4037ed32007-02-20 10:43:34 +01002330 sync();
2331 eieio();
2332 wait_ddr_idle();
2333
Stefan Roeseba58e4c2007-03-01 21:11:36 +01002334 /* clear ECC error repoting registers */
2335 mtsdram(SDRAM_ECCCR, 0xffffffff);
2336 mtdcr(0x4c, 0xffffffff);
2337
Stefan Roese4037ed32007-02-20 10:43:34 +01002338 mtsdram(SDRAM_MCOPT1,
Stefan Roeseba58e4c2007-03-01 21:11:36 +01002339 (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
Stefan Roese4037ed32007-02-20 10:43:34 +01002340 sync();
2341 eieio();
2342 wait_ddr_idle();
Stefan Roese4037ed32007-02-20 10:43:34 +01002343 }
2344}
Stefan Roesedf294492007-03-08 10:06:09 +01002345#endif
Stefan Roese4037ed32007-02-20 10:43:34 +01002346
2347/*-----------------------------------------------------------------------------+
2348 * program_DQS_calibration.
2349 *-----------------------------------------------------------------------------*/
2350static void program_DQS_calibration(unsigned long *dimm_populated,
2351 unsigned char *iic0_dimm_addr,
2352 unsigned long num_dimm_banks)
2353{
2354 unsigned long val;
2355
2356#ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2357 mtsdram(SDRAM_RQDC, 0x80000037);
2358 mtsdram(SDRAM_RDCC, 0x40000000);
2359 mtsdram(SDRAM_RFDC, 0x000001DF);
2360
2361 test();
2362#else
2363 /*------------------------------------------------------------------
2364 * Program RDCC register
2365 * Read sample cycle auto-update enable
2366 *-----------------------------------------------------------------*/
2367
Stefan Roese4037ed32007-02-20 10:43:34 +01002368 mfsdram(SDRAM_RDCC, val);
2369 mtsdram(SDRAM_RDCC,
2370 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
Stefan Roese845c6c92008-01-05 09:12:41 +01002371 | SDRAM_RDCC_RSAE_ENABLE);
Stefan Roese4037ed32007-02-20 10:43:34 +01002372
2373 /*------------------------------------------------------------------
2374 * Program RQDC register
2375 * Internal DQS delay mechanism enable
2376 *-----------------------------------------------------------------*/
2377 mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2378
2379 /*------------------------------------------------------------------
2380 * Program RFDC register
2381 * Set Feedback Fractional Oversample
2382 * Auto-detect read sample cycle enable
2383 *-----------------------------------------------------------------*/
2384 mfsdram(SDRAM_RFDC, val);
2385 mtsdram(SDRAM_RFDC,
2386 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2387 SDRAM_RFDC_RFFD_MASK))
2388 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2389 SDRAM_RFDC_RFFD_ENCODE(0)));
2390
2391 DQS_calibration_process();
2392#endif
2393}
2394
Stefan Roese94f54702007-03-31 08:46:08 +02002395static int short_mem_test(void)
Stefan Roese4037ed32007-02-20 10:43:34 +01002396{
2397 u32 *membase;
2398 u32 bxcr_num;
2399 u32 bxcf;
2400 int i;
2401 int j;
2402 u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2403 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2404 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2405 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2406 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2407 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2408 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2409 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2410 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2411 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2412 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2413 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2414 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2415 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2416 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2417 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2418 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
Stefan Roese94f54702007-03-31 08:46:08 +02002419 int l;
Stefan Roese4037ed32007-02-20 10:43:34 +01002420
2421 for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2422 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2423
2424 /* Banks enabled */
2425 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
Stefan Roese4037ed32007-02-20 10:43:34 +01002426 /* Bank is enabled */
Stefan Roese4037ed32007-02-20 10:43:34 +01002427
2428 /*------------------------------------------------------------------
2429 * Run the short memory test.
2430 *-----------------------------------------------------------------*/
Stefan Roese94f54702007-03-31 08:46:08 +02002431 membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2432
Stefan Roese4037ed32007-02-20 10:43:34 +01002433 for (i = 0; i < NUMMEMTESTS; i++) {
2434 for (j = 0; j < NUMMEMWORDS; j++) {
2435 membase[j] = test[i][j];
2436 ppcDcbf((u32)&(membase[j]));
2437 }
2438 sync();
Stefan Roese94f54702007-03-31 08:46:08 +02002439 for (l=0; l<NUMLOOPS; l++) {
2440 for (j = 0; j < NUMMEMWORDS; j++) {
2441 if (membase[j] != test[i][j]) {
2442 ppcDcbf((u32)&(membase[j]));
2443 return 0;
2444 }
Stefan Roese4037ed32007-02-20 10:43:34 +01002445 ppcDcbf((u32)&(membase[j]));
Stefan Roese4037ed32007-02-20 10:43:34 +01002446 }
Stefan Roese94f54702007-03-31 08:46:08 +02002447 sync();
Stefan Roese4037ed32007-02-20 10:43:34 +01002448 }
Stefan Roese4037ed32007-02-20 10:43:34 +01002449 }
Stefan Roese4037ed32007-02-20 10:43:34 +01002450 } /* if bank enabled */
2451 } /* for bxcf_num */
2452
Stefan Roese94f54702007-03-31 08:46:08 +02002453 return 1;
Stefan Roese4037ed32007-02-20 10:43:34 +01002454}
2455
2456#ifndef HARD_CODED_DQS
2457/*-----------------------------------------------------------------------------+
2458 * DQS_calibration_process.
2459 *-----------------------------------------------------------------------------*/
2460static void DQS_calibration_process(void)
2461{
Stefan Roese4037ed32007-02-20 10:43:34 +01002462 unsigned long rfdc_reg;
2463 unsigned long rffd;
Stefan Roese4037ed32007-02-20 10:43:34 +01002464 unsigned long val;
Stefan Roese4037ed32007-02-20 10:43:34 +01002465 long rffd_average;
2466 long max_start;
2467 long min_end;
2468 unsigned long begin_rqfd[MAXRANKS];
2469 unsigned long begin_rffd[MAXRANKS];
2470 unsigned long end_rqfd[MAXRANKS];
2471 unsigned long end_rffd[MAXRANKS];
2472 char window_found;
2473 unsigned long dlycal;
2474 unsigned long dly_val;
2475 unsigned long max_pass_length;
2476 unsigned long current_pass_length;
2477 unsigned long current_fail_length;
2478 unsigned long current_start;
2479 long max_end;
2480 unsigned char fail_found;
2481 unsigned char pass_found;
Stefan Roese845c6c92008-01-05 09:12:41 +01002482#if !defined(CONFIG_DDR_RQDC_FIXED)
2483 u32 rqdc_reg;
2484 u32 rqfd;
Stefan Roese94f54702007-03-31 08:46:08 +02002485 u32 rqfd_start;
Stefan Roese845c6c92008-01-05 09:12:41 +01002486 u32 rqfd_average;
2487 int loopi = 0;
Stefan Roese94f54702007-03-31 08:46:08 +02002488 char str[] = "Auto calibration -";
2489 char slash[] = "\\|/-\\|/-";
Stefan Roese4037ed32007-02-20 10:43:34 +01002490
2491 /*------------------------------------------------------------------
2492 * Test to determine the best read clock delay tuning bits.
2493 *
2494 * Before the DDR controller can be used, the read clock delay needs to be
2495 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2496 * This value cannot be hardcoded into the program because it changes
2497 * depending on the board's setup and environment.
2498 * To do this, all delay values are tested to see if they
2499 * work or not. By doing this, you get groups of fails with groups of
2500 * passing values. The idea is to find the start and end of a passing
2501 * window and take the center of it to use as the read clock delay.
2502 *
2503 * A failure has to be seen first so that when we hit a pass, we know
2504 * that it is truely the start of the window. If we get passing values
2505 * to start off with, we don't know if we are at the start of the window.
2506 *
2507 * The code assumes that a failure will always be found.
2508 * If a failure is not found, there is no easy way to get the middle
2509 * of the passing window. I guess we can pretty much pick any value
2510 * but some values will be better than others. Since the lowest speed
2511 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2512 * from experimentation it is safe to say you will always have a failure.
2513 *-----------------------------------------------------------------*/
Stefan Roese94f54702007-03-31 08:46:08 +02002514
2515 /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2516 rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2517
2518 puts(str);
2519
2520calibration_loop:
2521 mfsdram(SDRAM_RQDC, rqdc_reg);
2522 mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2523 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
Stefan Roese845c6c92008-01-05 09:12:41 +01002524#else /* CONFIG_DDR_RQDC_FIXED */
2525 /*
2526 * On Katmai the complete auto-calibration somehow doesn't seem to
2527 * produce the best results, meaning optimal values for RQFD/RFFD.
2528 * This was discovered by GDA using a high bandwidth scope,
2529 * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2530 * so now on Katmai "only" RFFD is auto-calibrated.
2531 */
2532 mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2533#endif /* CONFIG_DDR_RQDC_FIXED */
Stefan Roese4037ed32007-02-20 10:43:34 +01002534
2535 max_start = 0;
2536 min_end = 0;
2537 begin_rqfd[0] = 0;
2538 begin_rffd[0] = 0;
2539 begin_rqfd[1] = 0;
2540 begin_rffd[1] = 0;
2541 end_rqfd[0] = 0;
2542 end_rffd[0] = 0;
2543 end_rqfd[1] = 0;
2544 end_rffd[1] = 0;
2545 window_found = FALSE;
2546
2547 max_pass_length = 0;
2548 max_start = 0;
2549 max_end = 0;
2550 current_pass_length = 0;
2551 current_fail_length = 0;
2552 current_start = 0;
2553 window_found = FALSE;
2554 fail_found = FALSE;
2555 pass_found = FALSE;
2556
Stefan Roese4037ed32007-02-20 10:43:34 +01002557 /*
2558 * get the delay line calibration register value
2559 */
2560 mfsdram(SDRAM_DLCR, dlycal);
2561 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2562
2563 for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2564 mfsdram(SDRAM_RFDC, rfdc_reg);
2565 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2566
2567 /*------------------------------------------------------------------
2568 * Set the timing reg for the test.
2569 *-----------------------------------------------------------------*/
2570 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2571
Stefan Roese4037ed32007-02-20 10:43:34 +01002572 /*------------------------------------------------------------------
2573 * See if the rffd value passed.
2574 *-----------------------------------------------------------------*/
Stefan Roese94f54702007-03-31 08:46:08 +02002575 if (short_mem_test()) {
Stefan Roese4037ed32007-02-20 10:43:34 +01002576 if (fail_found == TRUE) {
2577 pass_found = TRUE;
2578 if (current_pass_length == 0)
2579 current_start = rffd;
2580
2581 current_fail_length = 0;
2582 current_pass_length++;
2583
2584 if (current_pass_length > max_pass_length) {
2585 max_pass_length = current_pass_length;
2586 max_start = current_start;
2587 max_end = rffd;
2588 }
2589 }
2590 } else {
2591 current_pass_length = 0;
2592 current_fail_length++;
2593
2594 if (current_fail_length >= (dly_val >> 2)) {
2595 if (fail_found == FALSE) {
2596 fail_found = TRUE;
2597 } else if (pass_found == TRUE) {
2598 window_found = TRUE;
2599 break;
2600 }
2601 }
2602 }
2603 } /* for rffd */
2604
Stefan Roese4037ed32007-02-20 10:43:34 +01002605 /*------------------------------------------------------------------
2606 * Set the average RFFD value
2607 *-----------------------------------------------------------------*/
2608 rffd_average = ((max_start + max_end) >> 1);
2609
2610 if (rffd_average < 0)
2611 rffd_average = 0;
2612
2613 if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2614 rffd_average = SDRAM_RFDC_RFFD_MAX;
2615 /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2616 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2617
Stefan Roese845c6c92008-01-05 09:12:41 +01002618#if !defined(CONFIG_DDR_RQDC_FIXED)
Stefan Roese4037ed32007-02-20 10:43:34 +01002619 max_pass_length = 0;
2620 max_start = 0;
2621 max_end = 0;
2622 current_pass_length = 0;
2623 current_fail_length = 0;
2624 current_start = 0;
2625 window_found = FALSE;
2626 fail_found = FALSE;
2627 pass_found = FALSE;
2628
2629 for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2630 mfsdram(SDRAM_RQDC, rqdc_reg);
2631 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2632
2633 /*------------------------------------------------------------------
2634 * Set the timing reg for the test.
2635 *-----------------------------------------------------------------*/
2636 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2637
Stefan Roese4037ed32007-02-20 10:43:34 +01002638 /*------------------------------------------------------------------
2639 * See if the rffd value passed.
2640 *-----------------------------------------------------------------*/
Stefan Roese94f54702007-03-31 08:46:08 +02002641 if (short_mem_test()) {
Stefan Roese4037ed32007-02-20 10:43:34 +01002642 if (fail_found == TRUE) {
2643 pass_found = TRUE;
2644 if (current_pass_length == 0)
2645 current_start = rqfd;
2646
2647 current_fail_length = 0;
2648 current_pass_length++;
2649
2650 if (current_pass_length > max_pass_length) {
2651 max_pass_length = current_pass_length;
2652 max_start = current_start;
2653 max_end = rqfd;
2654 }
2655 }
2656 } else {
2657 current_pass_length = 0;
2658 current_fail_length++;
2659
2660 if (fail_found == FALSE) {
2661 fail_found = TRUE;
2662 } else if (pass_found == TRUE) {
2663 window_found = TRUE;
2664 break;
2665 }
2666 }
2667 }
2668
Stefan Roese94f54702007-03-31 08:46:08 +02002669 rqfd_average = ((max_start + max_end) >> 1);
2670
Stefan Roese4037ed32007-02-20 10:43:34 +01002671 /*------------------------------------------------------------------
2672 * Make sure we found the valid read passing window. Halt if not
2673 *-----------------------------------------------------------------*/
2674 if (window_found == FALSE) {
Stefan Roese94f54702007-03-31 08:46:08 +02002675 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2676 putc('\b');
2677 putc(slash[loopi++ % 8]);
2678
2679 /* try again from with a different RQFD start value */
2680 rqfd_start++;
2681 goto calibration_loop;
2682 }
2683
2684 printf("\nERROR: Cannot determine a common read delay for the "
Stefan Roese4037ed32007-02-20 10:43:34 +01002685 "DIMM(s) installed.\n");
2686 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
Stefan Roese6ed14ad2007-07-16 09:57:00 +02002687 ppc440sp_sdram_register_dump();
Heiko Schochera5d71e22007-06-25 19:11:37 +02002688 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01002689 }
2690
Stefan Roese4037ed32007-02-20 10:43:34 +01002691 if (rqfd_average < 0)
2692 rqfd_average = 0;
2693
2694 if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2695 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2696
Stefan Roese4037ed32007-02-20 10:43:34 +01002697 mtsdram(SDRAM_RQDC,
2698 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2699 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2700
Stefan Roese845c6c92008-01-05 09:12:41 +01002701 blank_string(strlen(str));
2702#endif /* CONFIG_DDR_RQDC_FIXED */
2703
2704 /*
2705 * Now complete RDSS configuration as mentioned on page 7 of the AMCC
2706 * PowerPC440SP/SPe DDR2 application note:
2707 * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
2708 */
2709 mfsdram(SDRAM_RTSR, val);
2710 if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
2711 mfsdram(SDRAM_RDCC, val);
2712 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
2713 val += 0x40000000;
2714 mtsdram(SDRAM_RDCC, val);
2715 }
2716 }
2717
Stefan Roese4037ed32007-02-20 10:43:34 +01002718 mfsdram(SDRAM_DLCR, val);
2719 debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2720 mfsdram(SDRAM_RQDC, val);
2721 debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2722 mfsdram(SDRAM_RFDC, val);
2723 debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
Stefan Roese845c6c92008-01-05 09:12:41 +01002724 mfsdram(SDRAM_RDCC, val);
2725 debug("%s[%d] RDCC: 0x%08X\n", __FUNCTION__, __LINE__, val);
Stefan Roese4037ed32007-02-20 10:43:34 +01002726}
2727#else /* calibration test with hardvalues */
2728/*-----------------------------------------------------------------------------+
2729 * DQS_calibration_process.
2730 *-----------------------------------------------------------------------------*/
2731static void test(void)
2732{
2733 unsigned long dimm_num;
2734 unsigned long ecc_temp;
2735 unsigned long i, j;
2736 unsigned long *membase;
2737 unsigned long bxcf[MAXRANKS];
2738 unsigned long val;
2739 char window_found;
2740 char begin_found[MAXDIMMS];
2741 char end_found[MAXDIMMS];
2742 char search_end[MAXDIMMS];
2743 unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2744 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2745 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2746 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2747 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2748 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2749 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2750 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2751 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2752 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2753 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2754 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2755 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2756 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2757 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2758 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2759 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2760
2761 /*------------------------------------------------------------------
2762 * Test to determine the best read clock delay tuning bits.
2763 *
2764 * Before the DDR controller can be used, the read clock delay needs to be
2765 * set. This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2766 * This value cannot be hardcoded into the program because it changes
2767 * depending on the board's setup and environment.
2768 * To do this, all delay values are tested to see if they
2769 * work or not. By doing this, you get groups of fails with groups of
2770 * passing values. The idea is to find the start and end of a passing
2771 * window and take the center of it to use as the read clock delay.
2772 *
2773 * A failure has to be seen first so that when we hit a pass, we know
2774 * that it is truely the start of the window. If we get passing values
2775 * to start off with, we don't know if we are at the start of the window.
2776 *
2777 * The code assumes that a failure will always be found.
2778 * If a failure is not found, there is no easy way to get the middle
2779 * of the passing window. I guess we can pretty much pick any value
2780 * but some values will be better than others. Since the lowest speed
2781 * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2782 * from experimentation it is safe to say you will always have a failure.
2783 *-----------------------------------------------------------------*/
2784 mfsdram(SDRAM_MCOPT1, ecc_temp);
2785 ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2786 mfsdram(SDRAM_MCOPT1, val);
2787 mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2788 SDRAM_MCOPT1_MCHK_NON);
2789
2790 window_found = FALSE;
2791 begin_found[0] = FALSE;
2792 end_found[0] = FALSE;
2793 search_end[0] = FALSE;
2794 begin_found[1] = FALSE;
2795 end_found[1] = FALSE;
2796 search_end[1] = FALSE;
2797
2798 for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2799 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2800
2801 /* Banks enabled */
2802 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2803
2804 /* Bank is enabled */
2805 membase =
2806 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2807
2808 /*------------------------------------------------------------------
2809 * Run the short memory test.
2810 *-----------------------------------------------------------------*/
2811 for (i = 0; i < NUMMEMTESTS; i++) {
2812 for (j = 0; j < NUMMEMWORDS; j++) {
2813 membase[j] = test[i][j];
2814 ppcDcbf((u32)&(membase[j]));
2815 }
2816 sync();
2817 for (j = 0; j < NUMMEMWORDS; j++) {
2818 if (membase[j] != test[i][j]) {
2819 ppcDcbf((u32)&(membase[j]));
2820 break;
2821 }
2822 ppcDcbf((u32)&(membase[j]));
2823 }
2824 sync();
2825 if (j < NUMMEMWORDS)
2826 break;
2827 }
2828
2829 /*------------------------------------------------------------------
2830 * See if the rffd value passed.
2831 *-----------------------------------------------------------------*/
2832 if (i < NUMMEMTESTS) {
2833 if ((end_found[dimm_num] == FALSE) &&
2834 (search_end[dimm_num] == TRUE)) {
2835 end_found[dimm_num] = TRUE;
2836 }
2837 if ((end_found[0] == TRUE) &&
2838 (end_found[1] == TRUE))
2839 break;
2840 } else {
2841 if (begin_found[dimm_num] == FALSE) {
2842 begin_found[dimm_num] = TRUE;
2843 search_end[dimm_num] = TRUE;
2844 }
2845 }
2846 } else {
2847 begin_found[dimm_num] = TRUE;
2848 end_found[dimm_num] = TRUE;
2849 }
2850 }
2851
2852 if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2853 window_found = TRUE;
2854
2855 /*------------------------------------------------------------------
2856 * Make sure we found the valid read passing window. Halt if not
2857 *-----------------------------------------------------------------*/
2858 if (window_found == FALSE) {
2859 printf("ERROR: Cannot determine a common read delay for the "
2860 "DIMM(s) installed.\n");
Heiko Schochera5d71e22007-06-25 19:11:37 +02002861 spd_ddr_init_hang ();
Stefan Roese4037ed32007-02-20 10:43:34 +01002862 }
2863
2864 /*------------------------------------------------------------------
2865 * Restore the ECC variable to what it originally was
2866 *-----------------------------------------------------------------*/
2867 mtsdram(SDRAM_MCOPT1,
2868 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2869 | ecc_temp);
2870}
2871#endif
2872
2873#if defined(DEBUG)
2874static void ppc440sp_sdram_register_dump(void)
2875{
2876 unsigned int sdram_reg;
2877 unsigned int sdram_data;
2878 unsigned int dcr_data;
2879
2880 printf("\n Register Dump:\n");
2881 sdram_reg = SDRAM_MCSTAT;
2882 mfsdram(sdram_reg, sdram_data);
2883 printf(" SDRAM_MCSTAT = 0x%08X", sdram_data);
2884 sdram_reg = SDRAM_MCOPT1;
2885 mfsdram(sdram_reg, sdram_data);
2886 printf(" SDRAM_MCOPT1 = 0x%08X\n", sdram_data);
2887 sdram_reg = SDRAM_MCOPT2;
2888 mfsdram(sdram_reg, sdram_data);
2889 printf(" SDRAM_MCOPT2 = 0x%08X", sdram_data);
2890 sdram_reg = SDRAM_MODT0;
2891 mfsdram(sdram_reg, sdram_data);
2892 printf(" SDRAM_MODT0 = 0x%08X\n", sdram_data);
2893 sdram_reg = SDRAM_MODT1;
2894 mfsdram(sdram_reg, sdram_data);
2895 printf(" SDRAM_MODT1 = 0x%08X", sdram_data);
2896 sdram_reg = SDRAM_MODT2;
2897 mfsdram(sdram_reg, sdram_data);
2898 printf(" SDRAM_MODT2 = 0x%08X\n", sdram_data);
2899 sdram_reg = SDRAM_MODT3;
2900 mfsdram(sdram_reg, sdram_data);
2901 printf(" SDRAM_MODT3 = 0x%08X", sdram_data);
2902 sdram_reg = SDRAM_CODT;
2903 mfsdram(sdram_reg, sdram_data);
2904 printf(" SDRAM_CODT = 0x%08X\n", sdram_data);
2905 sdram_reg = SDRAM_VVPR;
2906 mfsdram(sdram_reg, sdram_data);
2907 printf(" SDRAM_VVPR = 0x%08X", sdram_data);
2908 sdram_reg = SDRAM_OPARS;
2909 mfsdram(sdram_reg, sdram_data);
2910 printf(" SDRAM_OPARS = 0x%08X\n", sdram_data);
2911 /*
2912 * OPAR2 is only used as a trigger register.
2913 * No data is contained in this register, and reading or writing
2914 * to is can cause bad things to happen (hangs). Just skip it
2915 * and report NA
2916 * sdram_reg = SDRAM_OPAR2;
2917 * mfsdram(sdram_reg, sdram_data);
2918 * printf(" SDRAM_OPAR2 = 0x%08X\n", sdram_data);
2919 */
2920 printf(" SDRAM_OPART = N/A ");
2921 sdram_reg = SDRAM_RTR;
2922 mfsdram(sdram_reg, sdram_data);
2923 printf(" SDRAM_RTR = 0x%08X\n", sdram_data);
2924 sdram_reg = SDRAM_MB0CF;
2925 mfsdram(sdram_reg, sdram_data);
2926 printf(" SDRAM_MB0CF = 0x%08X", sdram_data);
2927 sdram_reg = SDRAM_MB1CF;
2928 mfsdram(sdram_reg, sdram_data);
2929 printf(" SDRAM_MB1CF = 0x%08X\n", sdram_data);
2930 sdram_reg = SDRAM_MB2CF;
2931 mfsdram(sdram_reg, sdram_data);
2932 printf(" SDRAM_MB2CF = 0x%08X", sdram_data);
2933 sdram_reg = SDRAM_MB3CF;
2934 mfsdram(sdram_reg, sdram_data);
2935 printf(" SDRAM_MB3CF = 0x%08X\n", sdram_data);
2936 sdram_reg = SDRAM_INITPLR0;
2937 mfsdram(sdram_reg, sdram_data);
2938 printf(" SDRAM_INITPLR0 = 0x%08X", sdram_data);
2939 sdram_reg = SDRAM_INITPLR1;
2940 mfsdram(sdram_reg, sdram_data);
2941 printf(" SDRAM_INITPLR1 = 0x%08X\n", sdram_data);
2942 sdram_reg = SDRAM_INITPLR2;
2943 mfsdram(sdram_reg, sdram_data);
2944 printf(" SDRAM_INITPLR2 = 0x%08X", sdram_data);
2945 sdram_reg = SDRAM_INITPLR3;
2946 mfsdram(sdram_reg, sdram_data);
2947 printf(" SDRAM_INITPLR3 = 0x%08X\n", sdram_data);
2948 sdram_reg = SDRAM_INITPLR4;
2949 mfsdram(sdram_reg, sdram_data);
2950 printf(" SDRAM_INITPLR4 = 0x%08X", sdram_data);
2951 sdram_reg = SDRAM_INITPLR5;
2952 mfsdram(sdram_reg, sdram_data);
2953 printf(" SDRAM_INITPLR5 = 0x%08X\n", sdram_data);
2954 sdram_reg = SDRAM_INITPLR6;
2955 mfsdram(sdram_reg, sdram_data);
2956 printf(" SDRAM_INITPLR6 = 0x%08X", sdram_data);
2957 sdram_reg = SDRAM_INITPLR7;
2958 mfsdram(sdram_reg, sdram_data);
2959 printf(" SDRAM_INITPLR7 = 0x%08X\n", sdram_data);
2960 sdram_reg = SDRAM_INITPLR8;
2961 mfsdram(sdram_reg, sdram_data);
2962 printf(" SDRAM_INITPLR8 = 0x%08X", sdram_data);
2963 sdram_reg = SDRAM_INITPLR9;
2964 mfsdram(sdram_reg, sdram_data);
2965 printf(" SDRAM_INITPLR9 = 0x%08X\n", sdram_data);
2966 sdram_reg = SDRAM_INITPLR10;
2967 mfsdram(sdram_reg, sdram_data);
2968 printf(" SDRAM_INITPLR10 = 0x%08X", sdram_data);
2969 sdram_reg = SDRAM_INITPLR11;
2970 mfsdram(sdram_reg, sdram_data);
2971 printf(" SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
2972 sdram_reg = SDRAM_INITPLR12;
2973 mfsdram(sdram_reg, sdram_data);
2974 printf(" SDRAM_INITPLR12 = 0x%08X", sdram_data);
2975 sdram_reg = SDRAM_INITPLR13;
2976 mfsdram(sdram_reg, sdram_data);
2977 printf(" SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
2978 sdram_reg = SDRAM_INITPLR14;
2979 mfsdram(sdram_reg, sdram_data);
2980 printf(" SDRAM_INITPLR14 = 0x%08X", sdram_data);
2981 sdram_reg = SDRAM_INITPLR15;
2982 mfsdram(sdram_reg, sdram_data);
2983 printf(" SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
2984 sdram_reg = SDRAM_RQDC;
2985 mfsdram(sdram_reg, sdram_data);
2986 printf(" SDRAM_RQDC = 0x%08X", sdram_data);
2987 sdram_reg = SDRAM_RFDC;
2988 mfsdram(sdram_reg, sdram_data);
2989 printf(" SDRAM_RFDC = 0x%08X\n", sdram_data);
2990 sdram_reg = SDRAM_RDCC;
2991 mfsdram(sdram_reg, sdram_data);
2992 printf(" SDRAM_RDCC = 0x%08X", sdram_data);
2993 sdram_reg = SDRAM_DLCR;
2994 mfsdram(sdram_reg, sdram_data);
2995 printf(" SDRAM_DLCR = 0x%08X\n", sdram_data);
2996 sdram_reg = SDRAM_CLKTR;
2997 mfsdram(sdram_reg, sdram_data);
2998 printf(" SDRAM_CLKTR = 0x%08X", sdram_data);
2999 sdram_reg = SDRAM_WRDTR;
3000 mfsdram(sdram_reg, sdram_data);
3001 printf(" SDRAM_WRDTR = 0x%08X\n", sdram_data);
3002 sdram_reg = SDRAM_SDTR1;
3003 mfsdram(sdram_reg, sdram_data);
3004 printf(" SDRAM_SDTR1 = 0x%08X", sdram_data);
3005 sdram_reg = SDRAM_SDTR2;
3006 mfsdram(sdram_reg, sdram_data);
3007 printf(" SDRAM_SDTR2 = 0x%08X\n", sdram_data);
3008 sdram_reg = SDRAM_SDTR3;
3009 mfsdram(sdram_reg, sdram_data);
3010 printf(" SDRAM_SDTR3 = 0x%08X", sdram_data);
3011 sdram_reg = SDRAM_MMODE;
3012 mfsdram(sdram_reg, sdram_data);
3013 printf(" SDRAM_MMODE = 0x%08X\n", sdram_data);
3014 sdram_reg = SDRAM_MEMODE;
3015 mfsdram(sdram_reg, sdram_data);
3016 printf(" SDRAM_MEMODE = 0x%08X", sdram_data);
3017 sdram_reg = SDRAM_ECCCR;
3018 mfsdram(sdram_reg, sdram_data);
3019 printf(" SDRAM_ECCCR = 0x%08X\n\n", sdram_data);
3020
3021 dcr_data = mfdcr(SDRAM_R0BAS);
3022 printf(" MQ0_B0BAS = 0x%08X", dcr_data);
3023 dcr_data = mfdcr(SDRAM_R1BAS);
3024 printf(" MQ1_B0BAS = 0x%08X\n", dcr_data);
3025 dcr_data = mfdcr(SDRAM_R2BAS);
3026 printf(" MQ2_B0BAS = 0x%08X", dcr_data);
3027 dcr_data = mfdcr(SDRAM_R3BAS);
3028 printf(" MQ3_B0BAS = 0x%08X\n", dcr_data);
3029}
Stefan Roese6ed14ad2007-07-16 09:57:00 +02003030#else
3031static void ppc440sp_sdram_register_dump(void)
3032{
3033}
Stefan Roese4037ed32007-02-20 10:43:34 +01003034#endif
3035#endif /* CONFIG_SPD_EEPROM */