blob: 5d424dd75f42f9aedd676e1c0eef73db085c20cc [file] [log] [blame]
wdenkc15f3122004-10-10 22:44:24 +00001/*
2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
4 *
5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
6 * Added support for Wind River SBC8540 board
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
Paul Gortmaker928435d2009-09-21 17:19:17 -040027/*
28 * sbc8540 board configuration file.
wdenkc15f3122004-10-10 22:44:24 +000029 */
wdenk8b74bf32004-10-11 23:10:30 +000030
wdenkc15f3122004-10-10 22:44:24 +000031#ifndef __CONFIG_H
32#define __CONFIG_H
33
Paul Gortmaker928435d2009-09-21 17:19:17 -040034/*
35 * Top level Makefile configuration choices
36 */
37#ifdef CONFIG_MK_66
38#define CONFIG_PCI_66
wdenkc15f3122004-10-10 22:44:24 +000039#endif
Paul Gortmaker928435d2009-09-21 17:19:17 -040040
wdenkc15f3122004-10-10 22:44:24 +000041#define TSEC_DEBUG
42
Paul Gortmaker928435d2009-09-21 17:19:17 -040043/*
44 * High Level Configuration Options
45 */
wdenkc15f3122004-10-10 22:44:24 +000046#define CONFIG_BOOKE 1 /* BOOKE */
47#define CONFIG_E500 1 /* BOOKE e500 family */
48#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
49#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
50
51
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050052#define CONFIG_CPM2 1 /* has CPM2 */
wdenkc15f3122004-10-10 22:44:24 +000053
Wolfgang Denk53677ef2008-05-20 16:00:29 +020054#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
Kumar Galaf0600542008-06-11 00:44:10 -050055#define CONFIG_MPC8540 1
wdenkc15f3122004-10-10 22:44:24 +000056
57#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
58
59#define CONFIG_TSEC_ENET /* tsec ethernet support */
60#undef CONFIG_PCI /* pci ethernet support */
61#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
62
Kumar Galae2b159d2008-01-16 09:05:27 -060063#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenkc15f3122004-10-10 22:44:24 +000064
65#define CONFIG_ENV_OVERWRITE
66
67/* Using Localbus SDRAM to emulate flash before we can program the flash,
68 * normally you need a flash-boot image(u-boot.bin), if so undef this.
69 */
70#undef CONFIG_RAM_AS_FLASH
71
72#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
73 #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
74#else
75 #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
76#endif
77
78/* below can be toggled for performance analysis. otherwise use default */
79#define CONFIG_L2_CACHE /* toggle L2 cache */
80#undef CONFIG_BTB /* toggle branch predition */
wdenkc15f3122004-10-10 22:44:24 +000081
82#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Peter Tyser004eca02009-09-16 22:03:08 -050083#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenkc15f3122004-10-10 22:44:24 +000084
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
86#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
87#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenkc15f3122004-10-10 22:44:24 +000088
89#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
90 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
91 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
92#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
93#endif
94
95/*
96 * Base addresses -- Note these are effective addresses where the
97 * actual resources get mapped (not physical addresses)
98 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
wdenkc15f3122004-10-10 22:44:24 +0000100
101#if XXX
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102 #define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
wdenkc15f3122004-10-10 22:44:24 +0000103#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104 #define CONFIG_SYS_CCSRBAR 0xff700000 /* default CCSRBAR */
wdenkc15f3122004-10-10 22:44:24 +0000105#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
107#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenkc15f3122004-10-10 22:44:24 +0000108
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
wdenkc15f3122004-10-10 22:44:24 +0000110
Kumar Gala8e553132008-08-26 23:52:58 -0500111/* DDR Setup */
112#define CONFIG_FSL_DDR1
113#undef CONFIG_FSL_DDR_INTERACTIVE
wdenkc15f3122004-10-10 22:44:24 +0000114#undef CONFIG_DDR_ECC /* only for ECC DDR module */
115#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
Kumar Gala8e553132008-08-26 23:52:58 -0500116#undef CONFIG_DDR_SPD
wdenkc15f3122004-10-10 22:44:24 +0000117
118#if defined(CONFIG_MPC85xx_REV1)
119 #define CONFIG_DDR_DLL /* possible DLL fix needed */
120#endif
121
Kumar Gala8e553132008-08-26 23:52:58 -0500122#undef CONFIG_DDR_ECC /* only for ECC DDR module */
123#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
124#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
127#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala8e553132008-08-26 23:52:58 -0500128#define CONFIG_VERY_BIG_RAM
129
130#define CONFIG_NUM_DDR_CONTROLLERS 1
131#define CONFIG_DIMM_SLOTS_PER_CTLR 1
132#define CONFIG_CHIP_SELECTS_PER_CTRL 2
133
134/* I2C addresses of SPD EEPROMs */
135#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
136
wdenkc15f3122004-10-10 22:44:24 +0000137#undef CONFIG_CLOCKS_IN_MHZ
138
139#if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140 #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
141 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
142 #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
143 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
wdenkc15f3122004-10-10 22:44:24 +0000144#else /* Boot from real Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
146 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
147 #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
148 #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
wdenkc15f3122004-10-10 22:44:24 +0000149#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenkc15f3122004-10-10 22:44:24 +0000151
152/* local bus definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
154#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
wdenkc15f3122004-10-10 22:44:24 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
157#define CONFIG_SYS_OR2_PRELIM 0x00000000
wdenkc15f3122004-10-10 22:44:24 +0000158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
160#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
wdenkc15f3122004-10-10 22:44:24 +0000161
162#if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
wdenkc15f3122004-10-10 22:44:24 +0000164#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165 #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
wdenkc15f3122004-10-10 22:44:24 +0000166#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
wdenkc15f3122004-10-10 22:44:24 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
wdenkc15f3122004-10-10 22:44:24 +0000170#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171 #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
wdenkc15f3122004-10-10 22:44:24 +0000172#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
wdenkc15f3122004-10-10 22:44:24 +0000174#endif
175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
177#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
178#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
179#define CONFIG_SYS_LBC_LBCR 0x00000000
180#define CONFIG_SYS_LBC_LSRT 0x20000000
181#define CONFIG_SYS_LBC_MRTPR 0x20000000
182#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
183#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
184#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
185#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
186#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
wdenkc15f3122004-10-10 22:44:24 +0000187
188/* just hijack the MOT BCSR def for SBC8560 misc devices */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
wdenkc15f3122004-10-10 22:44:24 +0000190/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_INIT_RAM_LOCK 1
193#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
194#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenkc15f3122004-10-10 22:44:24 +0000195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
197#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
198#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc15f3122004-10-10 22:44:24 +0000199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
201#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenkc15f3122004-10-10 22:44:24 +0000202
203/* Serial Port */
204#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
205#undef CONFIG_CONS_NONE /* define if console on something else */
206
207#define CONFIG_CONS_INDEX 1
208#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_NS16550
210#define CONFIG_SYS_NS16550_SERIAL
211#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenkc15f3122004-10-10 22:44:24 +0000212#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
wdenkc15f3122004-10-10 22:44:24 +0000214#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_NS16550_CLK 264000000 /* get_bus_freq(0) */
wdenkc15f3122004-10-10 22:44:24 +0000216#endif
217
218#define CONFIG_BAUDRATE 9600
219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_BAUDRATE_TABLE \
wdenkc15f3122004-10-10 22:44:24 +0000221 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
222
223#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
225#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
wdenkc15f3122004-10-10 22:44:24 +0000226#else
wdenk8b74bf32004-10-11 23:10:30 +0000227/* SBC8540 uses internal COMM controller */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500)
229#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600)
wdenkc15f3122004-10-10 22:44:24 +0000230#endif
231
232/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_HUSH_PARSER
234#ifdef CONFIG_SYS_HUSH_PARSER
235#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkc15f3122004-10-10 22:44:24 +0000236#endif
237
Jon Loeliger20476722006-10-20 15:50:15 -0500238/*
239 * I2C
240 */
241#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
242#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenkc15f3122004-10-10 22:44:24 +0000243#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
245#define CONFIG_SYS_I2C_SLAVE 0x7F
246#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
247#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenkc15f3122004-10-10 22:44:24 +0000248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
250#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
251#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
wdenkc15f3122004-10-10 22:44:24 +0000252
253#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
254
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500255# define CONFIG_NET_MULTI 1
256# define CONFIG_MPC85xx_TSEC1
257# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
258# define CONFIG_MII 1 /* MII PHY management */
259# define TSEC1_PHY_ADDR 25
260# define TSEC1_PHYIDX 0
261/* Options are: TSEC0 */
262# define CONFIG_ETHPRIME "TSEC0"
wdenkc15f3122004-10-10 22:44:24 +0000263
wdenk8b74bf32004-10-11 23:10:30 +0000264
wdenkc15f3122004-10-10 22:44:24 +0000265#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
266
267 #undef CONFIG_ETHER_NONE /* define if ether on something else */
268 #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
269 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
wdenk8b74bf32004-10-11 23:10:30 +0000270
wdenkc15f3122004-10-10 22:44:24 +0000271 #if (CONFIG_ETHER_INDEX == 2)
272 /*
273 * - Rx-CLK is CLK13
274 * - Tx-CLK is CLK14
275 * - Select bus for bd/buffers
276 * - Full duplex
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
279 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
280 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
281 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk8b74bf32004-10-11 23:10:30 +0000282
wdenkc15f3122004-10-10 22:44:24 +0000283 #elif (CONFIG_ETHER_INDEX == 3)
284 /* need more definitions here for FE3 */
285 #endif /* CONFIG_ETHER_INDEX */
wdenk8b74bf32004-10-11 23:10:30 +0000286
wdenkc15f3122004-10-10 22:44:24 +0000287 #define CONFIG_MII /* MII PHY management */
288 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
289 /*
290 * GPIO pins used for bit-banged MII communications
291 */
292 #define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200293 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
294 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
295 #define MDC_DECLARE MDIO_DECLARE
296
wdenkc15f3122004-10-10 22:44:24 +0000297 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
298 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
299 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
300
301 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
302 else iop->pdat &= ~0x00400000
303
304 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
305 else iop->pdat &= ~0x00200000
306
307 #define MIIDELAY udelay(1)
wdenk8b74bf32004-10-11 23:10:30 +0000308
wdenkc15f3122004-10-10 22:44:24 +0000309#endif
310
311/*-----------------------------------------------------------------------
312 * FLASH and environment organization
313 */
314
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200316#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
wdenkc15f3122004-10-10 22:44:24 +0000317#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
319#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
wdenkc15f3122004-10-10 22:44:24 +0000320#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
322#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenkc15f3122004-10-10 22:44:24 +0000323
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#undef CONFIG_SYS_FLASH_CHECKSUM
325#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
326#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
wdenkc15f3122004-10-10 22:44:24 +0000327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
wdenkc15f3122004-10-10 22:44:24 +0000329
330#if 0
331/* XXX This doesn't work and I don't want to fix it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
333 #define CONFIG_SYS_RAMBOOT
wdenkc15f3122004-10-10 22:44:24 +0000334#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335 #undef CONFIG_SYS_RAMBOOT
wdenkc15f3122004-10-10 22:44:24 +0000336#endif
337#endif
338
339/* Environment */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#if !defined(CONFIG_SYS_RAMBOOT)
wdenkc15f3122004-10-10 22:44:24 +0000341 #if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200342 #define CONFIG_ENV_IS_NOWHERE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200344 #define CONFIG_ENV_SIZE 0x2000
wdenkc15f3122004-10-10 22:44:24 +0000345 #else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200346 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200347 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200349 #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
wdenkc15f3122004-10-10 22:44:24 +0000350 #endif
351#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200353 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200355 #define CONFIG_ENV_SIZE 0x2000
wdenkc15f3122004-10-10 22:44:24 +0000356#endif
357
358#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
359/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
360#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
361#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
362
363#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc15f3122004-10-10 22:44:24 +0000365
Jon Loeliger2835e512007-06-13 13:22:08 -0500366
367/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500368 * BOOTP options
369 */
370#define CONFIG_BOOTP_BOOTFILESIZE
371#define CONFIG_BOOTP_BOOTPATH
372#define CONFIG_BOOTP_GATEWAY
373#define CONFIG_BOOTP_HOSTNAME
374
375
376/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500377 * Command line configuration.
378 */
379#include <config_cmd_default.h>
380
381#define CONFIG_CMD_PING
382#define CONFIG_CMD_I2C
Becky Bruce199e2622010-06-17 11:37:25 -0500383#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500384
385#if defined(CONFIG_PCI)
386 #define CONFIG_CMD_PCI
wdenkc15f3122004-10-10 22:44:24 +0000387#endif
388
Jon Loeliger2835e512007-06-13 13:22:08 -0500389#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
390 #define CONFIG_CMD_MII
391#endif
392
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500394 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500395 #undef CONFIG_CMD_LOADS
396#endif
397
wdenkc15f3122004-10-10 22:44:24 +0000398
399#undef CONFIG_WATCHDOG /* watchdog disabled */
400
401/*
402 * Miscellaneous configurable options
403 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_LONGHELP /* undef to save memory */
405#define CONFIG_SYS_PROMPT "SBC8540=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500406#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc15f3122004-10-10 22:44:24 +0000408#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc15f3122004-10-10 22:44:24 +0000410#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
412#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
413#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
414#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
415#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc15f3122004-10-10 22:44:24 +0000416
417/*
418 * For booting Linux, the board info and command line data
419 * have to be in the first 8 MB of memory, since this is
420 * the maximum mapped by the Linux kernel during initialization.
421 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc15f3122004-10-10 22:44:24 +0000423
wdenkc15f3122004-10-10 22:44:24 +0000424/*
425 * Internal Definitions
426 *
427 * Boot Flags
428 */
429#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
430#define BOOTFLAG_WARM 0x02 /* Software reboot */
431
Jon Loeliger2835e512007-06-13 13:22:08 -0500432#if defined(CONFIG_CMD_KGDB)
wdenkc15f3122004-10-10 22:44:24 +0000433 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
434 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
435#endif
436
437/*Note: change below for your network setting!!! */
438#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
wdenke2ffd592004-12-31 09:32:47 +0000439# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a
440# define CONFIG_HAS_ETH1
441# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b
442# define CONFIG_HAS_ETH2
443# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c
wdenkc15f3122004-10-10 22:44:24 +0000444#endif
445
446#define CONFIG_SERVERIP YourServerIP
447#define CONFIG_IPADDR YourTargetIP
448#define CONFIG_GATEWAYIP YourGatewayIP
449#define CONFIG_NETMASK 255.255.255.0
450#define CONFIG_HOSTNAME SBC8560
451#define CONFIG_ROOTPATH YourRootPath
452#define CONFIG_BOOTFILE YourImageName
453
454#endif /* __CONFIG_H */