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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simekf22651c2012-09-28 09:56:37 +00002/*
3 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
Michal Simek3e1b61d2018-01-17 07:37:47 +01004 * (C) Copyright 2013 - 2018 Xilinx, Inc.
Michal Simekf22651c2012-09-28 09:56:37 +00005 */
6
7#include <common.h>
Simon Glass52559322019-11-14 12:57:46 -07008#include <init.h>
Michal Simek62b96262020-07-28 12:45:47 +02009#include <log.h>
Michal Simeke6cc3b22018-02-21 17:04:28 +010010#include <dm/uclass.h>
Simon Glass9fb625c2019-08-01 09:46:51 -060011#include <env.h>
Michal Simek9e0e37a2014-02-24 11:16:32 +010012#include <fdtdec.h>
Michal Simek5b73caf2014-04-25 13:51:17 +020013#include <fpga.h>
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053014#include <malloc.h>
Michal Simek5b73caf2014-04-25 13:51:17 +020015#include <mmc.h>
Michal Simek0ecd14e2018-06-08 13:45:14 +020016#include <watchdog.h>
Michal Simeke6cc3b22018-02-21 17:04:28 +010017#include <wdt.h>
Michal Simekd5dae852013-04-22 15:43:02 +020018#include <zynqpl.h>
Michal Simek71936532013-04-12 16:33:08 +020019#include <asm/arch/hardware.h>
20#include <asm/arch/sys_proto.h>
Michal Simek80fdef12020-03-31 12:39:37 +020021#include "../common/board.h"
Michal Simekf22651c2012-09-28 09:56:37 +000022
23DECLARE_GLOBAL_DATA_PTR;
24
25int board_init(void)
26{
Michal Simekf22651c2012-09-28 09:56:37 +000027 return 0;
28}
29
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053030int board_late_init(void)
31{
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053032 int env_targets_len = 0;
33 const char *mode;
34 char *new_targets;
35 char *env_targets;
36
Michal Simek62b96262020-07-28 12:45:47 +020037 if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
38 debug("Saved variables - Skipping\n");
39 return 0;
40 }
41
42 if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
43 return 0;
44
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053045 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
Michal Simek085b2b82016-12-16 13:16:14 +010046 case ZYNQ_BM_QSPI:
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053047 mode = "qspi";
Simon Glass382bee52017-08-03 12:22:09 -060048 env_set("modeboot", "qspiboot");
Michal Simek085b2b82016-12-16 13:16:14 +010049 break;
50 case ZYNQ_BM_NAND:
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053051 mode = "nand";
Simon Glass382bee52017-08-03 12:22:09 -060052 env_set("modeboot", "nandboot");
Michal Simek085b2b82016-12-16 13:16:14 +010053 break;
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053054 case ZYNQ_BM_NOR:
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053055 mode = "nor";
Simon Glass382bee52017-08-03 12:22:09 -060056 env_set("modeboot", "norboot");
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053057 break;
58 case ZYNQ_BM_SD:
Michal Simek7712fb12019-09-11 12:51:49 +020059 mode = "mmc0";
Simon Glass382bee52017-08-03 12:22:09 -060060 env_set("modeboot", "sdboot");
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053061 break;
62 case ZYNQ_BM_JTAG:
T Karthik Reddyc352f1e2019-11-13 21:13:44 -070063 mode = "jtag pxe dhcp";
Simon Glass382bee52017-08-03 12:22:09 -060064 env_set("modeboot", "jtagboot");
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053065 break;
66 default:
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053067 mode = "";
Simon Glass382bee52017-08-03 12:22:09 -060068 env_set("modeboot", "");
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053069 break;
70 }
71
Siva Durga Prasad Paladugu3c7b4c32019-01-25 17:06:06 +053072 /*
73 * One terminating char + one byte for space between mode
74 * and default boot_targets
75 */
76 env_targets = env_get("boot_targets");
77 if (env_targets)
78 env_targets_len = strlen(env_targets);
79
80 new_targets = calloc(1, strlen(mode) + env_targets_len + 2);
81 if (!new_targets)
82 return -ENOMEM;
83
84 sprintf(new_targets, "%s %s", mode,
85 env_targets ? env_targets : "");
86
87 env_set("boot_targets", new_targets);
88
Michal Simek80fdef12020-03-31 12:39:37 +020089 return board_late_init_xilinx();
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053090}
Michal Simekf22651c2012-09-28 09:56:37 +000091
Michal Simek758f29d2016-04-01 15:56:33 +020092#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
Simon Glass76b00ac2017-03-31 08:40:32 -060093int dram_init_banksize(void)
Tom Rini361a8792016-12-09 07:56:54 -050094{
Michal Simekda3f0032017-11-03 15:25:51 +010095 return fdtdec_setup_memory_banksize();
Michal Simek758f29d2016-04-01 15:56:33 +020096}
97
Michal Simek8a5db0a2016-12-06 16:31:53 +010098int dram_init(void)
99{
Siva Durga Prasad Paladugu12308b12018-07-16 15:56:11 +0530100 if (fdtdec_setup_mem_size_base() != 0)
Nathan Rosside9bf1b2016-12-19 00:03:34 +1000101 return -EINVAL;
Michal Simek8a5db0a2016-12-06 16:31:53 +0100102
103 zynq_ddrc_init();
104
105 return 0;
106}
Michal Simek758f29d2016-04-01 15:56:33 +0200107#else
108int dram_init(void)
109{
Michal Simek61dc92a2018-04-11 16:12:28 +0200110 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
111 CONFIG_SYS_SDRAM_SIZE);
Michal Simek758f29d2016-04-01 15:56:33 +0200112
113 zynq_ddrc_init();
114
115 return 0;
116}
117#endif