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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
10#include <common.h>
11#include <command.h>
wdenk8bde7f72003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +053013#include <fs.h>
wdenkc3d2b4b2005-01-22 18:13:04 +000014#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000015
Michal Simekf4c7a4a2018-06-04 14:57:34 +020016static long do_fpga_get_device(char *arg)
17{
18 long dev = FPGA_INVALID_DEVICE;
19 char *devstr = env_get("fpga");
20
21 if (devstr)
22 /* Should be strtol to handle -1 cases */
23 dev = simple_strtol(devstr, NULL, 16);
24
Michal Simek8c75f792018-07-26 15:33:51 +020025 if (dev == FPGA_INVALID_DEVICE && arg)
Michal Simekf4c7a4a2018-06-04 14:57:34 +020026 dev = simple_strtol(arg, NULL, 16);
27
28 debug("%s: device = %ld\n", __func__, dev);
29
30 return dev;
31}
32
Michal Simek85754792018-06-04 15:51:23 +020033static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size,
34 cmd_tbl_t *cmdtp, int argc, char *const argv[])
35{
36 size_t local_data_size;
37 long local_fpga_data;
38
39 debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs);
40
41 if (argc != cmdtp->maxargs) {
42 debug("fpga: incorrect parameters passed\n");
43 return CMD_RET_USAGE;
44 }
45
46 *dev = do_fpga_get_device(argv[0]);
47
48 local_fpga_data = simple_strtol(argv[1], NULL, 16);
49 if (!local_fpga_data) {
50 debug("fpga: zero fpga_data address\n");
51 return CMD_RET_USAGE;
52 }
53 *fpga_data = local_fpga_data;
54
55 local_data_size = simple_strtoul(argv[2], NULL, 16);
56 if (!local_data_size) {
57 debug("fpga: zero size\n");
58 return CMD_RET_USAGE;
59 }
60 *data_size = local_data_size;
61
62 return 0;
63}
64
wdenk4a9cbbe2002-08-27 09:48:53 +000065/* Local defines */
Michal Simek5cf22282017-01-06 11:20:54 +010066enum {
67 FPGA_NONE = -1,
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +053068 FPGA_LOADS,
Michal Simek5cf22282017-01-06 11:20:54 +010069};
wdenk4a9cbbe2002-08-27 09:48:53 +000070
Michal Simek323fe382018-05-30 10:00:40 +020071/*
72 * Map op to supported operations. We don't use a table since we
73 * would just have to relocate it from flash anyway.
74 */
75static int fpga_get_op(char *opstr)
76{
77 int op = FPGA_NONE;
78
Michal Simek323fe382018-05-30 10:00:40 +020079#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek2892fe82018-06-04 16:15:58 +020080 if (!strcmp("loads", opstr))
Michal Simek323fe382018-05-30 10:00:40 +020081 op = FPGA_LOADS;
82#endif
83
84 return op;
85}
86
wdenk4a9cbbe2002-08-27 09:48:53 +000087/* ------------------------------------------------------------------------- */
88/* command form:
89 * fpga <op> <device number> <data addr> <datasize>
90 * where op is 'load', 'dump', or 'info'
91 * If there is no device number field, the fpga environment variable is used.
92 * If there is no data addr field, the fpgadata environment variable is used.
93 * The info command requires no data address field.
94 */
Michal Simekfc598412013-04-26 13:10:07 +020095int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000096{
wdenkd4ca31c2004-01-02 14:00:00 +000097 int op, dev = FPGA_INVALID_DEVICE;
98 size_t data_size = 0;
99 void *fpga_data = NULL;
wdenkd4ca31c2004-01-02 14:00:00 +0000100 int rc = FPGA_FAIL;
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530101#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
102 struct fpga_secure_info fpga_sec_info;
103
104 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
105#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000106
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530107 if (argc > 9 || argc < 2) {
108 debug("%s: Too many or too few args (%d)\n", __func__, argc);
109 return CMD_RET_USAGE;
110 }
111
Michal Simek323fe382018-05-30 10:00:40 +0200112 op = fpga_get_op(argv[1]);
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530113
114 switch (op) {
Michal Simek55010962018-05-30 09:57:42 +0200115 case FPGA_NONE:
116 printf("Unknown fpga operation \"%s\"\n", argv[1]);
117 return CMD_RET_USAGE;
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530118#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
119 case FPGA_LOADS:
120 if (argc < 7)
121 return CMD_RET_USAGE;
122 if (argc == 8)
123 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
124 simple_strtoull(argv[7],
125 NULL, 16);
126 fpga_sec_info.encflag = (u8)simple_strtoul(argv[6], NULL, 16);
127 fpga_sec_info.authflag = (u8)simple_strtoul(argv[5], NULL, 16);
Michal Simek44d839b2018-05-30 11:18:38 +0200128
129 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
130 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
131 puts("ERR: Use <fpga load> for NonSecure bitstream\n");
132 return CMD_RET_USAGE;
133 }
134
135 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
136 !fpga_sec_info.userkey_addr) {
137 puts("ERR: User key not provided\n");
138 return CMD_RET_USAGE;
139 }
140
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530141 argc = 5;
142 break;
143#endif
Siva Durga Prasad Paladuguf5953612018-05-31 15:10:21 +0530144 default:
145 break;
146 }
147
148 switch (argc) {
wdenkd4ca31c2004-01-02 14:00:00 +0000149 case 5: /* fpga <op> <dev> <data> <datasize> */
Michal Simekfc598412013-04-26 13:10:07 +0200150 data_size = simple_strtoul(argv[4], NULL, 16);
Michal Simek5cadab62018-05-30 11:28:57 +0200151 if (!data_size) {
152 puts("Zero data_size\n");
153 return CMD_RET_USAGE;
154 }
wdenkd4ca31c2004-01-02 14:00:00 +0000155 case 4: /* fpga <op> <dev> <data> */
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100156 {
Michal Simekfc598412013-04-26 13:10:07 +0200157 fpga_data = (void *)simple_strtoul(argv[3], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000158 debug("* fpga: cmdline image address = 0x%08lx\n",
Michal Simekfc598412013-04-26 13:10:07 +0200159 (ulong)fpga_data);
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100160 }
Michal Simek455ad582016-01-05 13:51:48 +0100161 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
Michal Simek5cadab62018-05-30 11:28:57 +0200162 if (!fpga_data) {
163 puts("Zero fpga_data address\n");
164 return CMD_RET_USAGE;
165 }
wdenkd4ca31c2004-01-02 14:00:00 +0000166 case 3: /* fpga <op> <dev | data addr> */
Michal Simekfc598412013-04-26 13:10:07 +0200167 dev = (int)simple_strtoul(argv[2], NULL, 16);
Stefano Babic06297db2011-12-28 06:47:01 +0000168 debug("%s: device = %d\n", __func__, dev);
wdenkd4ca31c2004-01-02 14:00:00 +0000169 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000170
Stefano Babica790b5b2010-10-19 09:22:52 +0200171 if (dev == FPGA_INVALID_DEVICE) {
172 puts("FPGA device not specified\n");
Michal Simekccd65202018-05-30 10:04:34 +0200173 return CMD_RET_USAGE;
Stefano Babica790b5b2010-10-19 09:22:52 +0200174 }
175
176 switch (op) {
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530177#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
178 case FPGA_LOADS:
179 rc = fpga_loads(dev, fpga_data, data_size, &fpga_sec_info);
180 break;
181#endif
Stefan Roesef0ff4692006-08-15 14:15:51 +0200182
wdenkd4ca31c2004-01-02 14:00:00 +0000183 default:
Michal Simekfc598412013-04-26 13:10:07 +0200184 printf("Unknown operation\n");
Simon Glass4c12eeb2011-12-10 08:44:01 +0000185 return CMD_RET_USAGE;
wdenkd4ca31c2004-01-02 14:00:00 +0000186 }
Michal Simekfc598412013-04-26 13:10:07 +0200187 return rc;
wdenk4a9cbbe2002-08-27 09:48:53 +0000188}
189
Michal Simek49503f92018-06-04 15:51:16 +0200190#if defined(CONFIG_CMD_FPGA_LOADFS)
191static int do_fpga_loadfs(cmd_tbl_t *cmdtp, int flag, int argc,
192 char *const argv[])
193{
194 size_t data_size = 0;
195 long fpga_data, dev;
196 int ret;
197 fpga_fs_info fpga_fsinfo;
198
199 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
200 cmdtp, argc, argv);
201 if (ret)
202 return ret;
203
204 fpga_fsinfo.fstype = FS_TYPE_ANY;
205 fpga_fsinfo.blocksize = (unsigned int)simple_strtoul(argv[3], NULL, 16);
206 fpga_fsinfo.interface = argv[4];
207 fpga_fsinfo.dev_part = argv[5];
208 fpga_fsinfo.filename = argv[6];
209
210 return fpga_fsload(dev, (void *)fpga_data, data_size, &fpga_fsinfo);
211}
212#endif
213
Michal Simekf4c7a4a2018-06-04 14:57:34 +0200214static int do_fpga_info(cmd_tbl_t *cmdtp, int flag, int argc,
215 char * const argv[])
216{
217 long dev = do_fpga_get_device(argv[0]);
218
219 return fpga_info(dev);
220}
221
Michal Simek85754792018-06-04 15:51:23 +0200222static int do_fpga_dump(cmd_tbl_t *cmdtp, int flag, int argc,
223 char * const argv[])
224{
225 size_t data_size = 0;
226 long fpga_data, dev;
227 int ret;
228
229 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
230 cmdtp, argc, argv);
231 if (ret)
232 return ret;
233
234 return fpga_dump(dev, (void *)fpga_data, data_size);
235}
236
237static int do_fpga_load(cmd_tbl_t *cmdtp, int flag, int argc,
238 char * const argv[])
239{
240 size_t data_size = 0;
241 long fpga_data, dev;
242 int ret;
243
244 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
245 cmdtp, argc, argv);
246 if (ret)
247 return ret;
248
249 return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL);
250}
251
252static int do_fpga_loadb(cmd_tbl_t *cmdtp, int flag, int argc,
253 char * const argv[])
254{
255 size_t data_size = 0;
256 long fpga_data, dev;
257 int ret;
258
259 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
260 cmdtp, argc, argv);
261 if (ret)
262 return ret;
263
264 return fpga_loadbitstream(dev, (void *)fpga_data, data_size, BIT_FULL);
265}
266
267#if defined(CONFIG_CMD_FPGA_LOADP)
268static int do_fpga_loadp(cmd_tbl_t *cmdtp, int flag, int argc,
269 char * const argv[])
270{
271 size_t data_size = 0;
272 long fpga_data, dev;
273 int ret;
274
275 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
276 cmdtp, argc, argv);
277 if (ret)
278 return ret;
279
280 return fpga_load(dev, (void *)fpga_data, data_size, BIT_PARTIAL);
281}
282#endif
283
284#if defined(CONFIG_CMD_FPGA_LOADBP)
285static int do_fpga_loadbp(cmd_tbl_t *cmdtp, int flag, int argc,
286 char * const argv[])
287{
288 size_t data_size = 0;
289 long fpga_data, dev;
290 int ret;
291
292 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
293 cmdtp, argc, argv);
294 if (ret)
295 return ret;
296
297 return fpga_loadbitstream(dev, (void *)fpga_data, data_size,
298 BIT_PARTIAL);
299}
300#endif
301
Michal Simek2892fe82018-06-04 16:15:58 +0200302#if defined(CONFIG_CMD_FPGA_LOADMK)
303static int do_fpga_loadmk(cmd_tbl_t *cmdtp, int flag, int argc,
304 char * const argv[])
305{
306 size_t data_size = 0;
307 void *fpga_data = NULL;
308#if defined(CONFIG_FIT)
309 const char *fit_uname = NULL;
310 ulong fit_addr;
311#endif
312 ulong dev = do_fpga_get_device(argv[0]);
313 char *datastr = env_get("fpgadata");
314
Michal Simek8c75f792018-07-26 15:33:51 +0200315 debug("fpga: argc %x, dev %lx, datastr %s\n", argc, dev, datastr);
316
317 if (dev == FPGA_INVALID_DEVICE) {
318 debug("fpga: Invalid fpga device\n");
319 return CMD_RET_USAGE;
320 }
321
322 if (argc == 0 && !datastr) {
323 debug("fpga: No datastr passed\n");
324 return CMD_RET_USAGE;
325 }
Michal Simek2892fe82018-06-04 16:15:58 +0200326
327 if (argc == 2) {
Michal Simek8c75f792018-07-26 15:33:51 +0200328 datastr = argv[1];
329 debug("fpga: Full command with two args\n");
330 } else if (argc == 1 && !datastr) {
331 debug("fpga: Dev is setup - fpgadata passed\n");
332 datastr = argv[0];
333 }
334
Michal Simek2892fe82018-06-04 16:15:58 +0200335#if defined(CONFIG_FIT)
Michal Simek8c75f792018-07-26 15:33:51 +0200336 if (fit_parse_subimage(datastr, (ulong)fpga_data,
337 &fit_addr, &fit_uname)) {
338 fpga_data = (void *)fit_addr;
339 debug("* fpga: subimage '%s' from FIT image ",
340 fit_uname);
341 debug("at 0x%08lx\n", fit_addr);
342 } else
Michal Simek2892fe82018-06-04 16:15:58 +0200343#endif
Michal Simek8c75f792018-07-26 15:33:51 +0200344 {
345 fpga_data = (void *)simple_strtoul(datastr, NULL, 16);
346 debug("* fpga: cmdline image address = 0x%08lx\n",
347 (ulong)fpga_data);
348 }
349 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
350 if (!fpga_data) {
351 puts("Zero fpga_data address\n");
352 return CMD_RET_USAGE;
Michal Simek2892fe82018-06-04 16:15:58 +0200353 }
354
355 switch (genimg_get_format(fpga_data)) {
356#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
357 case IMAGE_FORMAT_LEGACY:
358 {
359 image_header_t *hdr = (image_header_t *)fpga_data;
360 ulong data;
361 u8 comp;
362
363 comp = image_get_comp(hdr);
364 if (comp == IH_COMP_GZIP) {
365#if defined(CONFIG_GZIP)
366 ulong image_buf = image_get_data(hdr);
367 ulong image_size = ~0UL;
368
369 data = image_get_load(hdr);
370
371 if (gunzip((void *)data, ~0UL, (void *)image_buf,
372 &image_size) != 0) {
373 puts("GUNZIP: error\n");
374 return 1;
375 }
376 data_size = image_size;
377#else
378 puts("Gunzip image is not supported\n");
379 return 1;
380#endif
381 } else {
382 data = (ulong)image_get_data(hdr);
383 data_size = image_get_data_size(hdr);
384 }
385 return fpga_load(dev, (void *)data, data_size,
386 BIT_FULL);
387 }
388#endif
389#if defined(CONFIG_FIT)
390 case IMAGE_FORMAT_FIT:
391 {
392 const void *fit_hdr = (const void *)fpga_data;
393 int noffset;
394 const void *fit_data;
395
396 if (!fit_uname) {
397 puts("No FIT subimage unit name\n");
398 return 1;
399 }
400
401 if (!fit_check_format(fit_hdr)) {
402 puts("Bad FIT image format\n");
403 return 1;
404 }
405
406 /* get fpga component image node offset */
407 noffset = fit_image_get_node(fit_hdr, fit_uname);
408 if (noffset < 0) {
409 printf("Can't find '%s' FIT subimage\n", fit_uname);
410 return 1;
411 }
412
413 /* verify integrity */
414 if (!fit_image_verify(fit_hdr, noffset)) {
415 puts("Bad Data Hash\n");
416 return 1;
417 }
418
419 /* get fpga subimage data address and length */
420 if (fit_image_get_data(fit_hdr, noffset, &fit_data,
421 &data_size)) {
422 puts("Fpga subimage data not found\n");
423 return 1;
424 }
425
426 return fpga_load(dev, fit_data, data_size, BIT_FULL);
427 }
428#endif
429 default:
430 puts("** Unknown image type\n");
431 return FPGA_FAIL;
432 }
433}
434#endif
435
Michal Simek9657d972018-06-04 14:55:20 +0200436static cmd_tbl_t fpga_commands[] = {
Michal Simekf4c7a4a2018-06-04 14:57:34 +0200437 U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""),
Michal Simek85754792018-06-04 15:51:23 +0200438 U_BOOT_CMD_MKENT(dump, 3, 1, do_fpga_dump, "", ""),
439 U_BOOT_CMD_MKENT(load, 3, 1, do_fpga_load, "", ""),
440 U_BOOT_CMD_MKENT(loadb, 3, 1, do_fpga_loadb, "", ""),
441#if defined(CONFIG_CMD_FPGA_LOADP)
442 U_BOOT_CMD_MKENT(loadp, 3, 1, do_fpga_loadp, "", ""),
443#endif
444#if defined(CONFIG_CMD_FPGA_LOADBP)
445 U_BOOT_CMD_MKENT(loadbp, 3, 1, do_fpga_loadbp, "", ""),
446#endif
Michal Simek49503f92018-06-04 15:51:16 +0200447#if defined(CONFIG_CMD_FPGA_LOADFS)
448 U_BOOT_CMD_MKENT(loadfs, 7, 1, do_fpga_loadfs, "", ""),
449#endif
Michal Simek2892fe82018-06-04 16:15:58 +0200450#if defined(CONFIG_CMD_FPGA_LOADMK)
451 U_BOOT_CMD_MKENT(loadmk, 2, 1, do_fpga_loadmk, "", ""),
452#endif
Michal Simek9657d972018-06-04 14:55:20 +0200453};
454
455static int do_fpga_wrapper(cmd_tbl_t *cmdtp, int flag, int argc,
456 char *const argv[])
457{
458 cmd_tbl_t *fpga_cmd;
459 int ret;
460
461 if (argc < 2)
462 return CMD_RET_USAGE;
463
464 fpga_cmd = find_cmd_tbl(argv[1], fpga_commands,
465 ARRAY_SIZE(fpga_commands));
466
467 /* This should be removed when all functions are converted */
468 if (!fpga_cmd)
469 return do_fpga(cmdtp, flag, argc, argv);
470
471 /* FIXME This can't be reached till all functions are converted */
472 if (!fpga_cmd) {
473 debug("fpga: non existing command\n");
474 return CMD_RET_USAGE;
475 }
476
477 argc -= 2;
478 argv += 2;
479
480 if (argc > fpga_cmd->maxargs) {
481 debug("fpga: more parameters passed\n");
482 return CMD_RET_USAGE;
483 }
484
485 ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv);
486
487 return cmd_process_error(fpga_cmd, ret);
488}
489
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530490#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek9657d972018-06-04 14:55:20 +0200491U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530492#else
Michal Simek9657d972018-06-04 14:55:20 +0200493U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530494#endif
Michal Simekfc598412013-04-26 13:10:07 +0200495 "loadable FPGA image support",
496 "[operation type] [device number] [image address] [image size]\n"
497 "fpga operations:\n"
Michal Simek2d73f0d2015-01-26 08:52:27 +0100498 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simekfc598412013-04-26 13:10:07 +0200499 " info\t[dev]\t\t\tlist known device information\n"
500 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek67193862014-05-02 13:43:39 +0200501#if defined(CONFIG_CMD_FPGA_LOADP)
502 " loadp\t[dev] [address] [size]\t"
503 "Load device from memory buffer with partial bitstream\n"
504#endif
Michal Simekfc598412013-04-26 13:10:07 +0200505 " loadb\t[dev] [address] [size]\t"
506 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek67193862014-05-02 13:43:39 +0200507#if defined(CONFIG_CMD_FPGA_LOADBP)
508 " loadbp\t[dev] [address] [size]\t"
509 "Load device from bitstream buffer with partial bitstream"
510 "(Xilinx only)\n"
511#endif
Siva Durga Prasad Paladugu1a897662014-03-14 16:35:37 +0530512#if defined(CONFIG_CMD_FPGA_LOADFS)
513 "Load device from filesystem (FAT by default) (Xilinx only)\n"
514 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
515 " [<dev[:part]>] <filename>\n"
516#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530517#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simekfc598412013-04-26 13:10:07 +0200518 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100519#if defined(CONFIG_FIT)
Michal Simekfc598412013-04-26 13:10:07 +0200520 "\n"
521 "\tFor loadmk operating on FIT format uImage address must include\n"
522 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100523#endif
Siva Durga Prasad Paladugu64e809a2014-03-14 16:35:38 +0530524#endif
Siva Durga Prasad Paladugucedd48e2018-05-31 15:10:22 +0530525#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
526 "Load encrypted bitstream (Xilinx only)\n"
527 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
528 " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n"
529 "Loads the secure bistreams(authenticated/encrypted/both\n"
530 "authenticated and encrypted) of [size] from [address].\n"
531 "The auth-OCM/DDR flag specifies to perform authentication\n"
532 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
533 "The enc flag specifies which key to be used for decryption\n"
534 "0-device key, 1-user key, 2-no encryption.\n"
535 "The optional Userkey address specifies from which address key\n"
536 "has to be used for decryption if user key is selected.\n"
537 "NOTE: the sceure bitstream has to be created using xilinx\n"
538 "bootgen tool only.\n"
539#endif
Marian Balakowiczc28c4d12008-03-12 10:33:01 +0100540);