Jean-Christophe PLAGNIOL-VILLARD | b3acb6c | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Jean-Christophe PLAGNIOL-VILLARD | b3acb6c | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
| 9 | #include <asm/system.h> |
R Sricharan | 96fdbec | 2013-03-04 20:04:44 +0000 | [diff] [blame] | 10 | #include <asm/cache.h> |
| 11 | #include <linux/compiler.h> |
Jean-Christophe PLAGNIOL-VILLARD | b3acb6c | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 12 | |
Aneesh V | e47f2db | 2011-06-16 23:30:48 +0000 | [diff] [blame] | 13 | #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 14 | |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
Jeroen Hofstee | fcfddfd | 2014-06-23 22:07:04 +0200 | [diff] [blame] | 17 | __weak void arm_init_before_mmu(void) |
Aneesh V | c2dd0d4 | 2011-06-16 23:30:49 +0000 | [diff] [blame] | 18 | { |
| 19 | } |
Aneesh V | c2dd0d4 | 2011-06-16 23:30:49 +0000 | [diff] [blame] | 20 | |
R Sricharan | de63ac2 | 2013-03-04 20:04:45 +0000 | [diff] [blame] | 21 | __weak void arm_init_domains(void) |
| 22 | { |
| 23 | } |
| 24 | |
Jean-Christophe PLAGNIOL-VILLARD | b3acb6c | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 25 | static void cp_delay (void) |
| 26 | { |
| 27 | volatile int i; |
| 28 | |
| 29 | /* copro seems to need some delay between reading and writing */ |
| 30 | for (i = 0; i < 100; i++) |
| 31 | nop(); |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 32 | asm volatile("" : : : "memory"); |
| 33 | } |
| 34 | |
Simon Glass | 0dde7f5 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 35 | void set_section_dcache(int section, enum dcache_option option) |
Heiko Schocher | f1d2b31 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 36 | { |
Simon Glass | 34fd5d2 | 2012-12-13 20:48:39 +0000 | [diff] [blame] | 37 | u32 *page_table = (u32 *)gd->arch.tlb_addr; |
Simon Glass | 0dde7f5 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 38 | u32 value; |
| 39 | |
| 40 | value = (section << MMU_SECTION_SHIFT) | (3 << 10); |
| 41 | value |= option; |
| 42 | page_table[section] = value; |
| 43 | } |
| 44 | |
Jeroen Hofstee | fcfddfd | 2014-06-23 22:07:04 +0200 | [diff] [blame] | 45 | __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) |
Simon Glass | 0dde7f5 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 46 | { |
| 47 | debug("%s: Warning: not implemented\n", __func__); |
| 48 | } |
| 49 | |
Thierry Reding | 25026fa | 2014-08-26 17:34:21 +0200 | [diff] [blame] | 50 | void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, |
Simon Glass | 0dde7f5 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 51 | enum dcache_option option) |
| 52 | { |
Simon Glass | 34fd5d2 | 2012-12-13 20:48:39 +0000 | [diff] [blame] | 53 | u32 *page_table = (u32 *)gd->arch.tlb_addr; |
Thierry Reding | 25026fa | 2014-08-26 17:34:21 +0200 | [diff] [blame] | 54 | unsigned long upto, end; |
Simon Glass | 0dde7f5 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 55 | |
| 56 | end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; |
| 57 | start = start >> MMU_SECTION_SHIFT; |
Thierry Reding | 25026fa | 2014-08-26 17:34:21 +0200 | [diff] [blame] | 58 | debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size, |
Simon Glass | 0dde7f5 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 59 | option); |
| 60 | for (upto = start; upto < end; upto++) |
| 61 | set_section_dcache(upto, option); |
| 62 | mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); |
| 63 | } |
| 64 | |
R Sricharan | 96fdbec | 2013-03-04 20:04:44 +0000 | [diff] [blame] | 65 | __weak void dram_bank_mmu_setup(int bank) |
Simon Glass | 0dde7f5 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 66 | { |
Heiko Schocher | f1d2b31 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 67 | bd_t *bd = gd->bd; |
| 68 | int i; |
| 69 | |
| 70 | debug("%s: bank: %d\n", __func__, bank); |
| 71 | for (i = bd->bi_dram[bank].start >> 20; |
Marek Vasut | 221a49d | 2014-08-04 01:45:46 +0200 | [diff] [blame] | 72 | i < (bd->bi_dram[bank].start >> 20) + (bd->bi_dram[bank].size >> 20); |
Heiko Schocher | f1d2b31 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 73 | i++) { |
Simon Glass | 0dde7f5 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 74 | #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |
| 75 | set_section_dcache(i, DCACHE_WRITETHROUGH); |
Marek Vasut | ff7e970 | 2014-09-15 02:44:36 +0200 | [diff] [blame] | 76 | #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) |
| 77 | set_section_dcache(i, DCACHE_WRITEALLOC); |
Simon Glass | 0dde7f5 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 78 | #else |
| 79 | set_section_dcache(i, DCACHE_WRITEBACK); |
| 80 | #endif |
Heiko Schocher | f1d2b31 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 81 | } |
| 82 | } |
Heiko Schocher | f1d2b31 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 83 | |
| 84 | /* to activate the MMU we need to set up virtual memory: use 1M areas */ |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 85 | static inline void mmu_setup(void) |
| 86 | { |
Heiko Schocher | f1d2b31 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 87 | int i; |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 88 | u32 reg; |
| 89 | |
Aneesh V | c2dd0d4 | 2011-06-16 23:30:49 +0000 | [diff] [blame] | 90 | arm_init_before_mmu(); |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 91 | /* Set up an identity-mapping for all 4GB, rw for everyone */ |
| 92 | for (i = 0; i < 4096; i++) |
Simon Glass | 0dde7f5 | 2012-10-17 13:24:53 +0000 | [diff] [blame] | 93 | set_section_dcache(i, DCACHE_OFF); |
Heiko Schocher | f1d2b31 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 94 | |
Heiko Schocher | f1d2b31 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 95 | for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
| 96 | dram_bank_mmu_setup(i); |
| 97 | } |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 98 | |
Marek Vasut | a592e6f | 2015-12-29 19:44:01 +0100 | [diff] [blame^] | 99 | #ifdef CONFIG_CPU_V7 |
Bryan Brinsko | 97840b5 | 2015-03-24 11:25:12 -0500 | [diff] [blame] | 100 | /* Set TTBR0 */ |
| 101 | reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK; |
| 102 | #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) |
| 103 | reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT; |
| 104 | #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) |
| 105 | reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA; |
| 106 | #else |
| 107 | reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB; |
| 108 | #endif |
| 109 | asm volatile("mcr p15, 0, %0, c2, c0, 0" |
| 110 | : : "r" (reg) : "memory"); |
| 111 | #else |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 112 | /* Copy the page table address to cp15 */ |
| 113 | asm volatile("mcr p15, 0, %0, c2, c0, 0" |
Simon Glass | 34fd5d2 | 2012-12-13 20:48:39 +0000 | [diff] [blame] | 114 | : : "r" (gd->arch.tlb_addr) : "memory"); |
Bryan Brinsko | 97840b5 | 2015-03-24 11:25:12 -0500 | [diff] [blame] | 115 | #endif |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 116 | /* Set the access control to all-supervisor */ |
| 117 | asm volatile("mcr p15, 0, %0, c3, c0, 0" |
| 118 | : : "r" (~0)); |
R Sricharan | de63ac2 | 2013-03-04 20:04:45 +0000 | [diff] [blame] | 119 | |
| 120 | arm_init_domains(); |
| 121 | |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 122 | /* and enable the mmu */ |
| 123 | reg = get_cr(); /* get control reg. */ |
| 124 | cp_delay(); |
| 125 | set_cr(reg | CR_M); |
Jean-Christophe PLAGNIOL-VILLARD | b3acb6c | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 126 | } |
| 127 | |
Aneesh V | e05f007 | 2011-06-16 23:30:50 +0000 | [diff] [blame] | 128 | static int mmu_enabled(void) |
| 129 | { |
| 130 | return get_cr() & CR_M; |
| 131 | } |
| 132 | |
Jean-Christophe PLAGNIOL-VILLARD | b3acb6c | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 133 | /* cache_bit must be either CR_I or CR_C */ |
| 134 | static void cache_enable(uint32_t cache_bit) |
| 135 | { |
| 136 | uint32_t reg; |
| 137 | |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 138 | /* The data cache is not active unless the mmu is enabled too */ |
Aneesh V | e05f007 | 2011-06-16 23:30:50 +0000 | [diff] [blame] | 139 | if ((cache_bit == CR_C) && !mmu_enabled()) |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 140 | mmu_setup(); |
Jean-Christophe PLAGNIOL-VILLARD | b3acb6c | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 141 | reg = get_cr(); /* get control reg. */ |
| 142 | cp_delay(); |
| 143 | set_cr(reg | cache_bit); |
| 144 | } |
| 145 | |
| 146 | /* cache_bit must be either CR_I or CR_C */ |
| 147 | static void cache_disable(uint32_t cache_bit) |
| 148 | { |
| 149 | uint32_t reg; |
| 150 | |
SRICHARAN R | d702b08 | 2012-05-16 23:52:54 +0000 | [diff] [blame] | 151 | reg = get_cr(); |
| 152 | cp_delay(); |
| 153 | |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 154 | if (cache_bit == CR_C) { |
Heiko Schocher | f1d2b31 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 155 | /* if cache isn;t enabled no need to disable */ |
Heiko Schocher | f1d2b31 | 2010-09-17 13:10:39 +0200 | [diff] [blame] | 156 | if ((reg & CR_C) != CR_C) |
| 157 | return; |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 158 | /* if disabling data cache, disable mmu too */ |
| 159 | cache_bit |= CR_M; |
Heiko Schocher | 880eff5 | 2010-09-17 13:10:29 +0200 | [diff] [blame] | 160 | } |
Arun Mankuzhi | 44df5e8 | 2012-11-30 13:01:14 +0000 | [diff] [blame] | 161 | reg = get_cr(); |
| 162 | cp_delay(); |
| 163 | if (cache_bit == (CR_C | CR_M)) |
| 164 | flush_dcache_all(); |
Jean-Christophe PLAGNIOL-VILLARD | b3acb6c | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 165 | set_cr(reg & ~cache_bit); |
| 166 | } |
| 167 | #endif |
| 168 | |
Aneesh V | e47f2db | 2011-06-16 23:30:48 +0000 | [diff] [blame] | 169 | #ifdef CONFIG_SYS_ICACHE_OFF |
Jean-Christophe PLAGNIOL-VILLARD | b3acb6c | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 170 | void icache_enable (void) |
| 171 | { |
| 172 | return; |
| 173 | } |
| 174 | |
| 175 | void icache_disable (void) |
| 176 | { |
| 177 | return; |
| 178 | } |
| 179 | |
| 180 | int icache_status (void) |
| 181 | { |
| 182 | return 0; /* always off */ |
| 183 | } |
| 184 | #else |
| 185 | void icache_enable(void) |
| 186 | { |
| 187 | cache_enable(CR_I); |
| 188 | } |
| 189 | |
| 190 | void icache_disable(void) |
| 191 | { |
| 192 | cache_disable(CR_I); |
| 193 | } |
| 194 | |
| 195 | int icache_status(void) |
| 196 | { |
| 197 | return (get_cr() & CR_I) != 0; |
| 198 | } |
| 199 | #endif |
| 200 | |
Aneesh V | e47f2db | 2011-06-16 23:30:48 +0000 | [diff] [blame] | 201 | #ifdef CONFIG_SYS_DCACHE_OFF |
Jean-Christophe PLAGNIOL-VILLARD | b3acb6c | 2009-04-05 13:06:31 +0200 | [diff] [blame] | 202 | void dcache_enable (void) |
| 203 | { |
| 204 | return; |
| 205 | } |
| 206 | |
| 207 | void dcache_disable (void) |
| 208 | { |
| 209 | return; |
| 210 | } |
| 211 | |
| 212 | int dcache_status (void) |
| 213 | { |
| 214 | return 0; /* always off */ |
| 215 | } |
| 216 | #else |
| 217 | void dcache_enable(void) |
| 218 | { |
| 219 | cache_enable(CR_C); |
| 220 | } |
| 221 | |
| 222 | void dcache_disable(void) |
| 223 | { |
| 224 | cache_disable(CR_C); |
| 225 | } |
| 226 | |
| 227 | int dcache_status(void) |
| 228 | { |
| 229 | return (get_cr() & CR_C) != 0; |
| 230 | } |
| 231 | #endif |