blob: f20ee79e872938cfc48117ed83b2eadabecbbb30 [file] [log] [blame]
Jon Loeliger5c9efb32006-04-27 10:15:16 -05001/*
Kumar Gala1b77ca82011-01-04 17:45:13 -06002 * Copyright 2006, 2010-2011 Freescale Semiconductor.
Jon Loeliger5c9efb32006-04-27 10:15:16 -05003 *
Jon Loeligerdebb7352006-04-26 17:58:56 -05004 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
Jon Loeligerdebb7352006-04-26 17:58:56 -05007 */
8
9/*
Jon Loeliger5c9efb32006-04-27 10:15:16 -050010 * MPC8641HPCN board configuration file
Jon Loeligerdebb7352006-04-26 17:58:56 -050011 *
12 * Make sure you change the MAC address and other network params first,
Joe Hershberger92ac5202015-05-04 14:55:14 -050013 * search for CONFIG_SERVERIP, etc. in this file.
Jon Loeligerdebb7352006-04-26 17:58:56 -050014 */
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
York Sun15672c62014-04-30 14:43:49 -070019#define CONFIG_SYS_GENERIC_BOARD
20#define CONFIG_DISPLAY_BOARDINFO
21
Jon Loeligerdebb7352006-04-26 17:58:56 -050022/* High Level Configuration Options */
Jon Loeligerdebb7352006-04-26 17:58:56 -050023#define CONFIG_MPC8641 1 /* MPC8641 specific */
24#define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */
Kumar Gala7649a592009-03-31 23:02:38 -050025#define CONFIG_MP 1 /* support multiple processors */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020026#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
Becky Bruce3111d322008-11-06 17:37:35 -060027/*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */
Becky Bruced591a802009-02-03 18:10:54 -060028#define CONFIG_ADDR_MAP 1 /* Use addr map */
Jon Loeligerdebb7352006-04-26 17:58:56 -050029
Wolfgang Denk2ae18242010-10-06 09:05:45 +020030/*
31 * default CCSRBAR is at 0xff700000
32 * assume U-Boot is less than 0.5MB
33 */
34#define CONFIG_SYS_TEXT_BASE 0xeff00000
35
Jon Loeligerdebb7352006-04-26 17:58:56 -050036#ifdef RUN_DIAG
Becky Bruce6bf98b12008-11-05 14:55:33 -060037#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
Jon Loeligerdebb7352006-04-26 17:58:56 -050038#endif
Jon Loeliger5c9efb32006-04-27 10:15:16 -050039
Becky Bruceaf5d1002008-10-31 17:14:14 -050040/*
Becky Bruce1266df82008-11-03 15:44:01 -060041 * virtual address to be used for temporary mappings. There
42 * should be 128k free at this VA.
43 */
44#define CONFIG_SYS_SCRATCH_VA 0xe0000000
45
Kumar Gala1b77ca82011-01-04 17:45:13 -060046#define CONFIG_SYS_SRIO
47#define CONFIG_SRIO1 /* SRIO port 1 */
Becky Bruceaf5d1002008-10-31 17:14:14 -050048
Ed Swarthout63cec582007-08-02 14:09:49 -050049#define CONFIG_PCI 1 /* Enable PCI/PCIE */
Kumar Gala46f3e382010-07-09 00:02:34 -050050#define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */
51#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */
Ed Swarthout63cec582007-08-02 14:09:49 -050052#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Kumar Gala8ba93f62008-10-21 18:06:15 -050053#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Becky Bruce4933b912008-01-23 16:31:01 -060054#define CONFIG_FSL_LAW 1 /* Use common FSL law init code */
Jon Loeliger5c9efb32006-04-27 10:15:16 -050055
Wolfgang Denk53677ef2008-05-20 16:00:29 +020056#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeligerdebb7352006-04-26 17:58:56 -050057#define CONFIG_ENV_OVERWRITE
Jon Loeliger5c9efb32006-04-27 10:15:16 -050058
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050059#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Becky Bruce31d82672008-05-08 19:02:12 -050060#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
Becky Bruced591a802009-02-03 18:10:54 -060061#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
Jon Loeligerdebb7352006-04-26 17:58:56 -050062
Wolfgang Denk53677ef2008-05-20 16:00:29 +020063#define CONFIG_ALTIVEC 1
Jon Loeligerdebb7352006-04-26 17:58:56 -050064
Jon Loeliger5c9efb32006-04-27 10:15:16 -050065/*
Jon Loeligerdebb7352006-04-26 17:58:56 -050066 * L2CR setup -- make sure this is right for your board!
67 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_L2
Jon Loeligerdebb7352006-04-26 17:58:56 -050069#define L2_INIT 0
70#define L2_ENABLE (L2CR_L2E)
71
72#ifndef CONFIG_SYS_CLK_FREQ
Ed Swarthout63cec582007-08-02 14:09:49 -050073#ifndef __ASSEMBLY__
74extern unsigned long get_board_sys_clk(unsigned long dummy);
75#endif
Wolfgang Denk53677ef2008-05-20 16:00:29 +020076#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
Jon Loeligerdebb7352006-04-26 17:58:56 -050077#endif
78
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
80#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeligerdebb7352006-04-26 17:58:56 -050081
Jon Loeligerdebb7352006-04-26 17:58:56 -050082/*
Becky Bruce3111d322008-11-06 17:37:35 -060083 * With the exception of PCI Memory and Rapid IO, most devices will simply
84 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
85 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
86 */
87#ifdef CONFIG_PHYS_64BIT
Becky Bruce1605cc92011-10-03 19:10:51 -050088#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
Becky Bruce3111d322008-11-06 17:37:35 -060089#else
Becky Bruce1605cc92011-10-03 19:10:51 -050090#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -060091#endif
92
93/*
Jon Loeligerdebb7352006-04-26 17:58:56 -050094 * Base addresses -- Note these are effective addresses where the
95 * actual resources get mapped (not physical addresses)
96 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
Becky Brucec759a012008-11-06 17:36:04 -060098#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500100
Becky Bruce3111d322008-11-06 17:37:35 -0600101/* Physical addresses */
102#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Becky Bruce1605cc92011-10-03 19:10:51 -0500103#define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
104#define CONFIG_SYS_CCSRBAR_PHYS \
105 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
106 CONFIG_SYS_CCSRBAR_PHYS_HIGH)
Becky Bruce3111d322008-11-06 17:37:35 -0600107
york076bff82010-07-02 22:25:52 +0000108#define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
109
Jon Loeligerdebb7352006-04-26 17:58:56 -0500110/*
111 * DDR Setup
112 */
York Sun5614e712013-09-30 09:22:09 -0700113#define CONFIG_SYS_FSL_DDR2
Kumar Gala6a8e5692008-08-26 15:01:35 -0500114#undef CONFIG_FSL_DDR_INTERACTIVE
115#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
116#define CONFIG_DDR_SPD
117
118#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
119#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
122#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Becky Bruce1266df82008-11-03 15:44:01 -0600123#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
Jin Zhengxiongfcb28e72006-07-13 10:35:10 -0500124#define CONFIG_VERY_BIG_RAM
Jon Loeligerdebb7352006-04-26 17:58:56 -0500125
Kumar Gala6a8e5692008-08-26 15:01:35 -0500126#define CONFIG_NUM_DDR_CONTROLLERS 2
127#define CONFIG_DIMM_SLOTS_PER_CTLR 2
128#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500129
Kumar Gala6a8e5692008-08-26 15:01:35 -0500130/*
131 * I2C addresses of SPD EEPROMs
132 */
133#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
134#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
135#define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
136#define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500137
Jon Loeligerdebb7352006-04-26 17:58:56 -0500138
Kumar Gala6a8e5692008-08-26 15:01:35 -0500139/*
140 * These are used when DDR doesn't use SPD.
141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
143#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
144#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
145#define CONFIG_SYS_DDR_TIMING_3 0x00000000
146#define CONFIG_SYS_DDR_TIMING_0 0x00260802
147#define CONFIG_SYS_DDR_TIMING_1 0x39357322
148#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
149#define CONFIG_SYS_DDR_MODE_1 0x00480432
150#define CONFIG_SYS_DDR_MODE_2 0x00000000
151#define CONFIG_SYS_DDR_INTERVAL 0x06090100
152#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
153#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
154#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
155#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
156#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
157#define CONFIG_SYS_DDR_CONTROL2 0x04400000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500158
Jon Loeligerad8f8682008-01-15 13:42:41 -0600159#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_I2C_EEPROM_NXID
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200161#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
163#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500164
Becky Brucec759a012008-11-06 17:36:04 -0600165#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
Becky Bruce1605cc92011-10-03 19:10:51 -0500166#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
167#define CONFIG_SYS_FLASH_BASE_PHYS \
168 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
169 CONFIG_SYS_PHYS_ADDR_HIGH)
Becky Bruce3111d322008-11-06 17:37:35 -0600170
Becky Bruceb81b7732009-02-02 16:34:52 -0600171#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Jon Loeligerdebb7352006-04-26 17:58:56 -0500172
Becky Bruce3111d322008-11-06 17:37:35 -0600173#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
174 | 0x00001001) /* port size 16bit */
175#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500176
Becky Bruce3111d322008-11-06 17:37:35 -0600177#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
178 | 0x00001001) /* port size 16bit */
179#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500180
Becky Bruce3111d322008-11-06 17:37:35 -0600181#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
182 | 0x00000801) /* port size 8bit */
183#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500184
Becky Brucec759a012008-11-06 17:36:04 -0600185/*
186 * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
187 * The PIXIS and CF by themselves aren't large enough to take up the 128k
188 * required for the smallest BAT mapping, so there's a 64k hole.
189 */
190#define CONFIG_SYS_LBC_BASE 0xffde0000
Becky Bruce1605cc92011-10-03 19:10:51 -0500191#define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500192
Kim Phillips7608d752007-08-21 17:00:17 -0500193#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Becky Brucec759a012008-11-06 17:36:04 -0600194#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
Becky Bruce1605cc92011-10-03 19:10:51 -0500195#define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
196#define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
197 CONFIG_SYS_PHYS_ADDR_HIGH)
Becky Brucec759a012008-11-06 17:36:04 -0600198#define PIXIS_SIZE 0x00008000 /* 32k */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500199#define PIXIS_ID 0x0 /* Board ID at offset 0 */
200#define PIXIS_VER 0x1 /* Board version at offset 1 */
201#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
202#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
203#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
204#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
205#define PIXIS_VCTL 0x10 /* VELA Control Register */
206#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
207#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
208#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala9af9c6b2009-07-15 13:45:00 -0500209#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
210#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500211#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
212#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
213#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
214#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500216
Becky Bruceb5431562008-10-31 17:13:49 -0500217/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
Becky Brucec759a012008-11-06 17:36:04 -0600218#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
Becky Bruce3111d322008-11-06 17:37:35 -0600219#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
Becky Bruceb5431562008-10-31 17:13:49 -0500220
Becky Bruce170deac2008-11-05 14:55:32 -0600221#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#undef CONFIG_SYS_FLASH_CHECKSUM
225#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
226#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200227#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600228#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500229
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200230#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_FLASH_CFI
232#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeligerdebb7352006-04-26 17:58:56 -0500233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
235#define CONFIG_SYS_RAMBOOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500236#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#undef CONFIG_SYS_RAMBOOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500238#endif
239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#if defined(CONFIG_SYS_RAMBOOT)
Jin Zhengxiong-R64188fa7db9c2006-06-27 18:11:54 +0800241#undef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_SDRAM_SIZE 256
Jon Loeligerdebb7352006-04-26 17:58:56 -0500243#endif
244
245#undef CONFIG_CLOCKS_IN_MHZ
246
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_INIT_RAM_LOCK 1
248#ifndef CONFIG_SYS_INIT_RAM_LOCK
249#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500250#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500252#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200253#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500254
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200255#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeligerdebb7352006-04-26 17:58:56 -0500257
Scott Wood221fbd22015-04-15 16:13:48 -0500258#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500260
261/* Serial Port */
262#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_NS16550
264#define CONFIG_SYS_NS16550_SERIAL
265#define CONFIG_SYS_NS16550_REG_SIZE 1
266#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeligerdebb7352006-04-26 17:58:56 -0500269 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
272#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500273
274/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_HUSH_PARSER
Jon Loeligerdebb7352006-04-26 17:58:56 -0500276
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500277/*
278 * Pass open firmware flat tree to kernel
279 */
Jon Loeligerea9f7392007-11-28 14:47:18 -0600280#define CONFIG_OF_LIBFDT 1
281#define CONFIG_OF_BOARD_SETUP 1
282#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500283
Jon Loeliger586d1d52006-05-19 13:22:44 -0500284/*
285 * I2C
286 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200287#define CONFIG_SYS_I2C
288#define CONFIG_SYS_I2C_FSL
289#define CONFIG_SYS_FSL_I2C_SPEED 400000
290#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
291#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
292#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jon Loeligerdebb7352006-04-26 17:58:56 -0500293
Jon Loeliger586d1d52006-05-19 13:22:44 -0500294/*
295 * RapidIO MMU
296 */
Kumar Gala1b77ca82011-01-04 17:45:13 -0600297#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
Becky Bruce3111d322008-11-06 17:37:35 -0600298#ifdef CONFIG_PHYS_64BIT
Becky Bruce1605cc92011-10-03 19:10:51 -0500299#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
300#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
Becky Bruce3111d322008-11-06 17:37:35 -0600301#else
Becky Bruce1605cc92011-10-03 19:10:51 -0500302#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
303#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -0600304#endif
Becky Bruce1605cc92011-10-03 19:10:51 -0500305#define CONFIG_SYS_SRIO1_MEM_PHYS \
306 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
307 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
Kumar Gala1b77ca82011-01-04 17:45:13 -0600308#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500309
310/*
311 * General PCI
312 * Addresses are mapped 1-1.
313 */
Becky Bruce49f46f32009-02-03 18:10:53 -0600314
Kumar Gala64e55d52010-12-17 10:47:36 -0600315#define CONFIG_SYS_PCIE1_NAME "ULI"
Kumar Gala46f3e382010-07-09 00:02:34 -0500316#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
Becky Bruce3111d322008-11-06 17:37:35 -0600317#ifdef CONFIG_PHYS_64BIT
Kumar Gala46f3e382010-07-09 00:02:34 -0500318#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Becky Bruce1605cc92011-10-03 19:10:51 -0500319#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
320#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
Becky Bruce3111d322008-11-06 17:37:35 -0600321#else
Kumar Gala46f3e382010-07-09 00:02:34 -0500322#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
Becky Bruce1605cc92011-10-03 19:10:51 -0500323#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
324#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -0600325#endif
Becky Bruce1605cc92011-10-03 19:10:51 -0500326#define CONFIG_SYS_PCIE1_MEM_PHYS \
327 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
328 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
Kumar Gala46f3e382010-07-09 00:02:34 -0500329#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
330#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
331#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
Becky Bruce1605cc92011-10-03 19:10:51 -0500332#define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
333#define CONFIG_SYS_PCIE1_IO_PHYS \
334 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
335 CONFIG_SYS_PHYS_ADDR_HIGH)
Kumar Gala46f3e382010-07-09 00:02:34 -0500336#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500337
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600338#ifdef CONFIG_PHYS_64BIT
339/*
Kumar Gala46f3e382010-07-09 00:02:34 -0500340 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600341 * This will increase the amount of PCI address space available for
342 * for mapping RAM.
343 */
Kumar Gala46f3e382010-07-09 00:02:34 -0500344#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600345#else
Kumar Gala46f3e382010-07-09 00:02:34 -0500346#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
347 + CONFIG_SYS_PCIE1_MEM_SIZE)
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600348#endif
Kumar Gala46f3e382010-07-09 00:02:34 -0500349#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
350 + CONFIG_SYS_PCIE1_MEM_SIZE)
Becky Bruce1605cc92011-10-03 19:10:51 -0500351#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
352 + CONFIG_SYS_PCIE1_MEM_SIZE)
353#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
Kumar Gala46f3e382010-07-09 00:02:34 -0500354#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
355 + CONFIG_SYS_PCIE1_MEM_SIZE)
356#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
357#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
358#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
359 + CONFIG_SYS_PCIE1_IO_SIZE)
Becky Bruce1605cc92011-10-03 19:10:51 -0500360#define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
361 + CONFIG_SYS_PCIE1_IO_SIZE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500362#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
363 + CONFIG_SYS_PCIE1_IO_SIZE)
364#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500365
Jon Loeligerdebb7352006-04-26 17:58:56 -0500366#if defined(CONFIG_PCI)
367
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200368#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500369
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500371
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200372#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500373
374#define CONFIG_RTL8139
375
Jon Loeligerdebb7352006-04-26 17:58:56 -0500376#undef CONFIG_EEPRO100
377#undef CONFIG_TULIP
378
Zhang Weia81d1c02007-06-06 10:08:14 +0200379/************************************************************
380 * USB support
381 ************************************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200382#define CONFIG_PCI_OHCI 1
Zhang Weia81d1c02007-06-06 10:08:14 +0200383#define CONFIG_USB_OHCI_NEW 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200384#define CONFIG_USB_KEYBOARD 1
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200385#define CONFIG_SYS_STDIO_DEREGISTER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_USB_EVENT_POLL 1
387#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
388#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
389#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Zhang Weia81d1c02007-06-06 10:08:14 +0200390
Jason Jin0f460a12007-07-13 12:14:58 +0800391/*PCIE video card used*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500392#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
Jason Jin0f460a12007-07-13 12:14:58 +0800393
394/*PCI video card used*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500395/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
Jason Jin0f460a12007-07-13 12:14:58 +0800396
397/* video */
398#define CONFIG_VIDEO
399
400#if defined(CONFIG_VIDEO)
401#define CONFIG_BIOSEMU
402#define CONFIG_CFB_CONSOLE
403#define CONFIG_VIDEO_SW_CURSOR
404#define CONFIG_VGA_AS_SINGLE_DEVICE
405#define CONFIG_ATI_RADEON_FB
406#define CONFIG_VIDEO_LOGO
407/*#define CONFIG_CONSOLE_CURSOR*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500408#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
Jason Jin0f460a12007-07-13 12:14:58 +0800409#endif
410
Jon Loeligerdebb7352006-04-26 17:58:56 -0500411#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500412
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800413#define CONFIG_DOS_PARTITION
414#define CONFIG_SCSI_AHCI
415
416#ifdef CONFIG_SCSI_AHCI
Rob Herring344ca0b2013-08-24 10:10:54 -0500417#define CONFIG_LIBATA
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800418#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
420#define CONFIG_SYS_SCSI_MAX_LUN 1
421#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
422#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800423#endif
424
Jon Loeligerdebb7352006-04-26 17:58:56 -0500425#endif /* CONFIG_PCI */
426
Jon Loeligerdebb7352006-04-26 17:58:56 -0500427#if defined(CONFIG_TSEC_ENET)
428
Jon Loeligerdebb7352006-04-26 17:58:56 -0500429#define CONFIG_MII 1 /* MII PHY management */
430
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200431#define CONFIG_TSEC1 1
432#define CONFIG_TSEC1_NAME "eTSEC1"
433#define CONFIG_TSEC2 1
434#define CONFIG_TSEC2_NAME "eTSEC2"
435#define CONFIG_TSEC3 1
436#define CONFIG_TSEC3_NAME "eTSEC3"
437#define CONFIG_TSEC4 1
438#define CONFIG_TSEC4_NAME "eTSEC4"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500439
Jon Loeligerdebb7352006-04-26 17:58:56 -0500440#define TSEC1_PHY_ADDR 0
441#define TSEC2_PHY_ADDR 1
442#define TSEC3_PHY_ADDR 2
443#define TSEC4_PHY_ADDR 3
444#define TSEC1_PHYIDX 0
445#define TSEC2_PHYIDX 0
446#define TSEC3_PHYIDX 0
447#define TSEC4_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500448#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
449#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
450#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
451#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500452
453#define CONFIG_ETHPRIME "eTSEC1"
454
455#endif /* CONFIG_TSEC_ENET */
456
Becky Bruce1605cc92011-10-03 19:10:51 -0500457
Becky Bruce3111d322008-11-06 17:37:35 -0600458#ifdef CONFIG_PHYS_64BIT
Becky Bruce3111d322008-11-06 17:37:35 -0600459#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
460#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
461
Becky Bruce1605cc92011-10-03 19:10:51 -0500462/* Put physical address into the BAT format */
463#define BAT_PHYS_ADDR(low, high) \
464 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
465/* Convert high/low pairs to actual 64-bit value */
466#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
467#else
468/* 32-bit systems just ignore the "high" bits */
469#define BAT_PHYS_ADDR(low, high) (low)
470#define PAIRED_PHYS_TO_PHYS(low, high) (low)
471#endif
472
Jon Loeliger586d1d52006-05-19 13:22:44 -0500473/*
Becky Brucec759a012008-11-06 17:36:04 -0600474 * BAT0 DDR
Jon Loeligerdebb7352006-04-26 17:58:56 -0500475 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200476#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
Timur Tabi9ff32d82010-03-29 12:51:07 -0500477#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500478
Jon Loeliger586d1d52006-05-19 13:22:44 -0500479/*
Becky Brucec759a012008-11-06 17:36:04 -0600480 * BAT1 LBC (PIXIS/CF)
Becky Bruceaf5d1002008-10-31 17:14:14 -0500481 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500482#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
483 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600484 | BATL_PP_RW | BATL_CACHEINHIBIT | \
485 BATL_GUARDEDSTORAGE)
Becky Brucec759a012008-11-06 17:36:04 -0600486#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
487 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500488#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
489 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600490 | BATL_PP_RW | BATL_MEMCOHERENCE)
Becky Brucec759a012008-11-06 17:36:04 -0600491#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
Becky Bruceaf5d1002008-10-31 17:14:14 -0500492
493/* if CONFIG_PCI:
Kumar Gala46f3e382010-07-09 00:02:34 -0500494 * BAT2 PCIE1 and PCIE1 MEM
Becky Bruceaf5d1002008-10-31 17:14:14 -0500495 * if CONFIG_RIO
Becky Brucec759a012008-11-06 17:36:04 -0600496 * BAT2 Rapidio Memory
Jon Loeligerdebb7352006-04-26 17:58:56 -0500497 */
Becky Bruceaf5d1002008-10-31 17:14:14 -0500498#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000499#define CONFIG_PCI_INDIRECT_BRIDGE
Becky Bruce1605cc92011-10-03 19:10:51 -0500500#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
501 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600502 | BATL_PP_RW | BATL_CACHEINHIBIT \
503 | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500504#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
Becky Bruceaf5d1002008-10-31 17:14:14 -0500505 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500506#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
507 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600508 | BATL_PP_RW | BATL_CACHEINHIBIT)
Becky Bruceaf5d1002008-10-31 17:14:14 -0500509#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
510#else /* CONFIG_RIO */
Becky Bruce1605cc92011-10-03 19:10:51 -0500511#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
512 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600513 | BATL_PP_RW | BATL_CACHEINHIBIT | \
514 BATL_GUARDEDSTORAGE)
Kumar Gala1b77ca82011-01-04 17:45:13 -0600515#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
Becky Bruce3111d322008-11-06 17:37:35 -0600516 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500517#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
518 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600519 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
Becky Bruceaf5d1002008-10-31 17:14:14 -0500521#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -0500522
Jon Loeliger586d1d52006-05-19 13:22:44 -0500523/*
Becky Brucec759a012008-11-06 17:36:04 -0600524 * BAT3 CCSR Space
Jon Loeligerdebb7352006-04-26 17:58:56 -0500525 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500526#define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
527 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600528 | BATL_PP_RW | BATL_CACHEINHIBIT \
529 | BATL_GUARDEDSTORAGE)
Becky Brucec759a012008-11-06 17:36:04 -0600530#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
531 | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500532#define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
533 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600534 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500536
Becky Bruce3111d322008-11-06 17:37:35 -0600537#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
538#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
539 | BATL_PP_RW | BATL_CACHEINHIBIT \
540 | BATL_GUARDEDSTORAGE)
541#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
542 | BATU_BL_1M | BATU_VS | BATU_VP)
543#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
544 | BATL_PP_RW | BATL_CACHEINHIBIT)
545#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
546#endif
547
Jon Loeliger586d1d52006-05-19 13:22:44 -0500548/*
Kumar Gala46f3e382010-07-09 00:02:34 -0500549 * BAT4 PCIE1_IO and PCIE2_IO
Jon Loeligerdebb7352006-04-26 17:58:56 -0500550 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500551#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
552 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600553 | BATL_PP_RW | BATL_CACHEINHIBIT \
554 | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500555#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
Becky Brucec759a012008-11-06 17:36:04 -0600556 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500557#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
558 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600559 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200560#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500561
Jon Loeliger586d1d52006-05-19 13:22:44 -0500562/*
Becky Brucec759a012008-11-06 17:36:04 -0600563 * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500564 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200565#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
566#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
567#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
568#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500569
Jon Loeliger586d1d52006-05-19 13:22:44 -0500570/*
Becky Brucec759a012008-11-06 17:36:04 -0600571 * BAT6 FLASH
Jon Loeligerdebb7352006-04-26 17:58:56 -0500572 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500573#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
574 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600575 | BATL_PP_RW | BATL_CACHEINHIBIT \
576 | BATL_GUARDEDSTORAGE)
Becky Bruce170deac2008-11-05 14:55:32 -0600577#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
578 | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500579#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
580 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600581 | BATL_PP_RW | BATL_MEMCOHERENCE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200582#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500583
Becky Brucebf9a8c32008-11-05 14:55:35 -0600584/* Map the last 1M of flash where we're running from reset */
585#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
586 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200587#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
Becky Brucebf9a8c32008-11-05 14:55:35 -0600588#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
589 | BATL_MEMCOHERENCE)
590#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
591
Becky Brucec759a012008-11-06 17:36:04 -0600592/*
593 * BAT7 FREE - used later for tmp mappings
594 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200595#define CONFIG_SYS_DBAT7L 0x00000000
596#define CONFIG_SYS_DBAT7U 0x00000000
597#define CONFIG_SYS_IBAT7L 0x00000000
598#define CONFIG_SYS_IBAT7U 0x00000000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500599
Jon Loeligerdebb7352006-04-26 17:58:56 -0500600/*
601 * Environment
602 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200603#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200604 #define CONFIG_ENV_IS_IN_FLASH 1
Scott Wood221fbd22015-04-15 16:13:48 -0500605 #define CONFIG_ENV_ADDR \
606 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200607 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500608#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200609 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200610 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500611#endif
Becky Bruce0f2d6602008-11-05 14:55:31 -0600612#define CONFIG_ENV_SIZE 0x2000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500613
614#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200615#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500616
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500617
618/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500619 * BOOTP options
620 */
621#define CONFIG_BOOTP_BOOTFILESIZE
622#define CONFIG_BOOTP_BOOTPATH
623#define CONFIG_BOOTP_GATEWAY
624#define CONFIG_BOOTP_HOSTNAME
625
626
627/*
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500628 * Command line configuration.
629 */
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500630#define CONFIG_CMD_PING
631#define CONFIG_CMD_I2C
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600632#define CONFIG_CMD_REGINFO
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500633
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500634#if defined(CONFIG_PCI)
635 #define CONFIG_CMD_PCI
636 #define CONFIG_CMD_SCSI
637 #define CONFIG_CMD_EXT2
Zhang Weibbf47962007-10-25 17:30:04 +0800638 #define CONFIG_CMD_USB
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500639#endif
640
Jon Loeligerdebb7352006-04-26 17:58:56 -0500641
642#undef CONFIG_WATCHDOG /* watchdog disabled */
643
644/*
645 * Miscellaneous configurable options
646 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200647#define CONFIG_SYS_LONGHELP /* undef to save memory */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200648#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200649#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500650
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500651#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200652 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500653#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200654 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500655#endif
656
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200657#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
658#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
659#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500660
661/*
662 * For booting Linux, the board info and command line data
663 * have to be in the first 8 MB of memory, since this is
664 * the maximum mapped by the Linux kernel during initialization.
665 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200666#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500667
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500668#if defined(CONFIG_CMD_KGDB)
669 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500670#endif
671
Jon Loeligerdebb7352006-04-26 17:58:56 -0500672/*
673 * Environment Configuration
674 */
675
Andy Fleming10327dc2007-08-16 16:35:02 -0500676#define CONFIG_HAS_ETH0 1
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500677#define CONFIG_HAS_ETH1 1
678#define CONFIG_HAS_ETH2 1
679#define CONFIG_HAS_ETH3 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500680
Jon Loeliger18b6c8c2006-05-09 08:23:49 -0500681#define CONFIG_IPADDR 192.168.1.100
Jon Loeligerdebb7352006-04-26 17:58:56 -0500682
683#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000684#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000685#define CONFIG_BOOTFILE "uImage"
Ed Swarthout32922cd2007-06-05 12:30:52 -0500686#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500687
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500688#define CONFIG_SERVERIP 192.168.1.1
Jon Loeliger18b6c8c2006-05-09 08:23:49 -0500689#define CONFIG_GATEWAYIP 192.168.1.1
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500690#define CONFIG_NETMASK 255.255.255.0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500691
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500692/* default location for tftp and bootm */
693#define CONFIG_LOADADDR 1000000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500694
695#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200696#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500697
698#define CONFIG_BAUDRATE 115200
699
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200700#define CONFIG_EXTRA_ENV_SETTINGS \
701 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200702 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200703 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200704 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
705 " +$filesize; " \
706 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
707 " +$filesize; " \
708 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
709 " $filesize; " \
710 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
711 " +$filesize; " \
712 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
713 " $filesize\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200714 "consoledev=ttyS0\0" \
715 "ramdiskaddr=2000000\0" \
716 "ramdiskfile=your.ramdisk.u-boot\0" \
717 "fdtaddr=c00000\0" \
718 "fdtfile=mpc8641_hpcn.dtb\0" \
Becky Bruce3111d322008-11-06 17:37:35 -0600719 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
720 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200721 "maxcpus=2"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500722
723
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200724#define CONFIG_NFSBOOTCOMMAND \
725 "setenv bootargs root=/dev/nfs rw " \
726 "nfsroot=$serverip:$rootpath " \
727 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
728 "console=$consoledev,$baudrate $othbootargs;" \
729 "tftp $loadaddr $bootfile;" \
730 "tftp $fdtaddr $fdtfile;" \
731 "bootm $loadaddr - $fdtaddr"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500732
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200733#define CONFIG_RAMBOOTCOMMAND \
734 "setenv bootargs root=/dev/ram rw " \
735 "console=$consoledev,$baudrate $othbootargs;" \
736 "tftp $ramdiskaddr $ramdiskfile;" \
737 "tftp $loadaddr $bootfile;" \
738 "tftp $fdtaddr $fdtfile;" \
739 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500740
741#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
742
743#endif /* __CONFIG_H */