Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 2 | /* |
| 3 | * RealTek PHY drivers |
| 4 | * |
Codrin Ciubotariu | 3cee138 | 2015-02-13 14:47:58 +0200 | [diff] [blame] | 5 | * Copyright 2010-2011, 2015 Freescale Semiconductor, Inc. |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 6 | * author Andy Fleming |
Karsten Merker | 563d8d9 | 2016-03-21 20:29:07 +0100 | [diff] [blame] | 7 | * Copyright 2016 Karsten Merker <merker@debian.org> |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 8 | */ |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 9 | #include <common.h> |
oliver@schinagl.nl | 020f676 | 2016-11-08 17:38:57 +0100 | [diff] [blame] | 10 | #include <linux/bitops.h> |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 11 | #include <phy.h> |
Simon Glass | c05ed00 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 12 | #include <linux/delay.h> |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 13 | |
oliver@schinagl.nl | cebf3f5 | 2016-11-08 17:38:59 +0100 | [diff] [blame] | 14 | #define PHY_RTL8211x_FORCE_MASTER BIT(1) |
kevans@FreeBSD.org | 66526e7 | 2018-02-14 17:02:15 -0600 | [diff] [blame] | 15 | #define PHY_RTL8211E_PINE64_GIGABIT_FIX BIT(2) |
Carlo Caione | d47cfdb | 2019-01-24 08:54:37 +0000 | [diff] [blame] | 16 | #define PHY_RTL8211F_FORCE_EEE_RXC_ON BIT(3) |
oliver@schinagl.nl | cebf3f5 | 2016-11-08 17:38:59 +0100 | [diff] [blame] | 17 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 18 | #define PHY_AUTONEGOTIATE_TIMEOUT 5000 |
| 19 | |
Michael Haas | 525d187 | 2016-03-25 18:22:50 +0100 | [diff] [blame] | 20 | /* RTL8211x 1000BASE-T Control Register */ |
oliver@schinagl.nl | 020f676 | 2016-11-08 17:38:57 +0100 | [diff] [blame] | 21 | #define MIIM_RTL8211x_CTRL1000T_MSCE BIT(12); |
oliver@schinagl.nl | cbe40e1 | 2016-11-08 17:38:58 +0100 | [diff] [blame] | 22 | #define MIIM_RTL8211x_CTRL1000T_MASTER BIT(11); |
Michael Haas | 525d187 | 2016-03-25 18:22:50 +0100 | [diff] [blame] | 23 | |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 24 | /* RTL8211x PHY Status Register */ |
| 25 | #define MIIM_RTL8211x_PHY_STATUS 0x11 |
| 26 | #define MIIM_RTL8211x_PHYSTAT_SPEED 0xc000 |
| 27 | #define MIIM_RTL8211x_PHYSTAT_GBIT 0x8000 |
| 28 | #define MIIM_RTL8211x_PHYSTAT_100 0x4000 |
| 29 | #define MIIM_RTL8211x_PHYSTAT_DUPLEX 0x2000 |
| 30 | #define MIIM_RTL8211x_PHYSTAT_SPDDONE 0x0800 |
| 31 | #define MIIM_RTL8211x_PHYSTAT_LINK 0x0400 |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 32 | |
Codrin Ciubotariu | 3cee138 | 2015-02-13 14:47:58 +0200 | [diff] [blame] | 33 | /* RTL8211x PHY Interrupt Enable Register */ |
| 34 | #define MIIM_RTL8211x_PHY_INER 0x12 |
| 35 | #define MIIM_RTL8211x_PHY_INTR_ENA 0x9f01 |
| 36 | #define MIIM_RTL8211x_PHY_INTR_DIS 0x0000 |
| 37 | |
| 38 | /* RTL8211x PHY Interrupt Status Register */ |
| 39 | #define MIIM_RTL8211x_PHY_INSR 0x13 |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 40 | |
Shengzhou Liu | 3d6af74 | 2015-03-12 18:54:59 +0800 | [diff] [blame] | 41 | /* RTL8211F PHY Status Register */ |
| 42 | #define MIIM_RTL8211F_PHY_STATUS 0x1a |
| 43 | #define MIIM_RTL8211F_AUTONEG_ENABLE 0x1000 |
| 44 | #define MIIM_RTL8211F_PHYSTAT_SPEED 0x0030 |
| 45 | #define MIIM_RTL8211F_PHYSTAT_GBIT 0x0020 |
| 46 | #define MIIM_RTL8211F_PHYSTAT_100 0x0010 |
| 47 | #define MIIM_RTL8211F_PHYSTAT_DUPLEX 0x0008 |
| 48 | #define MIIM_RTL8211F_PHYSTAT_SPDDONE 0x0800 |
| 49 | #define MIIM_RTL8211F_PHYSTAT_LINK 0x0004 |
| 50 | |
kevans@FreeBSD.org | 66526e7 | 2018-02-14 17:02:15 -0600 | [diff] [blame] | 51 | #define MIIM_RTL8211E_CONFREG 0x1c |
| 52 | #define MIIM_RTL8211E_CONFREG_TXD 0x0002 |
| 53 | #define MIIM_RTL8211E_CONFREG_RXD 0x0004 |
| 54 | #define MIIM_RTL8211E_CONFREG_MAGIC 0xb400 /* Undocumented */ |
| 55 | |
| 56 | #define MIIM_RTL8211E_EXT_PAGE_SELECT 0x1e |
| 57 | |
Shengzhou Liu | 3d6af74 | 2015-03-12 18:54:59 +0800 | [diff] [blame] | 58 | #define MIIM_RTL8211F_PAGE_SELECT 0x1f |
Shengzhou Liu | 793ea94 | 2015-04-24 16:57:17 +0800 | [diff] [blame] | 59 | #define MIIM_RTL8211F_TX_DELAY 0x100 |
Fugang Duan | e32e4d0 | 2020-05-03 22:41:16 +0800 | [diff] [blame] | 60 | #define MIIM_RTL8211F_RX_DELAY 0x8 |
Shengzhou Liu | 9071274 | 2015-05-21 18:07:35 +0800 | [diff] [blame] | 61 | #define MIIM_RTL8211F_LCR 0x10 |
Shengzhou Liu | 3d6af74 | 2015-03-12 18:54:59 +0800 | [diff] [blame] | 62 | |
Carlo Caione | e57c9fd | 2019-01-16 11:34:50 +0000 | [diff] [blame] | 63 | static int rtl8211f_phy_extread(struct phy_device *phydev, int addr, |
| 64 | int devaddr, int regnum) |
| 65 | { |
| 66 | int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, |
| 67 | MIIM_RTL8211F_PAGE_SELECT); |
| 68 | int val; |
| 69 | |
| 70 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr); |
| 71 | val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); |
| 72 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage); |
| 73 | |
| 74 | return val; |
| 75 | } |
| 76 | |
| 77 | static int rtl8211f_phy_extwrite(struct phy_device *phydev, int addr, |
| 78 | int devaddr, int regnum, u16 val) |
| 79 | { |
| 80 | int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, |
| 81 | MIIM_RTL8211F_PAGE_SELECT); |
| 82 | |
| 83 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, devaddr); |
| 84 | phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); |
| 85 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, oldpage); |
| 86 | |
| 87 | return 0; |
| 88 | } |
| 89 | |
oliver@schinagl.nl | cebf3f5 | 2016-11-08 17:38:59 +0100 | [diff] [blame] | 90 | static int rtl8211b_probe(struct phy_device *phydev) |
| 91 | { |
| 92 | #ifdef CONFIG_RTL8211X_PHY_FORCE_MASTER |
| 93 | phydev->flags |= PHY_RTL8211x_FORCE_MASTER; |
| 94 | #endif |
| 95 | |
| 96 | return 0; |
| 97 | } |
| 98 | |
kevans@FreeBSD.org | 66526e7 | 2018-02-14 17:02:15 -0600 | [diff] [blame] | 99 | static int rtl8211e_probe(struct phy_device *phydev) |
| 100 | { |
| 101 | #ifdef CONFIG_RTL8211E_PINE64_GIGABIT_FIX |
| 102 | phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX; |
| 103 | #endif |
| 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
Carlo Caione | d47cfdb | 2019-01-24 08:54:37 +0000 | [diff] [blame] | 108 | static int rtl8211f_probe(struct phy_device *phydev) |
| 109 | { |
| 110 | #ifdef CONFIG_RTL8211F_PHY_FORCE_EEE_RXC_ON |
| 111 | phydev->flags |= PHY_RTL8211F_FORCE_EEE_RXC_ON; |
| 112 | #endif |
| 113 | |
| 114 | return 0; |
| 115 | } |
| 116 | |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 117 | /* RealTek RTL8211x */ |
| 118 | static int rtl8211x_config(struct phy_device *phydev) |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 119 | { |
| 120 | phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); |
| 121 | |
Codrin Ciubotariu | 3cee138 | 2015-02-13 14:47:58 +0200 | [diff] [blame] | 122 | /* mask interrupt at init; if the interrupt is |
| 123 | * needed indeed, it should be explicitly enabled |
| 124 | */ |
| 125 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, |
| 126 | MIIM_RTL8211x_PHY_INTR_DIS); |
oliver@schinagl.nl | cebf3f5 | 2016-11-08 17:38:59 +0100 | [diff] [blame] | 127 | |
| 128 | if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) { |
| 129 | unsigned int reg; |
| 130 | |
| 131 | reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); |
| 132 | /* force manual master/slave configuration */ |
| 133 | reg |= MIIM_RTL8211x_CTRL1000T_MSCE; |
| 134 | /* force master mode */ |
| 135 | reg |= MIIM_RTL8211x_CTRL1000T_MASTER; |
| 136 | phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); |
| 137 | } |
kevans@FreeBSD.org | 66526e7 | 2018-02-14 17:02:15 -0600 | [diff] [blame] | 138 | if (phydev->flags & PHY_RTL8211E_PINE64_GIGABIT_FIX) { |
| 139 | unsigned int reg; |
| 140 | |
| 141 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, |
| 142 | 7); |
| 143 | phy_write(phydev, MDIO_DEVAD_NONE, |
| 144 | MIIM_RTL8211E_EXT_PAGE_SELECT, 0xa4); |
| 145 | reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG); |
| 146 | /* Ensure both internal delays are turned off */ |
| 147 | reg &= ~(MIIM_RTL8211E_CONFREG_TXD | MIIM_RTL8211E_CONFREG_RXD); |
| 148 | /* Flip the magic undocumented bits */ |
| 149 | reg |= MIIM_RTL8211E_CONFREG_MAGIC; |
| 150 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211E_CONFREG, reg); |
| 151 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, |
| 152 | 0); |
| 153 | } |
Codrin Ciubotariu | 3cee138 | 2015-02-13 14:47:58 +0200 | [diff] [blame] | 154 | /* read interrupt status just to clear it */ |
| 155 | phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER); |
| 156 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 157 | genphy_config_aneg(phydev); |
| 158 | |
| 159 | return 0; |
| 160 | } |
| 161 | |
Amit Singh Tomar | b0778d9 | 2020-05-09 19:55:10 +0530 | [diff] [blame^] | 162 | /* RealTek RTL8201F */ |
| 163 | static int rtl8201f_config(struct phy_device *phydev) |
| 164 | { |
| 165 | genphy_config_aneg(phydev); |
| 166 | |
| 167 | return 0; |
| 168 | } |
| 169 | |
Shengzhou Liu | 793ea94 | 2015-04-24 16:57:17 +0800 | [diff] [blame] | 170 | static int rtl8211f_config(struct phy_device *phydev) |
| 171 | { |
| 172 | u16 reg; |
| 173 | |
Carlo Caione | d47cfdb | 2019-01-24 08:54:37 +0000 | [diff] [blame] | 174 | if (phydev->flags & PHY_RTL8211F_FORCE_EEE_RXC_ON) { |
| 175 | unsigned int reg; |
| 176 | |
| 177 | reg = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1); |
| 178 | reg &= ~MDIO_PCS_CTRL1_CLKSTOP_EN; |
| 179 | phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, reg); |
| 180 | } |
| 181 | |
Shengzhou Liu | 793ea94 | 2015-04-24 16:57:17 +0800 | [diff] [blame] | 182 | phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); |
| 183 | |
Madalin Bucur | 05b29aa | 2017-08-18 11:35:24 +0300 | [diff] [blame] | 184 | phy_write(phydev, MDIO_DEVAD_NONE, |
| 185 | MIIM_RTL8211F_PAGE_SELECT, 0xd08); |
| 186 | reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x11); |
| 187 | |
| 188 | /* enable TX-delay for rgmii-id and rgmii-txid, otherwise disable it */ |
| 189 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || |
| 190 | phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) |
Shengzhou Liu | 793ea94 | 2015-04-24 16:57:17 +0800 | [diff] [blame] | 191 | reg |= MIIM_RTL8211F_TX_DELAY; |
Madalin Bucur | 05b29aa | 2017-08-18 11:35:24 +0300 | [diff] [blame] | 192 | else |
| 193 | reg &= ~MIIM_RTL8211F_TX_DELAY; |
| 194 | |
| 195 | phy_write(phydev, MDIO_DEVAD_NONE, 0x11, reg); |
Fugang Duan | e32e4d0 | 2020-05-03 22:41:16 +0800 | [diff] [blame] | 196 | |
| 197 | /* enable RX-delay for rgmii-id and rgmii-rxid, otherwise disable it */ |
| 198 | reg = phy_read(phydev, MDIO_DEVAD_NONE, 0x15); |
| 199 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID || |
| 200 | phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) |
| 201 | reg |= MIIM_RTL8211F_RX_DELAY; |
| 202 | else |
| 203 | reg &= ~MIIM_RTL8211F_RX_DELAY; |
| 204 | phy_write(phydev, MDIO_DEVAD_NONE, 0x15, reg); |
| 205 | |
Madalin Bucur | 05b29aa | 2017-08-18 11:35:24 +0300 | [diff] [blame] | 206 | /* restore to default page 0 */ |
| 207 | phy_write(phydev, MDIO_DEVAD_NONE, |
| 208 | MIIM_RTL8211F_PAGE_SELECT, 0x0); |
Shengzhou Liu | 793ea94 | 2015-04-24 16:57:17 +0800 | [diff] [blame] | 209 | |
Shengzhou Liu | 9071274 | 2015-05-21 18:07:35 +0800 | [diff] [blame] | 210 | /* Set green LED for Link, yellow LED for Active */ |
| 211 | phy_write(phydev, MDIO_DEVAD_NONE, |
| 212 | MIIM_RTL8211F_PAGE_SELECT, 0xd04); |
| 213 | phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x617f); |
| 214 | phy_write(phydev, MDIO_DEVAD_NONE, |
| 215 | MIIM_RTL8211F_PAGE_SELECT, 0x0); |
| 216 | |
Shengzhou Liu | 793ea94 | 2015-04-24 16:57:17 +0800 | [diff] [blame] | 217 | genphy_config_aneg(phydev); |
| 218 | |
| 219 | return 0; |
| 220 | } |
| 221 | |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 222 | static int rtl8211x_parse_status(struct phy_device *phydev) |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 223 | { |
| 224 | unsigned int speed; |
| 225 | unsigned int mii_reg; |
| 226 | |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 227 | mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_STATUS); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 228 | |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 229 | if (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) { |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 230 | int i = 0; |
| 231 | |
| 232 | /* in case of timeout ->link is cleared */ |
| 233 | phydev->link = 1; |
| 234 | puts("Waiting for PHY realtime link"); |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 235 | while (!(mii_reg & MIIM_RTL8211x_PHYSTAT_SPDDONE)) { |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 236 | /* Timeout reached ? */ |
| 237 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { |
| 238 | puts(" TIMEOUT !\n"); |
| 239 | phydev->link = 0; |
| 240 | break; |
| 241 | } |
| 242 | |
| 243 | if ((i++ % 1000) == 0) |
| 244 | putc('.'); |
| 245 | udelay(1000); /* 1 ms */ |
| 246 | mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 247 | MIIM_RTL8211x_PHY_STATUS); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 248 | } |
| 249 | puts(" done\n"); |
| 250 | udelay(500000); /* another 500 ms (results in faster booting) */ |
| 251 | } else { |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 252 | if (mii_reg & MIIM_RTL8211x_PHYSTAT_LINK) |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 253 | phydev->link = 1; |
| 254 | else |
| 255 | phydev->link = 0; |
| 256 | } |
| 257 | |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 258 | if (mii_reg & MIIM_RTL8211x_PHYSTAT_DUPLEX) |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 259 | phydev->duplex = DUPLEX_FULL; |
| 260 | else |
| 261 | phydev->duplex = DUPLEX_HALF; |
| 262 | |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 263 | speed = (mii_reg & MIIM_RTL8211x_PHYSTAT_SPEED); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 264 | |
| 265 | switch (speed) { |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 266 | case MIIM_RTL8211x_PHYSTAT_GBIT: |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 267 | phydev->speed = SPEED_1000; |
| 268 | break; |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 269 | case MIIM_RTL8211x_PHYSTAT_100: |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 270 | phydev->speed = SPEED_100; |
| 271 | break; |
| 272 | default: |
| 273 | phydev->speed = SPEED_10; |
| 274 | } |
| 275 | |
| 276 | return 0; |
| 277 | } |
| 278 | |
Shengzhou Liu | 3d6af74 | 2015-03-12 18:54:59 +0800 | [diff] [blame] | 279 | static int rtl8211f_parse_status(struct phy_device *phydev) |
| 280 | { |
| 281 | unsigned int speed; |
| 282 | unsigned int mii_reg; |
| 283 | int i = 0; |
| 284 | |
| 285 | phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PAGE_SELECT, 0xa43); |
| 286 | mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211F_PHY_STATUS); |
| 287 | |
| 288 | phydev->link = 1; |
| 289 | while (!(mii_reg & MIIM_RTL8211F_PHYSTAT_LINK)) { |
| 290 | if (i > PHY_AUTONEGOTIATE_TIMEOUT) { |
| 291 | puts(" TIMEOUT !\n"); |
| 292 | phydev->link = 0; |
| 293 | break; |
| 294 | } |
| 295 | |
| 296 | if ((i++ % 1000) == 0) |
| 297 | putc('.'); |
| 298 | udelay(1000); |
| 299 | mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, |
| 300 | MIIM_RTL8211F_PHY_STATUS); |
| 301 | } |
| 302 | |
| 303 | if (mii_reg & MIIM_RTL8211F_PHYSTAT_DUPLEX) |
| 304 | phydev->duplex = DUPLEX_FULL; |
| 305 | else |
| 306 | phydev->duplex = DUPLEX_HALF; |
| 307 | |
| 308 | speed = (mii_reg & MIIM_RTL8211F_PHYSTAT_SPEED); |
| 309 | |
| 310 | switch (speed) { |
| 311 | case MIIM_RTL8211F_PHYSTAT_GBIT: |
| 312 | phydev->speed = SPEED_1000; |
| 313 | break; |
| 314 | case MIIM_RTL8211F_PHYSTAT_100: |
| 315 | phydev->speed = SPEED_100; |
| 316 | break; |
| 317 | default: |
| 318 | phydev->speed = SPEED_10; |
| 319 | } |
| 320 | |
Shengzhou Liu | 3d6af74 | 2015-03-12 18:54:59 +0800 | [diff] [blame] | 321 | return 0; |
| 322 | } |
| 323 | |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 324 | static int rtl8211x_startup(struct phy_device *phydev) |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 325 | { |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 326 | int ret; |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 327 | |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 328 | /* Read the Status (2x to make sure link is right) */ |
| 329 | ret = genphy_update_link(phydev); |
| 330 | if (ret) |
| 331 | return ret; |
| 332 | |
| 333 | return rtl8211x_parse_status(phydev); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 334 | } |
| 335 | |
Michal Simek | 6a10bc5 | 2016-02-13 10:31:32 +0100 | [diff] [blame] | 336 | static int rtl8211e_startup(struct phy_device *phydev) |
| 337 | { |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 338 | int ret; |
Michal Simek | 6a10bc5 | 2016-02-13 10:31:32 +0100 | [diff] [blame] | 339 | |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 340 | ret = genphy_update_link(phydev); |
| 341 | if (ret) |
| 342 | return ret; |
| 343 | |
| 344 | return genphy_parse_link(phydev); |
Michal Simek | 6a10bc5 | 2016-02-13 10:31:32 +0100 | [diff] [blame] | 345 | } |
| 346 | |
Shengzhou Liu | 3d6af74 | 2015-03-12 18:54:59 +0800 | [diff] [blame] | 347 | static int rtl8211f_startup(struct phy_device *phydev) |
| 348 | { |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 349 | int ret; |
Shengzhou Liu | 3d6af74 | 2015-03-12 18:54:59 +0800 | [diff] [blame] | 350 | |
Michal Simek | b733c27 | 2016-05-18 12:46:12 +0200 | [diff] [blame] | 351 | /* Read the Status (2x to make sure link is right) */ |
| 352 | ret = genphy_update_link(phydev); |
| 353 | if (ret) |
| 354 | return ret; |
| 355 | /* Read the Status (2x to make sure link is right) */ |
| 356 | |
| 357 | return rtl8211f_parse_status(phydev); |
Shengzhou Liu | 3d6af74 | 2015-03-12 18:54:59 +0800 | [diff] [blame] | 358 | } |
| 359 | |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 360 | /* Support for RTL8211B PHY */ |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 361 | static struct phy_driver RTL8211B_driver = { |
| 362 | .name = "RealTek RTL8211B", |
Karsten Merker | 563d8d9 | 2016-03-21 20:29:07 +0100 | [diff] [blame] | 363 | .uid = 0x1cc912, |
Bhupesh Sharma | 4220504 | 2013-09-01 04:40:52 +0530 | [diff] [blame] | 364 | .mask = 0xffffff, |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 365 | .features = PHY_GBIT_FEATURES, |
oliver@schinagl.nl | cebf3f5 | 2016-11-08 17:38:59 +0100 | [diff] [blame] | 366 | .probe = &rtl8211b_probe, |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 367 | .config = &rtl8211x_config, |
| 368 | .startup = &rtl8211x_startup, |
| 369 | .shutdown = &genphy_shutdown, |
| 370 | }; |
| 371 | |
| 372 | /* Support for RTL8211E-VB-CG, RTL8211E-VL-CG and RTL8211EG-VB-CG PHYs */ |
| 373 | static struct phy_driver RTL8211E_driver = { |
| 374 | .name = "RealTek RTL8211E", |
| 375 | .uid = 0x1cc915, |
Bhupesh Sharma | 4220504 | 2013-09-01 04:40:52 +0530 | [diff] [blame] | 376 | .mask = 0xffffff, |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 377 | .features = PHY_GBIT_FEATURES, |
kevans@FreeBSD.org | 66526e7 | 2018-02-14 17:02:15 -0600 | [diff] [blame] | 378 | .probe = &rtl8211e_probe, |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 379 | .config = &rtl8211x_config, |
Michal Simek | 6a10bc5 | 2016-02-13 10:31:32 +0100 | [diff] [blame] | 380 | .startup = &rtl8211e_startup, |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 381 | .shutdown = &genphy_shutdown, |
| 382 | }; |
| 383 | |
| 384 | /* Support for RTL8211DN PHY */ |
| 385 | static struct phy_driver RTL8211DN_driver = { |
| 386 | .name = "RealTek RTL8211DN", |
| 387 | .uid = 0x1cc914, |
Bhupesh Sharma | 4220504 | 2013-09-01 04:40:52 +0530 | [diff] [blame] | 388 | .mask = 0xffffff, |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 389 | .features = PHY_GBIT_FEATURES, |
| 390 | .config = &rtl8211x_config, |
| 391 | .startup = &rtl8211x_startup, |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 392 | .shutdown = &genphy_shutdown, |
| 393 | }; |
| 394 | |
Shengzhou Liu | 3d6af74 | 2015-03-12 18:54:59 +0800 | [diff] [blame] | 395 | /* Support for RTL8211F PHY */ |
| 396 | static struct phy_driver RTL8211F_driver = { |
| 397 | .name = "RealTek RTL8211F", |
| 398 | .uid = 0x1cc916, |
| 399 | .mask = 0xffffff, |
| 400 | .features = PHY_GBIT_FEATURES, |
Carlo Caione | d47cfdb | 2019-01-24 08:54:37 +0000 | [diff] [blame] | 401 | .probe = &rtl8211f_probe, |
Shengzhou Liu | 793ea94 | 2015-04-24 16:57:17 +0800 | [diff] [blame] | 402 | .config = &rtl8211f_config, |
Shengzhou Liu | 3d6af74 | 2015-03-12 18:54:59 +0800 | [diff] [blame] | 403 | .startup = &rtl8211f_startup, |
| 404 | .shutdown = &genphy_shutdown, |
Carlo Caione | e57c9fd | 2019-01-16 11:34:50 +0000 | [diff] [blame] | 405 | .readext = &rtl8211f_phy_extread, |
| 406 | .writeext = &rtl8211f_phy_extwrite, |
Shengzhou Liu | 3d6af74 | 2015-03-12 18:54:59 +0800 | [diff] [blame] | 407 | }; |
| 408 | |
Amit Singh Tomar | b0778d9 | 2020-05-09 19:55:10 +0530 | [diff] [blame^] | 409 | /* Support for RTL8201F PHY */ |
| 410 | static struct phy_driver RTL8201F_driver = { |
| 411 | .name = "RealTek RTL8201F 10/100Mbps Ethernet", |
| 412 | .uid = 0x1cc816, |
| 413 | .mask = 0xffffff, |
| 414 | .features = PHY_BASIC_FEATURES, |
| 415 | .config = &rtl8201f_config, |
| 416 | .startup = &rtl8211e_startup, |
| 417 | .shutdown = &genphy_shutdown, |
| 418 | }; |
| 419 | |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 420 | int phy_realtek_init(void) |
| 421 | { |
| 422 | phy_register(&RTL8211B_driver); |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 423 | phy_register(&RTL8211E_driver); |
Shengzhou Liu | 3d6af74 | 2015-03-12 18:54:59 +0800 | [diff] [blame] | 424 | phy_register(&RTL8211F_driver); |
Bhupesh Sharma | c624d16 | 2013-07-18 13:58:20 +0530 | [diff] [blame] | 425 | phy_register(&RTL8211DN_driver); |
Amit Singh Tomar | b0778d9 | 2020-05-09 19:55:10 +0530 | [diff] [blame^] | 426 | phy_register(&RTL8201F_driver); |
Andy Fleming | 9082eea | 2011-04-07 21:56:05 -0500 | [diff] [blame] | 427 | |
| 428 | return 0; |
| 429 | } |