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Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +01001/*
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2005-2007
6 * Modified for InterControl digsyMTC MPC5200 board by
7 * Frank Bodammer, GCD Hard- & Software GmbH,
8 * frank.bodammer@gcd-solutions.de
9 *
10 * (C) Copyright 2009 Semihalf
11 * Optimized for digsyMTC by: Grzegorz Bernacki <gjb@semihalf.com>
12 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020013 * SPDX-License-Identifier: GPL-2.0+
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010014 */
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
19/*
20 * High Level Configuration Options
21 */
22
Masahiro Yamadab2a6dfe2014-01-16 11:03:07 +090023#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010024#define CONFIG_DIGSY_MTC 1 /* ... on InterControl digsyMTC board */
Anatolij Gustschin77d43572014-10-21 13:47:04 +020025#define CONFIG_DISPLAY_BOARDINFO
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010026
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027/*
28 * Valid values for CONFIG_SYS_TEXT_BASE are:
29 * 0xFFF00000 boot high (standard configuration)
30 * 0xFE000000 boot low
31 * 0x00100000 boot from RAM (for testing only)
32 */
33#ifndef CONFIG_SYS_TEXT_BASE
34#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
35#endif
36
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010037#define CONFIG_SYS_MPC5XXX_CLKIN 33000000
38
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010039#define CONFIG_SYS_CACHELINE_SIZE 32
40
41/*
42 * Serial console configuration
43 */
44#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 */
45#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
46#define CONFIG_SYS_BAUDRATE_TABLE \
47 { 9600, 19200, 38400, 57600, 115200, 230400 }
48
49/*
50 * PCI Mapping:
51 * 0x40000000 - 0x4fffffff - PCI Memory
52 * 0x50000000 - 0x50ffffff - PCI IO Space
53 */
54#define CONFIG_PCI 1
55#define CONFIG_PCI_PNP 1
56#define CONFIG_PCI_SCAN_SHOW 1
Anatolij Gustschin4fc823d2011-10-13 05:19:17 +000057#define CONFIG_PCI_BOOTDELAY 250
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010058
59#define CONFIG_PCI_MEM_BUS 0x40000000
60#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
61#define CONFIG_PCI_MEM_SIZE 0x10000000
62
63#define CONFIG_PCI_IO_BUS 0x50000000
64#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
65#define CONFIG_PCI_IO_SIZE 0x01000000
66
67/*
68 * Partitions
69 */
70#define CONFIG_DOS_PARTITION
71#define CONFIG_BZIP2
72
73/*
Anatolij Gustschina59996e2011-05-29 21:16:20 +000074 * Video
75 */
76#define CONFIG_VIDEO
77
78#ifdef CONFIG_VIDEO
79#define CONFIG_VIDEO_MB862xx
80#define CONFIG_VIDEO_MB862xx_ACCEL
81#define CONFIG_VIDEO_CORALP
82#define CONFIG_CFB_CONSOLE
83#define CONFIG_VIDEO_LOGO
Anatolij Gustschin348de312011-07-16 10:26:50 +000084#define CONFIG_VIDEO_BMP_LOGO
Anatolij Gustschina59996e2011-05-29 21:16:20 +000085#define CONFIG_VIDEO_SW_CURSOR
86#define CONFIG_VGA_AS_SINGLE_DEVICE
87#define CONFIG_SYS_CONSOLE_IS_IN_ENV
88#define CONFIG_SPLASH_SCREEN
89#define CONFIG_VIDEO_BMP_GZIP
90#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
91
92/* Coral-PA clock frequency, geo and other both 133MHz */
93#define CONFIG_SYS_MB862xx_CCF 0x00050000
94/* Video SDRAM parameters */
95#define CONFIG_SYS_MB862xx_MMR 0x11d7fa72
96#endif
97
98/*
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +010099 * Command line configuration.
100 */
Anatolij Gustschina59996e2011-05-29 21:16:20 +0000101#ifdef CONFIG_VIDEO
102#define CONFIG_CMD_BMP
103#endif
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100104#define CONFIG_CMD_CACHE
105#define CONFIG_CMD_DATE
106#define CONFIG_CMD_DHCP
107#define CONFIG_CMD_DIAG
108#define CONFIG_CMD_EEPROM
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100109#define CONFIG_CMD_EXT2
110#define CONFIG_CMD_FAT
111#define CONFIG_CMD_I2C
112#define CONFIG_CMD_IDE
113#define CONFIG_CMD_IRQ
114#define CONFIG_CMD_MII
115#define CONFIG_CMD_PCI
116#define CONFIG_CMD_PING
117#define CONFIG_CMD_REGINFO
118#define CONFIG_CMD_SAVES
Grzegorz Bernackif1f66ed2009-06-12 11:33:53 +0200119#define CONFIG_CMD_SPI
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100120#define CONFIG_CMD_USB
121
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200122#if (CONFIG_SYS_TEXT_BASE == 0xFF000000)
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100123#define CONFIG_SYS_LOWBOOT 1
124#endif
125
126/*
127 * Autobooting
128 */
129#define CONFIG_BOOTDELAY 1
130
131#undef CONFIG_BOOTARGS
132
Detlev Zundelff276502009-08-05 18:37:45 +0200133#define CONFIG_EXTRA_ENV_SETTINGS \
134 "fw_image=digsyMPC.img\0" \
135 "mtcb_start=mtc led diag orange; run mtcb_1\0" \
136 "mtcb_clearled=for x in user1 user2 usbpwr usbbusy; " \
137 "do mtc led $x; done\0" \
138 "mtcb_1=if mtc key; then run mtcb_clearled mtcb_update; " \
139 "else run mtcb_fw; fi\0" \
140 "mtcb_fw=if bootm ff000000; then echo FIRMWARE OK!; " \
141 "else echo BAD FIRMWARE CRC!; mtc led diag red; fi\0" \
142 "mtcb_update=mtc led user1 orange;" \
143 "while mtc key; do ; done; run mtcb_2;\0" \
144 "mtcb_2=mtc led user1 green 2; usb reset; run mtcb_usb1;\0" \
145 "mtcb_usb1=if fatload usb 0 400000 script.img; " \
146 "then run mtcb_doscript; else run mtcb_usb2; fi\0" \
147 "mtcb_usb2=if fatload usb 0 400000 $fw_image; " \
148 "then run mtcb_dousb; else run mtcb_ide; fi\0" \
149 "mtcb_doscript=run mtcb_usbleds; mtc led user2 orange 2; " \
150 "run mtcb_wait_flickr mtcb_ds_1;\0" \
151 "mtcb_ds_1=if imi 400000; then mtc led usbbusy; " \
152 "source 400000; else run mtcb_error; fi\0" \
153 "mtcb_dousb=run mtcb_usbleds mtcb_wait_flickr mtcb_du_1;\0" \
154 "mtcb_du_1=if imi 400000; then run mtcb_du_2; " \
155 "else run mtcb_error; fi\0" \
156 "mtcb_du_2=run mtcb_clear mtcb_prog; mtc led usbbusy; " \
157 "run mtcb_checkfw\0" \
158 "mtcb_checkfw=if imi ff000000; then run mtcb_success; " \
159 "else run mtcb_error; fi\0" \
160 "mtcb_waitkey=mtc key; until test $? -eq 0; do mtc key; done\0" \
161 "mtcb_wait_flickr=run mtcb_waitkey mtcb_uledflckr\0" \
162 "mtcb_usbleds=mtc led usbpwr green; mtc led usbbusy orange 1;\0"\
163 "mtcb_uledflckr=mtc led user1 orange 11\0" \
164 "mtcb_error=mtc led user1 red\0" \
165 "mtcb_clear=erase ff000000 ff0fffff\0" \
166 "mtcb_prog=cp.b 400000 ff000000 ${filesize}\0" \
167 "mtcb_success=mtc led user1 green\0" \
168 "mtcb_ide=if fatload ide 0 400000 $fw_image;" \
169 "then run mtcb_doide; else run mtcb_error; fi\0" \
170 "mtcb_doide=mtc led user2 green 1;" \
171 "run mtcb_wait_flickr mtcb_di_1;\0" \
172 "mtcb_di_1=if imi 400000; then run mtcb_di_2;" \
173 "else run mtcb_error; fi\0" \
174 "mtcb_di_2=run mtcb_clear; run mtcb_prog mtcb_checkfw\0" \
175 "ramdisk_num_sector=16\0" \
176 "flash_base=ff000000\0" \
177 "flashdisk_size=e00000\0" \
178 "env_sector=fff60000\0" \
179 "flashdisk_start=ff100000\0" \
180 "load_cmd=tftp 400000 digsyMPC.img\0" \
181 "clear_cmd=erase ff000000 ff0fffff\0" \
182 "flash_cmd=cp.b 400000 ff000000 ${filesize}\0" \
183 "update_cmd=run load_cmd; " \
184 "iminfo 400000; " \
185 "run clear_cmd flash_cmd; " \
186 "iminfo ff000000\0" \
187 "spi_driver=yes\0" \
188 "spi_watchdog=no\0" \
189 "ftps_start=yes\0" \
190 "ftps_user1=admin\0" \
191 "ftps_pass1=admin\0" \
192 "ftps_base1=/\0" \
193 "ftps_home1=/\0" \
194 "plc_sio_srv=no\0" \
195 "plc_sio_baud=57600\0" \
196 "plc_sio_parity=no\0" \
197 "plc_sio_stop=1\0" \
198 "plc_sio_com=2\0" \
199 "plc_eth_srv=yes\0" \
200 "plc_eth_port=1200\0" \
201 "plc_root=/ide/\0" \
202 "diag_level=0\0" \
203 "webvisu=no\0" \
204 "plc_can1_routing=no\0" \
205 "plc_can1_baudrate=250\0" \
206 "plc_can2_routing=no\0" \
207 "plc_can2_baudrate=250\0" \
208 "plc_can3_routing=no\0" \
209 "plc_can3_baudrate=250\0" \
210 "plc_can4_routing=no\0" \
211 "plc_can4_baudrate=250\0" \
212 "netdev=eth0\0" \
213 "console=ttyPSC0\0" \
214 "kernel_addr_r=400000\0" \
215 "fdt_addr_r=600000\0" \
216 "nfsargs=setenv bootargs root=/dev/nfs rw " \
217 "nfsroot=${serverip}:${rootpath}\0" \
218 "addip=setenv bootargs ${bootargs} " \
219 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
220 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100221 "addcons=setenv bootargs ${bootargs} console=${console},${baudrate}\0"\
Detlev Zundelff276502009-08-05 18:37:45 +0200222 "rootpath=/opt/eldk/ppc_6xx\0" \
223 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
224 "tftp ${fdt_addr_r} ${fdt_file};" \
225 "run nfsargs addip addcons;" \
226 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
227 "load=tftp 200000 ${u-boot}\0" \
228 "update=protect off FFF00000 +${filesize};" \
229 "erase FFF00000 +${filesize};" \
230 "cp.b 200000 FFF00000 ${filesize};" \
231 "protect on FFF00000 +${filesize}\0" \
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100232 ""
233
Detlev Zundelff276502009-08-05 18:37:45 +0200234#define CONFIG_BOOTCOMMAND "run mtcb_start"
235
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100236/*
Grzegorz Bernackif1f66ed2009-06-12 11:33:53 +0200237 * SPI configuration
238 */
239#define CONFIG_HARD_SPI 1
240#define CONFIG_MPC52XX_SPI 1
241
242/*
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100243 * I2C configuration
244 */
245#define CONFIG_HARD_I2C 1
246#define CONFIG_SYS_I2C_MODULE 1
247#define CONFIG_SYS_I2C_SPEED 100000
248#define CONFIG_SYS_I2C_SLAVE 0x7F
249
250/*
251 * EEPROM configuration
252 */
253#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
254#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
255#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
256#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
257
258/*
259 * RTC configuration
260 */
Heiko Schocher466f0132011-01-13 08:25:00 +0100261#if defined(CONFIG_DIGSY_REV5)
262#define CONFIG_SYS_I2C_RTC_ADDR 0x56
263#define CONFIG_RTC_RV3029
Heiko Schochera01ebd92011-03-28 09:24:23 +0200264/* Enable 5k Ohm trickle charge resistor */
265#define CONFIG_SYS_RV3029_TCR 0x20
Heiko Schocher466f0132011-01-13 08:25:00 +0100266#else
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100267#define CONFIG_RTC_DS1337
268#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Werner Pfisterc569ad62009-09-21 14:49:56 +0200269#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */
Heiko Schocher466f0132011-01-13 08:25:00 +0100270#endif
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100271
272/*
273 * Flash configuration
274 */
275#define CONFIG_SYS_FLASH_CFI 1
276#define CONFIG_FLASH_CFI_DRIVER 1
277
Heiko Schocher466f0132011-01-13 08:25:00 +0100278#if defined(CONFIG_DIGSY_REV5)
279#define CONFIG_SYS_FLASH_BASE 0xFE000000
280#define CONFIG_SYS_FLASH_BASE_CS1 0xFC000000
281#define CONFIG_SYS_MAX_FLASH_BANKS 2
Heiko Schocher927d2ce2011-01-21 07:23:35 +0100282#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
283 CONFIG_SYS_FLASH_BASE_CS1}
Heiko Schocher466f0132011-01-13 08:25:00 +0100284#define CONFIG_SYS_UPDATE_FLASH_SIZE
285#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
286#else
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100287#define CONFIG_SYS_FLASH_BASE 0xFF000000
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100288#define CONFIG_SYS_MAX_FLASH_BANKS 1
Heiko Schocher466f0132011-01-13 08:25:00 +0100289#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
290#endif
291
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100292#define CONFIG_SYS_MAX_FLASH_SECT 256
293#define CONFIG_FLASH_16BIT
294#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Heiko Schocher466f0132011-01-13 08:25:00 +0100295#define CONFIG_SYS_FLASH_SIZE 0x01000000
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100296#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
297#define CONFIG_SYS_FLASH_WRITE_TOUT 500
298
299#define CONFIG_OF_LIBFDT 1
300#define CONFIG_OF_BOARD_SETUP 1
301
302#define OF_CPU "PowerPC,5200@0"
303#define OF_SOC "soc5200@f0000000"
304#define OF_TBCLK (bd->bi_busfreq / 4)
305
306#define CONFIG_BOARD_EARLY_INIT_R
307#define CONFIG_MISC_INIT_R
308
309/*
310 * Environment settings
311 */
312#define CONFIG_ENV_IS_IN_FLASH 1
313#if defined(CONFIG_LOWBOOT)
314#define CONFIG_ENV_ADDR 0xFF060000
315#else /* CONFIG_LOWBOOT */
316#define CONFIG_ENV_ADDR 0xFFF60000
317#endif /* CONFIG_LOWBOOT */
318#define CONFIG_ENV_SIZE 0x10000
319#define CONFIG_ENV_SECT_SIZE 0x20000
320#define CONFIG_ENV_OVERWRITE 1
321
322/*
323 * Memory map
324 */
325#define CONFIG_SYS_MBAR 0xF0000000
326#define CONFIG_SYS_SDRAM_BASE 0x00000000
327#if !defined(CONFIG_SYS_LOWBOOT)
328#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
329#else
330#define CONFIG_SYS_DEFAULT_MBAR 0xF0000000
331#endif
332
333/*
334 * Use SRAM until RAM will be available
335 */
336#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denk553f0982010-10-26 13:32:32 +0200337#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100338
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100339#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200340 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100341#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
342
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200343#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100344#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
345#define CONFIG_SYS_RAMBOOT 1
346#endif
347
348#define CONFIG_SYS_MONITOR_LEN (256 << 10)
349#define CONFIG_SYS_MALLOC_LEN (4096 << 10)
350#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
351
352/*
353 * Ethernet configuration
354 */
355#define CONFIG_MPC5xxx_FEC 1
356#define CONFIG_MPC5xxx_FEC_MII100
Heiko Schocher1b414932011-04-03 20:10:20 +0000357#if defined(CONFIG_DIGSY_REV5)
358#define CONFIG_PHY_ADDR 0x01
359#else
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100360#define CONFIG_PHY_ADDR 0x00
Heiko Schocher1b414932011-04-03 20:10:20 +0000361#endif
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100362#define CONFIG_PHY_RESET_DELAY 1000
363
364#define CONFIG_NETCONSOLE /* include NetConsole support */
365
366/*
367 * GPIO configuration
Grzegorz Bernacki12602332009-06-12 11:33:55 +0200368 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1)
369 * Bit 0 (mask 0x80000000) : 0x1
370 * SPI on Tmr2/3/4/5 pins
371 * Bit 2:3 (mask 0x30000000) : 0x2
372 * ATA cs0/1 on csb_4/5
373 * Bit 6:7 (mask 0x03000000) : 0x2
374 * Ethernet 100Mbit with MD
375 * Bits 12:15 (mask 0x000f0000): 0x5
376 * USB - Two UARTs
377 * Bits 18:19 (mask 0x00003000) : 0x2
378 * PSC3 - USB2 on PSC3
379 * Bits 20:23 (mask 0x00000f00) : 0x1
380 * PSC2 - CAN1&2 on PSC2 pins
381 * Bits 25:27 (mask 0x00000070) : 0x1
382 * PSC1 - AC97 functionality
383 * Bits 29:31 (mask 0x00000007) : 0x2
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100384 */
385#define CONFIG_SYS_GPS_PORT_CONFIG 0xA2552112
386
387/*
388 * Miscellaneous configurable options
389 */
390#define CONFIG_SYS_LONGHELP
391#define CONFIG_AUTO_COMPLETE 1
Grzegorz Bernackia781de12009-06-17 16:20:14 +0200392#define CONFIG_CMDLINE_EDITING 1
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100393#define CONFIG_SYS_HUSH_PARSER
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100394
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100395#define CONFIG_LOOPW 1
396#define CONFIG_MX_CYCLIC 1
397#define CONFIG_ZERO_BOOTDELAY_CHECK
398
399#define CONFIG_SYS_CBSIZE 1024
400#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
401#define CONFIG_SYS_MAXARGS 32
402#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
403
404#define CONFIG_SYS_ALT_MEMTEST
405#define CONFIG_SYS_MEMTEST_SCRATCH 0x00001000
406#define CONFIG_SYS_MEMTEST_START 0x00010000
407#define CONFIG_SYS_MEMTEST_END 0x019fffff
408
409#define CONFIG_SYS_LOAD_ADDR 0x00100000
410
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100411/*
412 * Various low-level settings
413 */
414#define CONFIG_SYS_SDRAM_CS1 1
415#define CONFIG_SYS_XLB_PIPELINING 1
416
417#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
418#define CONFIG_SYS_HID0_FINAL HID0_ICE
419
420#if defined(CONFIG_SYS_LOWBOOT)
421#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
422#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
423#define CONFIG_SYS_BOOTCS_CFG 0x0002DD00
424#endif
425
426#define CONFIG_SYS_CS4_START 0x60000000
427#define CONFIG_SYS_CS4_SIZE 0x1000
428#define CONFIG_SYS_CS4_CFG 0x0008FC00
429
430#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
431#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
432#define CONFIG_SYS_CS0_CFG 0x0002DD00
433
Heiko Schocher466f0132011-01-13 08:25:00 +0100434#if defined(CONFIG_DIGSY_REV5)
435#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE_CS1
436#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
437#define CONFIG_SYS_CS1_CFG 0x0002DD00
438#endif
439
Grzegorz Bernacki5c4fa9b2009-03-17 10:06:40 +0100440#define CONFIG_SYS_CS_BURST 0x00000000
441#define CONFIG_SYS_CS_DEADCYCLE 0x11111111
442
443#if !defined(CONFIG_SYS_LOWBOOT)
444#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
445#else
446#define CONFIG_SYS_RESET_ADDRESS 0xff000100
447#endif
448
449/*
450 * USB
451 */
452#define CONFIG_USB_OHCI_NEW
453#define CONFIG_SYS_OHCI_BE_CONTROLLER
454#define CONFIG_USB_STORAGE
455
456#define CONFIG_USB_CLOCK 0x00013333
457#define CONFIG_USB_CONFIG 0x00002000
458
459#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
460#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
461#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
462#define CONFIG_SYS_USB_OHCI_CPU_INIT
463
464/*
465 * IDE/ATA
466 */
467#define CONFIG_IDE_RESET
468#define CONFIG_IDE_PREINIT
469
470#define CONFIG_SYS_ATA_CS_ON_I2C2
471#define CONFIG_SYS_IDE_MAXBUS 1
472#define CONFIG_SYS_IDE_MAXDEVICE 1
473
474#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
475#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
476#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
477#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
478#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
479#define CONFIG_SYS_ATA_STRIDE 4
480
481#define CONFIG_ATAPI 1
482#define CONFIG_LBA48 1
483
484#endif /* __CONFIG_H */