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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / b53f19061fc4d0a18e58fff84d68f465b1d387ee / . / arch / arm / dts / k3-am654-r5-base-board.dts
blob: d75c7bf3fe6625ff99b8d7e1f44f7b2684b68c5a [file] [log] [blame]
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
Nishanth Menona94a4072023-11-01 15:56:03 -0500[diff] [blame]3 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]4 */
5
6/dts-v1/;
7
8#include "k3-am654.dtsi"
James Doublesind5e08fd2019-10-07 14:04:25 +0530[diff] [blame]9#include "k3-am654-base-board-ddr4-1600MTs.dtsi"
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]10#include "k3-am654-ddr.dtsi"
11
12/ {
13 compatible = "ti,am654-evm", "ti,am654";
14 model = "Texas Instruments AM654 R5 Base Board";
15
16 aliases {
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]17 ethernet0 = &cpsw_port1;
18 remoteproc0 = &sysctrler;
19 remoteproc1 = &a53_0;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]20 serial0 = &wkup_uart0;
Andreas Dannenberg20a22962019-08-15 15:55:30 -0500[diff] [blame]21 serial1 = &mcu_uart0;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]22 serial2 = &main_uart0;
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]23 spi0 = &ospi0;
24 spi1 = &ospi1;
25 usb0 = &usb0;
26 usb1 = &usb1;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]27 };
28
29 chosen {
30 stdout-path = "serial2:115200n8";
31 tick-timer = &timer1;
32 };
33
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]34 a53_0: a53@0 {
35 compatible = "ti,am654-rproc";
36 reg = <0x0 0x00a90000 0x0 0x10>;
Lokesh Vutla355be912019-06-07 19:24:47 +0530[diff] [blame]37 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
38 <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]39 resets = <&k3_reset 202 0>;
Nishanth Menon965db9f2021-01-06 13:20:31 -0600[diff] [blame]40 clocks = <&k3_clks 61 0>;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]41 assigned-clocks = <&k3_clks 202 0>;
42 assigned-clock-rates = <800000000>;
43 ti,sci = <&dmsc>;
44 ti,sci-proc-id = <32>;
45 ti,sci-host-id = <10>;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]47 };
48
49 vtt_supply: vtt_supply {
50 compatible = "regulator-gpio";
51 regulator-name = "vtt";
52 regulator-min-microvolt = <0>;
53 regulator-max-microvolt = <3300000>;
54 gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
55 states = <0 0x0 3300000 0x1>;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]56 bootph-pre-ram;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]57 };
58};
59
60&cbass_main {
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]61 bootph-pre-ram;
62
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]63 timer1: timer@40400000 {
64 compatible = "ti,omap5430-timer";
65 reg = <0x0 0x40400000 0x0 0x80>;
66 ti,timer-alwon;
67 clock-frequency = <25000000>;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]68 bootph-all;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]69 };
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]70
71 main_navss: bus@30800000 {
72 bootph-pre-ram;
73 };
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]74};
75
76&cbass_mcu {
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]77 bootph-pre-ram;
78
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]79 mcu_secproxy: secproxy@28380000 {
80 compatible = "ti,am654-secure-proxy";
81 reg = <0x0 0x2a380000 0x0 0x80000>,
82 <0x0 0x2a400000 0x0 0x80000>,
83 <0x0 0x2a480000 0x0 0x80000>;
84 reg-names = "rt", "scfg", "target_data";
85 #mbox-cells = <1>;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]86 bootph-pre-ram;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]87 };
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]88
89 mcu_navss: bus@28380000 {
90 bootph-pre-ram;
91
92 ringacc@2b800000 {
93 reg = <0x0 0x2b800000 0x0 0x400000>,
94 <0x0 0x2b000000 0x0 0x400000>,
95 <0x0 0x28590000 0x0 0x100>,
96 <0x0 0x2a500000 0x0 0x40000>,
97 <0x0 0x28440000 0x0 0x40000>;
98 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
99 bootph-pre-ram;
100 ti,dma-ring-reset-quirk;
101 };
102
103 dma-controller@285c0000 {
104 reg = <0x0 0x285c0000 0x0 0x100>,
105 <0x0 0x284c0000 0x0 0x4000>,
106 <0x0 0x2a800000 0x0 0x40000>,
107 <0x0 0x284a0000 0x0 0x4000>,
108 <0x0 0x2aa00000 0x0 0x40000>,
109 <0x0 0x28400000 0x0 0x2000>;
110 reg-names = "gcfg", "rchan", "rchanrt", "tchan",
111 "tchanrt", "rflow";
112 bootph-pre-ram;
113 };
114 };
115};
116
117&k3_pds {
118 bootph-pre-ram;
119};
120
121&k3_clks {
122 bootph-pre-ram;
123};
124
125&k3_reset {
126 bootph-pre-ram;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]127};
128
Lokesh Vutlae4978762021-02-01 11:26:39 +0530[diff] [blame]129&wkup_gpio0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]130 bootph-pre-ram;
Lokesh Vutlae4978762021-02-01 11:26:39 +0530[diff] [blame]131};
132
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]133&secure_proxy_main {
134 bootph-pre-ram;
135};
136
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]137&cbass_wakeup {
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]138 bootph-pre-ram;
139
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]140 sysctrler: sysctrler {
141 compatible = "ti,am654-system-controller";
142 mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
143 mbox-names = "tx", "rx";
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]144 bootph-pre-ram;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]145 };
146
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530[diff] [blame]147 clk_200mhz: dummy_clock {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <200000000>;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]151 bootph-pre-ram;
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530[diff] [blame]152 };
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]153
154 chipid@43000014 {
155 bootph-pre-ram;
156 };
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]157};
158
159&dmsc {
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]160 bootph-pre-ram;
161
Andreas Dannenberg12df71c2019-04-25 12:27:02 -0500[diff] [blame]162 mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]163 mbox-names = "tx", "rx", "notify";
164 ti,host-id = <4>;
165 ti,secure-host;
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]166
167 k3_sysreset: sysreset-controller {
168 compatible = "ti,sci-sysreset";
169 bootph-pre-ram;
170 };
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]171};
172
173&wkup_uart0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]174 bootph-pre-ram;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]175 pinctrl-names = "default";
176 pinctrl-0 = <&wkup_uart0_pins_default>;
177 status = "okay";
178};
179
Andreas Dannenberg20a22962019-08-15 15:55:30 -0500[diff] [blame]180&mcu_uart0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]181 bootph-pre-ram;
Andreas Dannenberg20a22962019-08-15 15:55:30 -0500[diff] [blame]182 pinctrl-names = "default";
183 pinctrl-0 = <&mcu_uart0_pins_default>;
184 clock-frequency = <48000000>;
Lokesh Vutlae4978762021-02-01 11:26:39 +0530[diff] [blame]185 /delete-property/ power-domains;
Andreas Dannenberg20a22962019-08-15 15:55:30 -0500[diff] [blame]186 status = "okay";
187};
188
Lokesh Vutla355be912019-06-07 19:24:47 +0530[diff] [blame]189&main_uart0 {
Lokesh Vutlae4978762021-02-01 11:26:39 +0530[diff] [blame]190 pinctrl-names = "default";
191 pinctrl-0 = <&main_uart0_pins_default>;
Lokesh Vutla355be912019-06-07 19:24:47 +0530[diff] [blame]192 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
Lokesh Vutlae4978762021-02-01 11:26:39 +0530[diff] [blame]193 status = "okay";
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]194 bootph-pre-ram;
Lokesh Vutla355be912019-06-07 19:24:47 +0530[diff] [blame]195};
196
Tero Kristo56adc662019-10-24 15:00:57 +0530[diff] [blame]197&wkup_vtm0 {
Lokesh Vutlae4978762021-02-01 11:26:39 +0530[diff] [blame]198 compatible = "ti,am654-vtm", "ti,am654-avs";
Tero Kristo56adc662019-10-24 15:00:57 +0530[diff] [blame]199 vdd-supply-3 = <&vdd_mpu>;
200 vdd-supply-4 = <&vdd_mpu>;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]201 bootph-pre-ram;
Tero Kristo56adc662019-10-24 15:00:57 +0530[diff] [blame]202};
203
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]204&wkup_pmx0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]205 bootph-pre-ram;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]206 wkup_uart0_pins_default: wkup_uart0_pins_default {
207 pinctrl-single,pins = <
Andreas Dannenberg7202af92019-04-29 12:56:44 -0500[diff] [blame]208 AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT, 0) /* (AB1) WKUP_UART0_RXD */
209 AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT, 0) /* (AB5) WKUP_UART0_TXD */
210 AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT, 1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
211 AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]212 >;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]213 bootph-pre-ram;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]214 };
215
216 wkup_vtt_pins_default: wkup_vtt_pins_default {
217 pinctrl-single,pins = <
Andreas Dannenberg7202af92019-04-29 12:56:44 -0500[diff] [blame]218 AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP, 7) /* WKUP_GPIO0_28 */
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]219 >;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]220 bootph-pre-ram;
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]221 };
Andreas Dannenberg7e0363b2019-06-04 18:08:15 -0500[diff] [blame]222
Andreas Dannenberg20a22962019-08-15 15:55:30 -0500[diff] [blame]223 mcu_uart0_pins_default: mcu_uart0_pins_default {
224 pinctrl-single,pins = <
225 AM65X_WKUP_IOPAD(0x0044, PIN_INPUT, 4) /* (P4) MCU_OSPI1_D1.MCU_UART0_RXD */
226 AM65X_WKUP_IOPAD(0x0048, PIN_OUTPUT, 4) /* (P5) MCU_OSPI1_D2.MCU_UART0_TXD */
227 AM65X_WKUP_IOPAD(0x004C, PIN_INPUT, 4) /* (P1) MCU_OSPI1_D3.MCU_UART0_CTSn */
228 AM65X_WKUP_IOPAD(0x0054, PIN_OUTPUT, 4) /* (N3) MCU_OSPI1_CSn1.MCU_UART0_RTSn */
229 >;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]230 bootph-pre-ram;
Andreas Dannenberg20a22962019-08-15 15:55:30 -0500[diff] [blame]231 };
232
Andreas Dannenberg7e0363b2019-06-04 18:08:15 -0500[diff] [blame]233 wkup_i2c0_pins_default: wkup-i2c0-pins-default {
234 pinctrl-single,pins = <
235 AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
236 AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
237 >;
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]238 bootph-pre-ram;
Andreas Dannenberg7e0363b2019-06-04 18:08:15 -0500[diff] [blame]239 };
Vignesh Raghavendra9e9dfc12020-02-04 11:09:51 +0530[diff] [blame]240
241 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins_default {
242 pinctrl-single,pins = <
243 AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */
244 AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */
245 AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */
246 AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */
247 AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */
248 AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */
249 AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */
250 AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */
251 AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */
252 AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */
253 AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */
254 >;
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]255 bootph-pre-ram;
Vignesh Raghavendra9e9dfc12020-02-04 11:09:51 +0530[diff] [blame]256 };
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]257};
258
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530[diff] [blame]259&main_pmx0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]260 bootph-pre-ram;
Lokesh Vutlae4978762021-02-01 11:26:39 +0530[diff] [blame]261 main_uart0_pins_default: main-uart0-pins-default {
262 pinctrl-single,pins = <
263 AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */
264 AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */
265 AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */
266 AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */
267 >;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]268 bootph-pre-ram;
Lokesh Vutlae4978762021-02-01 11:26:39 +0530[diff] [blame]269 };
270
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530[diff] [blame]271 main_mmc0_pins_default: main_mmc0_pins_default {
272 pinctrl-single,pins = <
273 AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
274 AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
275 AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
276 AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
277 AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
278 AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
279 AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
280 AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
281 AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
282 AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
283 AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
284 >;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]285 bootph-pre-ram;
Faiz Abbas2121c7e2021-02-04 15:10:56 +0530[diff] [blame]286 };
287
288 main_mmc1_pins_default: main_mmc1_pins_default {
289 pinctrl-single,pins = <
290 AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
291 AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
292 AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
293 AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
294 AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
295 AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
296 AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
297 AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
298 >;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]299 bootph-pre-ram;
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530[diff] [blame]300 };
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]301
302 usb0_pins_default: usb0_pins_default {
303 pinctrl-single,pins = <
304 AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
305 >;
306 bootph-pre-ram;
307 };
308};
309
310&main_pmx1 {
311 bootph-pre-ram;
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530[diff] [blame]312};
313
Lokesh Vutla00b34e92018-11-02 19:51:09 +0530[diff] [blame]314&memorycontroller {
315 vtt-supply = <&vtt_supply>;
316 pinctrl-names = "default";
317 pinctrl-0 = <&wkup_vtt_pins_default>;
318};
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530[diff] [blame]319
320&sdhci0 {
321 clock-names = "clk_xin";
322 clocks = <&clk_200mhz>;
Faiz Abbas2121c7e2021-02-04 15:10:56 +0530[diff] [blame]323 pinctrl-0 = <&main_mmc0_pins_default>;
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530[diff] [blame]324 /delete-property/ power-domains;
325 ti,driver-strength-ohm = <50>;
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]326 bootph-pre-ram;
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530[diff] [blame]327};
328
329&sdhci1 {
330 clock-names = "clk_xin";
331 clocks = <&clk_200mhz>;
Faiz Abbas2121c7e2021-02-04 15:10:56 +0530[diff] [blame]332 pinctrl-0 = <&main_mmc1_pins_default>;
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530[diff] [blame]333 /delete-property/ power-domains;
Faiz Abbasbbcfaad2019-06-11 00:43:36 +0530[diff] [blame]334 ti,driver-strength-ohm = <50>;
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]335 bootph-pre-ram;
Faiz Abbas3a1a0df2019-06-11 00:43:31 +0530[diff] [blame]336};
Andreas Dannenberg7e0363b2019-06-04 18:08:15 -0500[diff] [blame]337
338&wkup_i2c0 {
339 pinctrl-names = "default";
340 pinctrl-0 = <&wkup_i2c0_pins_default>;
341 clock-frequency = <400000>;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]342 bootph-pre-ram;
Tero Kristoc5f73d12019-10-24 15:00:56 +0530[diff] [blame]343
344 vdd_mpu: tps62363@60 {
345 compatible = "ti,tps62363";
346 reg = <0x60>;
347 regulator-name = "VDD_MPU";
348 regulator-min-microvolt = <500000>;
349 regulator-max-microvolt = <1770000>;
350 regulator-always-on;
351 regulator-boot-on;
352 ti,vsel0-state-high;
353 ti,vsel1-state-high;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]354 bootph-pre-ram;
Tero Kristoc5f73d12019-10-24 15:00:56 +0530[diff] [blame]355 };
Andreas Dannenberg7e0363b2019-06-04 18:08:15 -0500[diff] [blame]356};
Vignesh Raghavendra9e9dfc12020-02-04 11:09:51 +0530[diff] [blame]357
358&ospi0 {
359 pinctrl-names = "default";
360 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]361 bootph-pre-ram;
Vignesh Raghavendra9e9dfc12020-02-04 11:09:51 +0530[diff] [blame]362
363 reg = <0x0 0x47040000 0x0 0x100>,
364 <0x0 0x50000000 0x0 0x8000000>;
365
366 flash@0{
367 compatible = "jedec,spi-nor";
368 reg = <0x0>;
369 spi-tx-bus-width = <1>;
370 spi-rx-bus-width = <8>;
Vignesh Raghavendrad5a1f4f2020-04-02 18:59:12 +0530[diff] [blame]371 spi-max-frequency = <50000000>;
Vignesh Raghavendra9e9dfc12020-02-04 11:09:51 +0530[diff] [blame]372 cdns,tshsl-ns = <60>;
373 cdns,tsd2d-ns = <60>;
374 cdns,tchsh-ns = <60>;
375 cdns,tslch-ns = <60>;
376 cdns,read-delay = <0>;
377 #address-cells = <1>;
378 #size-cells = <1>;
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]379 bootph-pre-ram;
Vignesh Raghavendra9e9dfc12020-02-04 11:09:51 +0530[diff] [blame]380 };
381};
Faiz Abbas5251eb12020-08-03 11:35:11 +0530[diff] [blame]382
383&main_pmx0 {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]384 bootph-pre-ram;
Faiz Abbas5251eb12020-08-03 11:35:11 +0530[diff] [blame]385 usb0_pins_default: usb0_pins_default {
386 pinctrl-single,pins = <
387 AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
388 >;
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]389 bootph-pre-ram;
Faiz Abbas5251eb12020-08-03 11:35:11 +0530[diff] [blame]390 };
391};
392
393&dwc3_0 {
394 status = "okay";
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]395 bootph-pre-ram;
Aswath Govindraju750d8472022-05-18 16:49:12 +0530[diff] [blame]396 /delete-property/ clocks;
Faiz Abbas5251eb12020-08-03 11:35:11 +0530[diff] [blame]397 /delete-property/ power-domains;
398 /delete-property/ assigned-clocks;
399 /delete-property/ assigned-clock-parents;
400};
401
402&usb0_phy {
403 status = "okay";
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]404 bootph-pre-ram;
Faiz Abbas5251eb12020-08-03 11:35:11 +0530[diff] [blame]405 /delete-property/ clocks;
406};
407
408&usb0 {
409 pinctrl-names = "default";
410 pinctrl-0 = <&usb0_pins_default>;
411 dr_mode = "peripheral";
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]412 bootph-pre-ram;
Faiz Abbas5251eb12020-08-03 11:35:11 +0530[diff] [blame]413};
414
415&scm_conf {
Simon Glass8c103c32023-02-13 08:56:33 -0700[diff] [blame]416 bootph-pre-ram;
Faiz Abbas5251eb12020-08-03 11:35:11 +0530[diff] [blame]417};
Bryan Brattlofb53f1902023-12-29 11:47:00 -0600[diff] [blame^]418
419&davinci_mdio {
420 phy0: ethernet-phy@0 {
421 reg = <0>;
422 /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
423 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
424 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
425 };
426};
427
428&mcu_cpsw {
429 reg = <0x0 0x46000000 0x0 0x200000>,
430 <0x0 0x40f00200 0x0 0x2>;
431 reg-names = "cpsw_nuss", "mac_efuse";
432 /delete-property/ ranges;
433
434 cpsw-phy-sel@40f04040 {
435 compatible = "ti,am654-cpsw-phy-sel";
436 reg= <0x0 0x40f04040 0x0 0x4>;
437 reg-names = "gmii-sel";
438 };
439};
440
441&usb1 {
442 dr_mode = "peripheral";
443};
444
445&fss {
446 bootph-pre-ram;
447};