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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Lei Wenaf62a552011-06-28 21:50:06 +00002/*
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
5 *
Lei Wenaf62a552011-06-28 21:50:06 +00006 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
8 */
9
10#include <common.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070011#include <cpu_func.h>
Faiz Abbas3d296362019-06-11 00:43:34 +053012#include <dm.h>
Simon Glass2a809092016-06-12 23:30:27 -060013#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060014#include <log.h>
Lei Wenaf62a552011-06-28 21:50:06 +000015#include <malloc.h>
16#include <mmc.h>
17#include <sdhci.h>
Simon Glass90526e92020-05-10 11:39:56 -060018#include <asm/cache.h>
Simon Glasscd93d622020-05-10 11:40:13 -060019#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060020#include <linux/delay.h>
Masahiro Yamada58d8ace2020-02-14 16:40:26 +090021#include <linux/dma-mapping.h>
Jaehoon Chungfac8bfd2020-03-27 13:08:00 +090022#include <phys2bus.h>
Lei Wenaf62a552011-06-28 21:50:06 +000023
Lei Wenaf62a552011-06-28 21:50:06 +000024static void sdhci_reset(struct sdhci_host *host, u8 mask)
25{
26 unsigned long timeout;
27
28 /* Wait max 100 ms */
29 timeout = 100;
30 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
31 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
32 if (timeout == 0) {
Darwin Rambo30e6d972013-12-19 15:13:25 -080033 printf("%s: Reset 0x%x never completed.\n",
34 __func__, (int)mask);
Lei Wenaf62a552011-06-28 21:50:06 +000035 return;
36 }
37 timeout--;
38 udelay(1000);
39 }
40}
41
42static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
43{
44 int i;
45 if (cmd->resp_type & MMC_RSP_136) {
46 /* CRC is stripped so we need to do some shifting. */
47 for (i = 0; i < 4; i++) {
48 cmd->response[i] = sdhci_readl(host,
49 SDHCI_RESPONSE + (3-i)*4) << 8;
50 if (i != 3)
51 cmd->response[i] |= sdhci_readb(host,
52 SDHCI_RESPONSE + (3-i)*4-1);
53 }
54 } else {
55 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
56 }
57}
58
59static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
60{
61 int i;
62 char *offs;
63 for (i = 0; i < data->blocksize; i += 4) {
64 offs = data->dest + i;
65 if (data->flags == MMC_DATA_READ)
66 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
67 else
68 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
69 }
70}
Faiz Abbas37cb6262019-04-16 23:06:58 +053071
72#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
Masahiro Yamada58d8ace2020-02-14 16:40:26 +090073static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
74 u16 len, bool end)
Faiz Abbas37cb6262019-04-16 23:06:58 +053075{
76 struct sdhci_adma_desc *desc;
77 u8 attr;
78
79 desc = &host->adma_desc_table[host->desc_slot];
80
81 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
82 if (!end)
83 host->desc_slot++;
84 else
85 attr |= ADMA_DESC_ATTR_END;
86
87 desc->attr = attr;
88 desc->len = len;
89 desc->reserved = 0;
Masahiro Yamada58d8ace2020-02-14 16:40:26 +090090 desc->addr_lo = lower_32_bits(dma_addr);
Faiz Abbas37cb6262019-04-16 23:06:58 +053091#ifdef CONFIG_DMA_ADDR_T_64BIT
Masahiro Yamada58d8ace2020-02-14 16:40:26 +090092 desc->addr_hi = upper_32_bits(dma_addr);
Faiz Abbas37cb6262019-04-16 23:06:58 +053093#endif
94}
95
96static void sdhci_prepare_adma_table(struct sdhci_host *host,
97 struct mmc_data *data)
98{
99 uint trans_bytes = data->blocksize * data->blocks;
100 uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
101 int i = desc_count;
Masahiro Yamada58d8ace2020-02-14 16:40:26 +0900102 dma_addr_t dma_addr = host->start_addr;
Faiz Abbas37cb6262019-04-16 23:06:58 +0530103
104 host->desc_slot = 0;
105
Faiz Abbas37cb6262019-04-16 23:06:58 +0530106 while (--i) {
Masahiro Yamada58d8ace2020-02-14 16:40:26 +0900107 sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
108 dma_addr += ADMA_MAX_LEN;
Faiz Abbas37cb6262019-04-16 23:06:58 +0530109 trans_bytes -= ADMA_MAX_LEN;
110 }
111
Masahiro Yamada58d8ace2020-02-14 16:40:26 +0900112 sdhci_adma_desc(host, dma_addr, trans_bytes, true);
Faiz Abbas37cb6262019-04-16 23:06:58 +0530113
114 flush_cache((dma_addr_t)host->adma_desc_table,
115 ROUND(desc_count * sizeof(struct sdhci_adma_desc),
116 ARCH_DMA_MINALIGN));
117}
118#elif defined(CONFIG_MMC_SDHCI_SDMA)
119static void sdhci_prepare_adma_table(struct sdhci_host *host,
120 struct mmc_data *data)
121{}
122#endif
123#if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
Faiz Abbas6d6af202019-04-16 23:06:57 +0530124static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
125 int *is_aligned, int trans_bytes)
126{
Jaehoon Chung804c7f42012-09-20 20:31:55 +0000127 unsigned char ctrl;
Masahiro Yamada58d8ace2020-02-14 16:40:26 +0900128 void *buf;
Faiz Abbas6d6af202019-04-16 23:06:57 +0530129
130 if (data->flags == MMC_DATA_READ)
Masahiro Yamada58d8ace2020-02-14 16:40:26 +0900131 buf = data->dest;
Faiz Abbas6d6af202019-04-16 23:06:57 +0530132 else
Masahiro Yamada58d8ace2020-02-14 16:40:26 +0900133 buf = (void *)data->src;
Faiz Abbas6d6af202019-04-16 23:06:57 +0530134
Faiz Abbas37cb6262019-04-16 23:06:58 +0530135 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
136 ctrl &= ~SDHCI_CTRL_DMA_MASK;
137 if (host->flags & USE_ADMA64)
138 ctrl |= SDHCI_CTRL_ADMA64;
139 else if (host->flags & USE_ADMA)
140 ctrl |= SDHCI_CTRL_ADMA32;
141 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
142
Masahiro Yamada58d8ace2020-02-14 16:40:26 +0900143 if (host->flags & USE_SDMA &&
144 (host->force_align_buffer ||
145 (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
146 ((unsigned long)buf & 0x7) != 0x0))) {
147 *is_aligned = 0;
148 if (data->flags != MMC_DATA_READ)
149 memcpy(host->align_buffer, buf, trans_bytes);
150 buf = host->align_buffer;
151 }
152
153 host->start_addr = dma_map_single(buf, trans_bytes,
154 mmc_get_dma_dir(data));
155
Faiz Abbas37cb6262019-04-16 23:06:58 +0530156 if (host->flags & USE_SDMA) {
Jaehoon Chungfac8bfd2020-03-27 13:08:00 +0900157 sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
158 SDHCI_DMA_ADDRESS);
Faiz Abbas37cb6262019-04-16 23:06:58 +0530159 } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
160 sdhci_prepare_adma_table(host, data);
161
Masahiro Yamadaa2b02212020-02-14 16:40:23 +0900162 sdhci_writel(host, lower_32_bits(host->adma_addr),
163 SDHCI_ADMA_ADDRESS);
Faiz Abbas37cb6262019-04-16 23:06:58 +0530164 if (host->flags & USE_ADMA64)
Masahiro Yamadaa2b02212020-02-14 16:40:23 +0900165 sdhci_writel(host, upper_32_bits(host->adma_addr),
Faiz Abbas37cb6262019-04-16 23:06:58 +0530166 SDHCI_ADMA_ADDRESS_HI);
Faiz Abbas6d6af202019-04-16 23:06:57 +0530167 }
Faiz Abbas6d6af202019-04-16 23:06:57 +0530168}
169#else
170static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
171 int *is_aligned, int trans_bytes)
172{}
173#endif
174static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
175{
176 dma_addr_t start_addr = host->start_addr;
177 unsigned int stat, rdy, mask, timeout, block = 0;
178 bool transfer_done = false;
Lei Wenaf62a552011-06-28 21:50:06 +0000179
Jaehoon Chung5d48e422012-09-20 20:31:54 +0000180 timeout = 1000000;
Lei Wenaf62a552011-06-28 21:50:06 +0000181 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
182 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
183 do {
184 stat = sdhci_readl(host, SDHCI_INT_STATUS);
185 if (stat & SDHCI_INT_ERROR) {
Masahiro Yamada61f2e5e2017-12-30 02:00:12 +0900186 pr_debug("%s: Error detected in status(0x%X)!\n",
187 __func__, stat);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900188 return -EIO;
Lei Wenaf62a552011-06-28 21:50:06 +0000189 }
Alex Deymo7dde50d2017-04-02 01:24:34 -0700190 if (!transfer_done && (stat & rdy)) {
Lei Wenaf62a552011-06-28 21:50:06 +0000191 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
192 continue;
193 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
194 sdhci_transfer_pio(host, data);
195 data->dest += data->blocksize;
Alex Deymo7dde50d2017-04-02 01:24:34 -0700196 if (++block >= data->blocks) {
197 /* Keep looping until the SDHCI_INT_DATA_END is
198 * cleared, even if we finished sending all the
199 * blocks.
200 */
201 transfer_done = true;
202 continue;
203 }
Lei Wenaf62a552011-06-28 21:50:06 +0000204 }
Faiz Abbas37cb6262019-04-16 23:06:58 +0530205 if ((host->flags & USE_DMA) && !transfer_done &&
Faiz Abbas6d6af202019-04-16 23:06:57 +0530206 (stat & SDHCI_INT_DMA_END)) {
Lei Wenaf62a552011-06-28 21:50:06 +0000207 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
Faiz Abbas37cb6262019-04-16 23:06:58 +0530208 if (host->flags & USE_SDMA) {
209 start_addr &=
210 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
211 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
Jaehoon Chungfac8bfd2020-03-27 13:08:00 +0900212 sdhci_writel(host, phys_to_bus((ulong)start_addr),
Faiz Abbas37cb6262019-04-16 23:06:58 +0530213 SDHCI_DMA_ADDRESS);
214 }
Lei Wenaf62a552011-06-28 21:50:06 +0000215 }
Lei Wena004abd2011-10-08 04:14:57 +0000216 if (timeout-- > 0)
217 udelay(10);
218 else {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800219 printf("%s: Transfer data timeout\n", __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900220 return -ETIMEDOUT;
Lei Wena004abd2011-10-08 04:14:57 +0000221 }
Lei Wenaf62a552011-06-28 21:50:06 +0000222 } while (!(stat & SDHCI_INT_DATA_END));
Masahiro Yamada4155ad92020-02-14 16:40:27 +0900223
224 dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
225 mmc_get_dma_dir(data));
226
Lei Wenaf62a552011-06-28 21:50:06 +0000227 return 0;
228}
229
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200230/*
231 * No command will be sent by driver if card is busy, so driver must wait
232 * for card ready state.
233 * Every time when card is busy after timeout then (last) timeout value will be
234 * increased twice but only if it doesn't exceed global defined maximum.
Masahiro Yamada65a25b22016-08-25 16:07:39 +0900235 * Each function call will use last timeout value.
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200236 */
Masahiro Yamada65a25b22016-08-25 16:07:39 +0900237#define SDHCI_CMD_MAX_TIMEOUT 3200
Masahiro Yamadad8ce77b2016-08-25 16:07:38 +0900238#define SDHCI_CMD_DEFAULT_TIMEOUT 100
Steve Raed90bb432016-06-29 13:42:01 -0700239#define SDHCI_READ_STATUS_TIMEOUT 1000
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200240
Simon Glasse7881d82017-07-29 11:35:31 -0600241#ifdef CONFIG_DM_MMC
Simon Glassef1e4ed2016-06-12 23:30:28 -0600242static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
243 struct mmc_data *data)
Lei Wenaf62a552011-06-28 21:50:06 +0000244{
Simon Glassef1e4ed2016-06-12 23:30:28 -0600245 struct mmc *mmc = mmc_get_mmc_dev(dev);
246
247#else
248static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
249 struct mmc_data *data)
250{
251#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200252 struct sdhci_host *host = mmc->priv;
Lei Wenaf62a552011-06-28 21:50:06 +0000253 unsigned int stat = 0;
254 int ret = 0;
255 int trans_bytes = 0, is_aligned = 1;
256 u32 mask, flags, mode;
Faiz Abbas6d6af202019-04-16 23:06:57 +0530257 unsigned int time = 0;
Simon Glass19d2e342016-05-14 14:03:04 -0600258 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
Vipul Kumar36332b62018-05-03 12:20:54 +0530259 ulong start = get_timer(0);
Lei Wenaf62a552011-06-28 21:50:06 +0000260
Faiz Abbas6d6af202019-04-16 23:06:57 +0530261 host->start_addr = 0;
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200262 /* Timeout unit - ms */
Masahiro Yamadad8ce77b2016-08-25 16:07:38 +0900263 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
Lei Wenaf62a552011-06-28 21:50:06 +0000264
Lei Wenaf62a552011-06-28 21:50:06 +0000265 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
266
267 /* We shouldn't wait for data inihibit for stop commands, even
268 though they might use busy signaling */
Siva Durga Prasad Paladugub88a7a42018-04-19 12:37:05 +0530269 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
Siva Durga Prasad Paladugu1a7414f2018-06-13 11:43:01 +0530270 ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
271 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
Lei Wenaf62a552011-06-28 21:50:06 +0000272 mask &= ~SDHCI_DATA_INHIBIT;
273
274 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200275 if (time >= cmd_timeout) {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800276 printf("%s: MMC: %d busy ", __func__, mmc_dev);
Masahiro Yamada65a25b22016-08-25 16:07:39 +0900277 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200278 cmd_timeout += cmd_timeout;
279 printf("timeout increasing to: %u ms.\n",
280 cmd_timeout);
281 } else {
282 puts("timeout.\n");
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900283 return -ECOMM;
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200284 }
Lei Wenaf62a552011-06-28 21:50:06 +0000285 }
Przemyslaw Marczak56b34bc2013-10-08 18:12:09 +0200286 time++;
Lei Wenaf62a552011-06-28 21:50:06 +0000287 udelay(1000);
288 }
289
Jorge Ramirez-Ortiz713e6812017-11-02 15:10:21 +0100290 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
291
Lei Wenaf62a552011-06-28 21:50:06 +0000292 mask = SDHCI_INT_RESPONSE;
Siva Durga Prasad Paladugu1a7414f2018-06-13 11:43:01 +0530293 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
294 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
Siva Durga Prasad Paladugub88a7a42018-04-19 12:37:05 +0530295 mask = SDHCI_INT_DATA_AVAIL;
296
Lei Wenaf62a552011-06-28 21:50:06 +0000297 if (!(cmd->resp_type & MMC_RSP_PRESENT))
298 flags = SDHCI_CMD_RESP_NONE;
299 else if (cmd->resp_type & MMC_RSP_136)
300 flags = SDHCI_CMD_RESP_LONG;
301 else if (cmd->resp_type & MMC_RSP_BUSY) {
302 flags = SDHCI_CMD_RESP_SHORT_BUSY;
Jaehoon Chung17ea3c82016-07-12 21:18:46 +0900303 if (data)
304 mask |= SDHCI_INT_DATA_END;
Lei Wenaf62a552011-06-28 21:50:06 +0000305 } else
306 flags = SDHCI_CMD_RESP_SHORT;
307
308 if (cmd->resp_type & MMC_RSP_CRC)
309 flags |= SDHCI_CMD_CRC;
310 if (cmd->resp_type & MMC_RSP_OPCODE)
311 flags |= SDHCI_CMD_INDEX;
Siva Durga Prasad Paladugu434f9d42018-05-29 20:03:10 +0530312 if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
313 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
Lei Wenaf62a552011-06-28 21:50:06 +0000314 flags |= SDHCI_CMD_DATA;
315
Darwin Rambo30e6d972013-12-19 15:13:25 -0800316 /* Set Transfer mode regarding to data flag */
Heinrich Schuchardtbb7b4ef2017-11-10 21:13:34 +0100317 if (data) {
Lei Wenaf62a552011-06-28 21:50:06 +0000318 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
319 mode = SDHCI_TRNS_BLK_CNT_EN;
320 trans_bytes = data->blocks * data->blocksize;
321 if (data->blocks > 1)
322 mode |= SDHCI_TRNS_MULTI;
323
324 if (data->flags == MMC_DATA_READ)
325 mode |= SDHCI_TRNS_READ;
326
Faiz Abbas37cb6262019-04-16 23:06:58 +0530327 if (host->flags & USE_DMA) {
Faiz Abbas6d6af202019-04-16 23:06:57 +0530328 mode |= SDHCI_TRNS_DMA;
329 sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
Lei Wenaf62a552011-06-28 21:50:06 +0000330 }
331
Lei Wenaf62a552011-06-28 21:50:06 +0000332 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
333 data->blocksize),
334 SDHCI_BLOCK_SIZE);
335 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
336 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
Kevin Liu5e1c23c2015-03-23 17:57:00 -0500337 } else if (cmd->resp_type & MMC_RSP_BUSY) {
338 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
Lei Wenaf62a552011-06-28 21:50:06 +0000339 }
340
341 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
Lei Wenaf62a552011-06-28 21:50:06 +0000342 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
Stefan Roese29905a42015-06-29 14:58:08 +0200343 start = get_timer(0);
Lei Wenaf62a552011-06-28 21:50:06 +0000344 do {
345 stat = sdhci_readl(host, SDHCI_INT_STATUS);
346 if (stat & SDHCI_INT_ERROR)
347 break;
Lei Wenaf62a552011-06-28 21:50:06 +0000348
Masahiro Yamadabae4a1f2016-07-10 00:40:22 +0900349 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
350 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
351 return 0;
352 } else {
353 printf("%s: Timeout for status update!\n",
354 __func__);
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900355 return -ETIMEDOUT;
Masahiro Yamadabae4a1f2016-07-10 00:40:22 +0900356 }
Jaehoon Chung3a638322012-04-23 02:36:25 +0000357 }
Masahiro Yamadabae4a1f2016-07-10 00:40:22 +0900358 } while ((stat & mask) != mask);
Jaehoon Chung3a638322012-04-23 02:36:25 +0000359
Lei Wenaf62a552011-06-28 21:50:06 +0000360 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
361 sdhci_cmd_done(host, cmd);
362 sdhci_writel(host, mask, SDHCI_INT_STATUS);
363 } else
364 ret = -1;
365
366 if (!ret && data)
Faiz Abbas6d6af202019-04-16 23:06:57 +0530367 ret = sdhci_transfer_data(host, data);
Lei Wenaf62a552011-06-28 21:50:06 +0000368
Tushar Behera13243f22012-09-20 20:31:57 +0000369 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
370 udelay(1000);
371
Lei Wenaf62a552011-06-28 21:50:06 +0000372 stat = sdhci_readl(host, SDHCI_INT_STATUS);
373 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
374 if (!ret) {
375 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
376 !is_aligned && (data->flags == MMC_DATA_READ))
Masahiro Yamadac8cc18b2020-02-14 16:40:21 +0900377 memcpy(data->dest, host->align_buffer, trans_bytes);
Lei Wenaf62a552011-06-28 21:50:06 +0000378 return 0;
379 }
380
381 sdhci_reset(host, SDHCI_RESET_CMD);
382 sdhci_reset(host, SDHCI_RESET_DATA);
383 if (stat & SDHCI_INT_TIMEOUT)
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900384 return -ETIMEDOUT;
Lei Wenaf62a552011-06-28 21:50:06 +0000385 else
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900386 return -ECOMM;
Lei Wenaf62a552011-06-28 21:50:06 +0000387}
388
Siva Durga Prasad Paladuguca992e82018-04-19 12:37:07 +0530389#if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
390static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
391{
392 int err;
393 struct mmc *mmc = mmc_get_mmc_dev(dev);
394 struct sdhci_host *host = mmc->priv;
395
396 debug("%s\n", __func__);
397
Ramon Friedb70fe962018-05-14 15:02:30 +0300398 if (host->ops && host->ops->platform_execute_tuning) {
Siva Durga Prasad Paladuguca992e82018-04-19 12:37:07 +0530399 err = host->ops->platform_execute_tuning(mmc, opcode);
400 if (err)
401 return err;
402 return 0;
403 }
404 return 0;
405}
406#endif
Faiz Abbas3966c7d2019-06-11 00:43:35 +0530407int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
Lei Wenaf62a552011-06-28 21:50:06 +0000408{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200409 struct sdhci_host *host = mmc->priv;
Stefan Roese899fb9e2016-12-12 08:34:42 +0100410 unsigned int div, clk = 0, timeout;
Lei Wenaf62a552011-06-28 21:50:06 +0000411
Wenyou Yang79667b72015-09-22 14:59:25 +0800412 /* Wait max 20 ms */
413 timeout = 200;
414 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
415 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
416 if (timeout == 0) {
417 printf("%s: Timeout to wait cmd & data inhibit\n",
418 __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900419 return -EBUSY;
Wenyou Yang79667b72015-09-22 14:59:25 +0800420 }
421
422 timeout--;
423 udelay(100);
424 }
425
Stefan Roese899fb9e2016-12-12 08:34:42 +0100426 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
Lei Wenaf62a552011-06-28 21:50:06 +0000427
428 if (clock == 0)
429 return 0;
430
Ramon Friedb70fe962018-05-14 15:02:30 +0300431 if (host->ops && host->ops->set_delay)
Siva Durga Prasad Paladuguca992e82018-04-19 12:37:07 +0530432 host->ops->set_delay(host);
433
Jaehoon Chung113e5df2013-07-19 17:44:49 +0900434 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800435 /*
436 * Check if the Host Controller supports Programmable Clock
437 * Mode.
438 */
439 if (host->clk_mul) {
440 for (div = 1; div <= 1024; div++) {
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800441 if ((host->max_clk / div) <= clock)
Lei Wenaf62a552011-06-28 21:50:06 +0000442 break;
443 }
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800444
445 /*
446 * Set Programmable Clock Mode in the Clock
447 * Control register.
448 */
449 clk = SDHCI_PROG_CLOCK_MODE;
450 div--;
451 } else {
452 /* Version 3.00 divisors must be a multiple of 2. */
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100453 if (host->max_clk <= clock) {
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800454 div = 1;
455 } else {
456 for (div = 2;
457 div < SDHCI_MAX_DIV_SPEC_300;
458 div += 2) {
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100459 if ((host->max_clk / div) <= clock)
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800460 break;
461 }
462 }
463 div >>= 1;
Lei Wenaf62a552011-06-28 21:50:06 +0000464 }
465 } else {
466 /* Version 2.00 divisors must be a power of 2. */
467 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100468 if ((host->max_clk / div) <= clock)
Lei Wenaf62a552011-06-28 21:50:06 +0000469 break;
470 }
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800471 div >>= 1;
Lei Wenaf62a552011-06-28 21:50:06 +0000472 }
Lei Wenaf62a552011-06-28 21:50:06 +0000473
Masahiro Yamadabf9c4d12017-01-13 11:51:51 +0900474 if (host->ops && host->ops->set_clock)
Jaehoon Chung62226b62016-12-30 15:30:18 +0900475 host->ops->set_clock(host, div);
Jaehoon Chungb09ed6e2012-08-30 16:24:11 +0000476
Wenyou Yang6dffdbc2016-09-18 09:01:22 +0800477 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
Lei Wenaf62a552011-06-28 21:50:06 +0000478 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
479 << SDHCI_DIVIDER_HI_SHIFT;
480 clk |= SDHCI_CLOCK_INT_EN;
481 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
482
483 /* Wait max 20 ms */
484 timeout = 20;
485 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
486 & SDHCI_CLOCK_INT_STABLE)) {
487 if (timeout == 0) {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800488 printf("%s: Internal clock never stabilised.\n",
489 __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900490 return -EBUSY;
Lei Wenaf62a552011-06-28 21:50:06 +0000491 }
492 timeout--;
493 udelay(1000);
494 }
495
496 clk |= SDHCI_CLOCK_CARD_EN;
497 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
498 return 0;
499}
500
501static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
502{
503 u8 pwr = 0;
504
505 if (power != (unsigned short)-1) {
506 switch (1 << power) {
507 case MMC_VDD_165_195:
508 pwr = SDHCI_POWER_180;
509 break;
510 case MMC_VDD_29_30:
511 case MMC_VDD_30_31:
512 pwr = SDHCI_POWER_300;
513 break;
514 case MMC_VDD_32_33:
515 case MMC_VDD_33_34:
516 pwr = SDHCI_POWER_330;
517 break;
518 }
519 }
520
521 if (pwr == 0) {
522 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
523 return;
524 }
525
526 pwr |= SDHCI_POWER_ON;
527
528 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
529}
530
Faiz Abbasd1c0a222019-06-11 00:43:40 +0530531void sdhci_set_uhs_timing(struct sdhci_host *host)
532{
Masahiro Yamadafdd84c82020-02-14 16:40:24 +0900533 struct mmc *mmc = host->mmc;
Faiz Abbasd1c0a222019-06-11 00:43:40 +0530534 u32 reg;
535
536 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
537 reg &= ~SDHCI_CTRL_UHS_MASK;
538
539 switch (mmc->selected_mode) {
540 case UHS_SDR50:
541 case MMC_HS_52:
542 reg |= SDHCI_CTRL_UHS_SDR50;
543 break;
544 case UHS_DDR50:
545 case MMC_DDR_52:
546 reg |= SDHCI_CTRL_UHS_DDR50;
547 break;
548 case UHS_SDR104:
549 case MMC_HS_200:
550 reg |= SDHCI_CTRL_UHS_SDR104;
551 break;
552 default:
553 reg |= SDHCI_CTRL_UHS_SDR12;
554 }
555
556 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
557}
558
Simon Glasse7881d82017-07-29 11:35:31 -0600559#ifdef CONFIG_DM_MMC
Simon Glassef1e4ed2016-06-12 23:30:28 -0600560static int sdhci_set_ios(struct udevice *dev)
561{
562 struct mmc *mmc = mmc_get_mmc_dev(dev);
563#else
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900564static int sdhci_set_ios(struct mmc *mmc)
Lei Wenaf62a552011-06-28 21:50:06 +0000565{
Simon Glassef1e4ed2016-06-12 23:30:28 -0600566#endif
Lei Wenaf62a552011-06-28 21:50:06 +0000567 u32 ctrl;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200568 struct sdhci_host *host = mmc->priv;
Jagan Tekif12341a2020-06-18 19:33:12 +0530569 bool no_hispd_bit = false;
Lei Wenaf62a552011-06-28 21:50:06 +0000570
Masahiro Yamadabf9c4d12017-01-13 11:51:51 +0900571 if (host->ops && host->ops->set_control_reg)
Jaehoon Chung62226b62016-12-30 15:30:18 +0900572 host->ops->set_control_reg(host);
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000573
Lei Wenaf62a552011-06-28 21:50:06 +0000574 if (mmc->clock != host->clock)
575 sdhci_set_clock(mmc, mmc->clock);
576
Siva Durga Prasad Paladugu2a2d7ef2018-04-19 12:37:04 +0530577 if (mmc->clk_disable)
578 sdhci_set_clock(mmc, 0);
579
Lei Wenaf62a552011-06-28 21:50:06 +0000580 /* Set bus width */
581 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
582 if (mmc->bus_width == 8) {
583 ctrl &= ~SDHCI_CTRL_4BITBUS;
Jaehoon Chung113e5df2013-07-19 17:44:49 +0900584 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
585 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
Lei Wenaf62a552011-06-28 21:50:06 +0000586 ctrl |= SDHCI_CTRL_8BITBUS;
587 } else {
Matt Reimerf88a4292015-02-19 11:22:53 -0700588 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
589 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
Lei Wenaf62a552011-06-28 21:50:06 +0000590 ctrl &= ~SDHCI_CTRL_8BITBUS;
591 if (mmc->bus_width == 4)
592 ctrl |= SDHCI_CTRL_4BITBUS;
593 else
594 ctrl &= ~SDHCI_CTRL_4BITBUS;
595 }
596
Hannes Schmelzer88a57122018-03-07 08:00:56 +0100597 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
Jagan Tekif12341a2020-06-18 19:33:12 +0530598 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) {
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000599 ctrl &= ~SDHCI_CTRL_HISPD;
Jagan Tekif12341a2020-06-18 19:33:12 +0530600 no_hispd_bit = true;
601 }
602
603 if (!no_hispd_bit) {
604 if (mmc->selected_mode == MMC_HS ||
605 mmc->selected_mode == SD_HS ||
606 mmc->selected_mode == MMC_DDR_52 ||
607 mmc->selected_mode == MMC_HS_200 ||
608 mmc->selected_mode == MMC_HS_400 ||
609 mmc->selected_mode == UHS_SDR25 ||
610 mmc->selected_mode == UHS_SDR50 ||
611 mmc->selected_mode == UHS_SDR104 ||
612 mmc->selected_mode == UHS_DDR50)
613 ctrl |= SDHCI_CTRL_HISPD;
614 else
615 ctrl &= ~SDHCI_CTRL_HISPD;
616 }
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000617
Lei Wenaf62a552011-06-28 21:50:06 +0000618 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900619
Stefan Roese210841c2016-12-12 08:24:56 +0100620 /* If available, call the driver specific "post" set_ios() function */
621 if (host->ops && host->ops->set_ios_post)
Faiz Abbasa8185c52019-06-11 00:43:37 +0530622 return host->ops->set_ios_post(host);
Stefan Roese210841c2016-12-12 08:24:56 +0100623
Simon Glassef1e4ed2016-06-12 23:30:28 -0600624 return 0;
Lei Wenaf62a552011-06-28 21:50:06 +0000625}
626
Jeroen Hofstee6588c782014-10-08 22:57:43 +0200627static int sdhci_init(struct mmc *mmc)
Lei Wenaf62a552011-06-28 21:50:06 +0000628{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200629 struct sdhci_host *host = mmc->priv;
T Karthik Reddy451931e2019-06-25 13:39:03 +0200630#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
631 struct udevice *dev = mmc->dev;
632
Baruch Siach58d65d52019-07-22 19:14:06 +0300633 gpio_request_by_name(dev, "cd-gpios", 0,
T Karthik Reddy451931e2019-06-25 13:39:03 +0200634 &host->cd_gpio, GPIOD_IS_IN);
635#endif
Lei Wenaf62a552011-06-28 21:50:06 +0000636
Masahiro Yamada8d549b62016-08-25 16:07:34 +0900637 sdhci_reset(host, SDHCI_RESET_ALL);
638
Masahiro Yamadac8cc18b2020-02-14 16:40:21 +0900639#if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
640 host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
Masahiro Yamadaf5df6aa2020-02-14 16:40:22 +0900641 /*
642 * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
643 * is defined.
644 */
645 host->force_align_buffer = true;
Masahiro Yamadac8cc18b2020-02-14 16:40:21 +0900646#else
647 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
648 host->align_buffer = memalign(8, 512 * 1024);
649 if (!host->align_buffer) {
Darwin Rambo30e6d972013-12-19 15:13:25 -0800650 printf("%s: Aligned buffer alloc failed!!!\n",
651 __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900652 return -ENOMEM;
Lei Wenaf62a552011-06-28 21:50:06 +0000653 }
654 }
Masahiro Yamadac8cc18b2020-02-14 16:40:21 +0900655#endif
Lei Wenaf62a552011-06-28 21:50:06 +0000656
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200657 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
Joe Hershberger470dcc72012-08-17 10:18:55 +0000658
Masahiro Yamadabf9c4d12017-01-13 11:51:51 +0900659 if (host->ops && host->ops->get_cd)
Jaehoon Chung6f88a3a2016-12-30 15:30:15 +0900660 host->ops->get_cd(host);
Joe Hershberger470dcc72012-08-17 10:18:55 +0000661
Łukasz Majewskice0c1bc2013-01-11 05:08:54 +0000662 /* Enable only interrupts served by the SD controller */
Darwin Rambo30e6d972013-12-19 15:13:25 -0800663 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
664 SDHCI_INT_ENABLE);
Łukasz Majewskice0c1bc2013-01-11 05:08:54 +0000665 /* Mask all sdhci interrupt sources */
666 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
Lei Wenaf62a552011-06-28 21:50:06 +0000667
Lei Wenaf62a552011-06-28 21:50:06 +0000668 return 0;
669}
670
Simon Glasse7881d82017-07-29 11:35:31 -0600671#ifdef CONFIG_DM_MMC
Simon Glassef1e4ed2016-06-12 23:30:28 -0600672int sdhci_probe(struct udevice *dev)
673{
674 struct mmc *mmc = mmc_get_mmc_dev(dev);
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200675
Simon Glassef1e4ed2016-06-12 23:30:28 -0600676 return sdhci_init(mmc);
677}
678
Faiz Abbascb884342020-02-26 13:44:31 +0530679static int sdhci_deferred_probe(struct udevice *dev)
680{
681 int err;
682 struct mmc *mmc = mmc_get_mmc_dev(dev);
683 struct sdhci_host *host = mmc->priv;
684
685 if (host->ops && host->ops->deferred_probe) {
686 err = host->ops->deferred_probe(host);
687 if (err)
688 return err;
689 }
690 return 0;
691}
692
Baruch Siach1b716952019-11-03 12:00:27 +0200693static int sdhci_get_cd(struct udevice *dev)
T Karthik Reddyda18c622019-06-25 13:39:04 +0200694{
695 struct mmc *mmc = mmc_get_mmc_dev(dev);
696 struct sdhci_host *host = mmc->priv;
697 int value;
698
699 /* If nonremovable, assume that the card is always present. */
700 if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
701 return 1;
702 /* If polling, assume that the card is always present. */
703 if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
704 return 1;
705
706#if CONFIG_IS_ENABLED(DM_GPIO)
707 value = dm_gpio_get_value(&host->cd_gpio);
708 if (value >= 0) {
709 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
710 return !value;
711 else
712 return value;
713 }
714#endif
715 value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
716 SDHCI_CARD_PRESENT);
717 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
718 return !value;
719 else
720 return value;
721}
722
Simon Glassef1e4ed2016-06-12 23:30:28 -0600723const struct dm_mmc_ops sdhci_ops = {
724 .send_cmd = sdhci_send_command,
725 .set_ios = sdhci_set_ios,
T Karthik Reddyda18c622019-06-25 13:39:04 +0200726 .get_cd = sdhci_get_cd,
Faiz Abbascb884342020-02-26 13:44:31 +0530727 .deferred_probe = sdhci_deferred_probe,
Siva Durga Prasad Paladuguca992e82018-04-19 12:37:07 +0530728#ifdef MMC_SUPPORTS_TUNING
729 .execute_tuning = sdhci_execute_tuning,
730#endif
Simon Glassef1e4ed2016-06-12 23:30:28 -0600731};
732#else
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200733static const struct mmc_ops sdhci_ops = {
734 .send_cmd = sdhci_send_command,
735 .set_ios = sdhci_set_ios,
736 .init = sdhci_init,
737};
Simon Glassef1e4ed2016-06-12 23:30:28 -0600738#endif
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200739
Jaehoon Chung14bed522016-07-26 19:06:24 +0900740int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100741 u32 f_max, u32 f_min)
Simon Glass2a809092016-06-12 23:30:27 -0600742{
Siva Durga Prasad Paladugub8e25ef2018-04-19 12:37:08 +0530743 u32 caps, caps_1 = 0;
Faiz Abbas3d296362019-06-11 00:43:34 +0530744#if CONFIG_IS_ENABLED(DM_MMC)
T Karthik Reddycd45d6f2019-09-02 16:34:31 +0200745 u64 dt_caps, dt_caps_mask;
Jaehoon Chung14bed522016-07-26 19:06:24 +0900746
T Karthik Reddycd45d6f2019-09-02 16:34:31 +0200747 dt_caps_mask = dev_read_u64_default(host->mmc->dev,
748 "sdhci-caps-mask", 0);
749 dt_caps = dev_read_u64_default(host->mmc->dev,
750 "sdhci-caps", 0);
Michal Simekb5a33872020-07-29 15:42:26 +0200751 caps = ~lower_32_bits(dt_caps_mask) &
T Karthik Reddycd45d6f2019-09-02 16:34:31 +0200752 sdhci_readl(host, SDHCI_CAPABILITIES);
Michal Simekb5a33872020-07-29 15:42:26 +0200753 caps |= lower_32_bits(dt_caps);
Faiz Abbas3d296362019-06-11 00:43:34 +0530754#else
Jaehoon Chung14bed522016-07-26 19:06:24 +0900755 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
Faiz Abbas3d296362019-06-11 00:43:34 +0530756#endif
T Karthik Reddycd45d6f2019-09-02 16:34:31 +0200757 debug("%s, caps: 0x%x\n", __func__, caps);
Masahiro Yamada15bd0992016-08-25 16:07:37 +0900758
Masahiro Yamada45a68fe2016-12-07 22:10:29 +0900759#ifdef CONFIG_MMC_SDHCI_SDMA
Jaehoon Chungfabb3a42020-03-27 13:08:01 +0900760 if ((caps & SDHCI_CAN_DO_SDMA)) {
761 host->flags |= USE_SDMA;
762 } else {
Matthias Brugger7acdc9a2020-05-12 12:02:06 +0200763 debug("%s: Your controller doesn't support SDMA!!\n",
764 __func__);
Masahiro Yamada15bd0992016-08-25 16:07:37 +0900765 }
766#endif
Faiz Abbas37cb6262019-04-16 23:06:58 +0530767#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
768 if (!(caps & SDHCI_CAN_DO_ADMA2)) {
769 printf("%s: Your controller doesn't support SDMA!!\n",
770 __func__);
771 return -EINVAL;
772 }
Masahiro Yamadafdd84c82020-02-14 16:40:24 +0900773 host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
Faiz Abbas37cb6262019-04-16 23:06:58 +0530774
775 host->adma_addr = (dma_addr_t)host->adma_desc_table;
776#ifdef CONFIG_DMA_ADDR_T_64BIT
777 host->flags |= USE_ADMA64;
778#else
779 host->flags |= USE_ADMA;
780#endif
781#endif
Jaehoon Chung895549a2016-09-26 08:10:01 +0900782 if (host->quirks & SDHCI_QUIRK_REG32_RW)
783 host->version =
784 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
785 else
786 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
Jaehoon Chung14bed522016-07-26 19:06:24 +0900787
788 cfg->name = host->name;
Simon Glasse7881d82017-07-29 11:35:31 -0600789#ifndef CONFIG_DM_MMC
Simon Glass2a809092016-06-12 23:30:27 -0600790 cfg->ops = &sdhci_ops;
791#endif
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800792
793 /* Check whether the clock multiplier is supported or not */
794 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Faiz Abbas3d296362019-06-11 00:43:34 +0530795#if CONFIG_IS_ENABLED(DM_MMC)
Michal Simekb5a33872020-07-29 15:42:26 +0200796 caps_1 = ~upper_32_bits(dt_caps_mask) &
T Karthik Reddycd45d6f2019-09-02 16:34:31 +0200797 sdhci_readl(host, SDHCI_CAPABILITIES_1);
Michal Simekb5a33872020-07-29 15:42:26 +0200798 caps_1 |= upper_32_bits(dt_caps);
Faiz Abbas3d296362019-06-11 00:43:34 +0530799#else
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800800 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
Faiz Abbas3d296362019-06-11 00:43:34 +0530801#endif
T Karthik Reddycd45d6f2019-09-02 16:34:31 +0200802 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800803 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
804 SDHCI_CLOCK_MUL_SHIFT;
805 }
806
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100807 if (host->max_clk == 0) {
Jaehoon Chung14bed522016-07-26 19:06:24 +0900808 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100809 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
Simon Glass2a809092016-06-12 23:30:27 -0600810 SDHCI_CLOCK_BASE_SHIFT;
811 else
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100812 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
Simon Glass2a809092016-06-12 23:30:27 -0600813 SDHCI_CLOCK_BASE_SHIFT;
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100814 host->max_clk *= 1000000;
Wenyou Yang0e0dcc12017-04-26 09:32:30 +0800815 if (host->clk_mul)
816 host->max_clk *= host->clk_mul;
Simon Glass2a809092016-06-12 23:30:27 -0600817 }
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100818 if (host->max_clk == 0) {
Masahiro Yamada6c679542016-08-25 16:07:35 +0900819 printf("%s: Hardware doesn't specify base clock frequency\n",
820 __func__);
Simon Glass2a809092016-06-12 23:30:27 -0600821 return -EINVAL;
Masahiro Yamada6c679542016-08-25 16:07:35 +0900822 }
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100823 if (f_max && (f_max < host->max_clk))
824 cfg->f_max = f_max;
825 else
826 cfg->f_max = host->max_clk;
827 if (f_min)
828 cfg->f_min = f_min;
Simon Glass2a809092016-06-12 23:30:27 -0600829 else {
Jaehoon Chung14bed522016-07-26 19:06:24 +0900830 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
Simon Glass2a809092016-06-12 23:30:27 -0600831 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
832 else
833 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
834 }
835 cfg->voltages = 0;
836 if (caps & SDHCI_CAN_VDD_330)
837 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
838 if (caps & SDHCI_CAN_VDD_300)
839 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
840 if (caps & SDHCI_CAN_VDD_180)
841 cfg->voltages |= MMC_VDD_165_195;
842
Masahiro Yamada3137e642016-08-25 16:07:36 +0900843 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
844 cfg->voltages |= host->voltages;
845
Faiz Abbas620bb462020-07-23 09:42:19 +0530846 if (caps & SDHCI_CAN_DO_HISPD)
847 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
848
849 cfg->host_caps |= MMC_MODE_4BIT;
Jaehoon Chung3fd0a9b2016-12-30 15:30:21 +0900850
851 /* Since Host Controller Version3.0 */
Jaehoon Chung14bed522016-07-26 19:06:24 +0900852 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
Jaehoon Chungecd7b242016-12-30 15:30:11 +0900853 if (!(caps & SDHCI_CAN_DO_8BIT))
854 cfg->host_caps &= ~MMC_MODE_8BIT;
Simon Glass2a809092016-06-12 23:30:27 -0600855 }
856
Hannes Schmelzer88a57122018-03-07 08:00:56 +0100857 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
858 cfg->host_caps &= ~MMC_MODE_HS;
859 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
860 }
861
Benedikt Grassl942b5fc2020-04-14 07:32:12 +0200862 if (!(cfg->voltages & MMC_VDD_165_195))
Siva Durga Prasad Paladugub8e25ef2018-04-19 12:37:08 +0530863 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
864 SDHCI_SUPPORT_DDR50);
865
866 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
867 SDHCI_SUPPORT_DDR50))
868 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
869
870 if (caps_1 & SDHCI_SUPPORT_SDR104) {
871 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
872 /*
873 * SD3.0: SDR104 is supported so (for eMMC) the caps2
874 * field can be promoted to support HS200.
875 */
876 cfg->host_caps |= MMC_CAP(MMC_HS_200);
877 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
878 cfg->host_caps |= MMC_CAP(UHS_SDR50);
879 }
880
881 if (caps_1 & SDHCI_SUPPORT_DDR50)
882 cfg->host_caps |= MMC_CAP(UHS_DDR50);
883
Jaehoon Chung14bed522016-07-26 19:06:24 +0900884 if (host->host_caps)
885 cfg->host_caps |= host->host_caps;
Simon Glass2a809092016-06-12 23:30:27 -0600886
887 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
888
889 return 0;
890}
891
Simon Glassef1e4ed2016-06-12 23:30:28 -0600892#ifdef CONFIG_BLK
893int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
894{
895 return mmc_bind(dev, mmc, cfg);
896}
897#else
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100898int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
Lei Wenaf62a552011-06-28 21:50:06 +0000899{
Masahiro Yamada6c679542016-08-25 16:07:35 +0900900 int ret;
901
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +0100902 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
Masahiro Yamada6c679542016-08-25 16:07:35 +0900903 if (ret)
904 return ret;
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000905
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200906 host->mmc = mmc_create(&host->cfg, host);
907 if (host->mmc == NULL) {
908 printf("%s: mmc create fail!\n", __func__);
Jaehoon Chung2cb5d672016-09-26 08:10:02 +0900909 return -ENOMEM;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200910 }
Lei Wenaf62a552011-06-28 21:50:06 +0000911
912 return 0;
913}
Simon Glassef1e4ed2016-06-12 23:30:28 -0600914#endif