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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Eran Libertyf046ccd2005-07-28 10:08:46 -05002/*
Ilya Yanok7c619dd2010-06-28 16:44:33 +04003 * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
Eran Libertyf046ccd2005-07-28 10:08:46 -05004 */
5
Eran Libertyf046ccd2005-07-28 10:08:46 -05006#ifndef __MPC83XX_H__
7#define __MPC83XX_H__
8
Dave Liuf6eda7f2006-10-25 14:41:21 -05009#include <config.h>
Anton Vorontsovbf30bb12008-05-28 18:20:15 +040010#include <asm/fsl_lbc.h>
Eran Libertyf046ccd2005-07-28 10:08:46 -050011#if defined(CONFIG_E300)
12#include <asm/e300.h>
13#endif
14
Heiko Schocher4e8b7502011-09-26 13:36:53 +020015/*
Heiko Schocher4e8b7502011-09-26 13:36:53 +020016 * System reset offset (PowerPC standard)
Eran Libertyf046ccd2005-07-28 10:08:46 -050017 */
Dave Liue0803132006-12-07 21:11:58 +080018#define EXC_OFF_SYS_RESET 0x0100
Rafal Jaworowski02032e82007-06-22 14:58:04 +020019#define _START_OFFSET EXC_OFF_SYS_RESET
Eran Libertyf046ccd2005-07-28 10:08:46 -050020
Heiko Schocher4e8b7502011-09-26 13:36:53 +020021/*
22 * IMMRBAR - Internal Memory Register Base Address
Eran Libertyf046ccd2005-07-28 10:08:46 -050023 */
Scott Woode4c09502008-06-30 14:13:28 -050024#ifndef CONFIG_DEFAULT_IMMR
Heiko Schocher4e8b7502011-09-26 13:36:53 +020025/* Default IMMR base address */
26#define CONFIG_DEFAULT_IMMR 0xFF400000
Scott Woode4c09502008-06-30 14:13:28 -050027#endif
Heiko Schocher4e8b7502011-09-26 13:36:53 +020028/* Register offset to immr */
29#define IMMRBAR 0x0000
30#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base addr. mask */
Dave Liue0803132006-12-07 21:11:58 +080031#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR)
Eran Libertyf046ccd2005-07-28 10:08:46 -050032
Heiko Schocher4e8b7502011-09-26 13:36:53 +020033/*
34 * LAWBAR - Local Access Window Base Address Register
Eran Libertyf046ccd2005-07-28 10:08:46 -050035 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +020036/* Register offset to immr */
37#define LBLAWBAR0 0x0020
Dave Liue0803132006-12-07 21:11:58 +080038#define LBLAWAR0 0x0024
39#define LBLAWBAR1 0x0028
40#define LBLAWAR1 0x002C
41#define LBLAWBAR2 0x0030
42#define LBLAWAR2 0x0034
43#define LBLAWBAR3 0x0038
44#define LBLAWAR3 0x003C
Heiko Schocher4e8b7502011-09-26 13:36:53 +020045#define LAWBAR_BAR 0xFFFFF000 /* Base addr. mask */
Eran Libertyf046ccd2005-07-28 10:08:46 -050046
Heiko Schocher4e8b7502011-09-26 13:36:53 +020047/*
48 * SPRIDR - System Part and Revision ID Register
Eran Libertyf046ccd2005-07-28 10:08:46 -050049 */
Kim Phillipse5c4ade2008-03-28 10:19:07 -050050#define SPRIDR_PARTID 0xFFFF0000 /* Part Id */
51#define SPRIDR_REVID 0x0000FFFF /* Revision Id */
Eran Libertyf046ccd2005-07-28 10:08:46 -050052
Mario Sixd5cfa4a2019-01-21 09:17:27 +010053#if defined(CONFIG_ARCH_MPC834X)
Kim Phillipse5c4ade2008-03-28 10:19:07 -050054#define REVID_MAJOR(spridr) ((spridr & 0x0000FF00) >> 8)
55#define REVID_MINOR(spridr) (spridr & 0x000000FF)
56#else
57#define REVID_MAJOR(spridr) ((spridr & 0x000000F0) >> 4)
58#define REVID_MINOR(spridr) (spridr & 0x0000000F)
59#endif
Dave Liue0803132006-12-07 21:11:58 +080060
Kim Phillipse5c4ade2008-03-28 10:19:07 -050061#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
Kim Phillips6b70ffb2008-06-16 15:55:53 -050062#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
Dave Liue0803132006-12-07 21:11:58 +080063
Ilya Yanok7c619dd2010-06-28 16:44:33 +040064#define SPR_8308 0x8100
Gerlando Falautoa88731a2012-10-10 22:13:08 +000065#define SPR_8309 0x8110
Kim Phillips6b70ffb2008-06-16 15:55:53 -050066#define SPR_831X_FAMILY 0x80B
Kim Phillipse5c4ade2008-03-28 10:19:07 -050067#define SPR_8311 0x80B2
68#define SPR_8313 0x80B0
69#define SPR_8314 0x80B6
70#define SPR_8315 0x80B4
Kim Phillips6b70ffb2008-06-16 15:55:53 -050071#define SPR_832X_FAMILY 0x806
Kim Phillipse5c4ade2008-03-28 10:19:07 -050072#define SPR_8321 0x8066
73#define SPR_8323 0x8062
Kim Phillips6b70ffb2008-06-16 15:55:53 -050074#define SPR_834X_FAMILY 0x803
Kim Phillipse5c4ade2008-03-28 10:19:07 -050075#define SPR_8343 0x8036
76#define SPR_8347_TBGA_ 0x8032
77#define SPR_8347_PBGA_ 0x8034
78#define SPR_8349 0x8030
Kim Phillips6b70ffb2008-06-16 15:55:53 -050079#define SPR_836X_FAMILY 0x804
Kim Phillipse5c4ade2008-03-28 10:19:07 -050080#define SPR_8358_TBGA_ 0x804A
81#define SPR_8358_PBGA_ 0x804E
82#define SPR_8360 0x8048
Kim Phillips6b70ffb2008-06-16 15:55:53 -050083#define SPR_837X_FAMILY 0x80C
Kim Phillipse5c4ade2008-03-28 10:19:07 -050084#define SPR_8377 0x80C6
85#define SPR_8378 0x80C4
86#define SPR_8379 0x80C2
Scott Woodd87c57b2007-04-16 14:31:55 -050087
Heiko Schocher4e8b7502011-09-26 13:36:53 +020088/*
89 * SPCR - System Priority Configuration Register
Eran Libertyf046ccd2005-07-28 10:08:46 -050090 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +020091/* PCI Highest Priority Enable */
92#define SPCR_PCIHPE 0x10000000
Dave Liue0803132006-12-07 21:11:58 +080093#define SPCR_PCIHPE_SHIFT (31-3)
Heiko Schocher4e8b7502011-09-26 13:36:53 +020094/* PCI bridge system bus request priority */
95#define SPCR_PCIPR 0x03000000
Dave Liue0803132006-12-07 21:11:58 +080096#define SPCR_PCIPR_SHIFT (31-7)
97#define SPCR_OPT 0x00800000 /* Optimize */
Michael Barkowski5bbeea82008-03-20 13:15:34 -040098#define SPCR_OPT_SHIFT (31-8)
Heiko Schocher4e8b7502011-09-26 13:36:53 +020099/* E300 PowerPC core time base unit enable */
100#define SPCR_TBEN 0x00400000
Dave Liue0803132006-12-07 21:11:58 +0800101#define SPCR_TBEN_SHIFT (31-9)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200102/* E300 PowerPC Core system bus request priority */
103#define SPCR_COREPR 0x00300000
Dave Liue0803132006-12-07 21:11:58 +0800104#define SPCR_COREPR_SHIFT (31-11)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500105
Mario Sixd5cfa4a2019-01-21 09:17:27 +0100106#if defined(CONFIG_ARCH_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +0800107/* SPCR bits - MPC8349 specific */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200108/* TSEC1 data priority */
109#define SPCR_TSEC1DP 0x00003000
Dave Liue0803132006-12-07 21:11:58 +0800110#define SPCR_TSEC1DP_SHIFT (31-19)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200111/* TSEC1 buffer descriptor priority */
112#define SPCR_TSEC1BDP 0x00000C00
Dave Liue0803132006-12-07 21:11:58 +0800113#define SPCR_TSEC1BDP_SHIFT (31-21)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200114/* TSEC1 emergency priority */
115#define SPCR_TSEC1EP 0x00000300
Dave Liue0803132006-12-07 21:11:58 +0800116#define SPCR_TSEC1EP_SHIFT (31-23)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200117/* TSEC2 data priority */
118#define SPCR_TSEC2DP 0x00000030
Dave Liue0803132006-12-07 21:11:58 +0800119#define SPCR_TSEC2DP_SHIFT (31-27)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200120/* TSEC2 buffer descriptor priority */
121#define SPCR_TSEC2BDP 0x0000000C
Dave Liue0803132006-12-07 21:11:58 +0800122#define SPCR_TSEC2BDP_SHIFT (31-29)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200123/* TSEC2 emergency priority */
124#define SPCR_TSEC2EP 0x00000003
Dave Liue0803132006-12-07 21:11:58 +0800125#define SPCR_TSEC2EP_SHIFT (31-31)
Scott Woodd87c57b2007-04-16 14:31:55 -0500126
Mario Six9403fc42019-01-21 09:17:25 +0100127#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six8439e992019-01-21 09:17:29 +0100128 defined(CONFIG_ARCH_MPC837X)
129/* SPCR bits - MPC8308, MPC831x and MPC837X specific */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200130/* TSEC data priority */
131#define SPCR_TSECDP 0x00003000
Scott Woodd87c57b2007-04-16 14:31:55 -0500132#define SPCR_TSECDP_SHIFT (31-19)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200133/* TSEC buffer descriptor priority */
134#define SPCR_TSECBDP 0x00000C00
Dave Liuec2638e2008-01-10 23:05:00 +0800135#define SPCR_TSECBDP_SHIFT (31-21)
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200136/* TSEC emergency priority */
137#define SPCR_TSECEP 0x00000300
Dave Liuec2638e2008-01-10 23:05:00 +0800138#define SPCR_TSECEP_SHIFT (31-23)
Dave Liu5f820432006-11-03 19:33:44 -0600139#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500140
Dave Liue0803132006-12-07 21:11:58 +0800141/* SICRL/H - System I/O Configuration Register Low/High
142 */
Mario Sixd5cfa4a2019-01-21 09:17:27 +0100143#if defined(CONFIG_ARCH_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +0800144/* SICRL bits - MPC8349 specific */
145#define SICRL_LDP_A 0x80000000
146#define SICRL_USB1 0x40000000
147#define SICRL_USB0 0x20000000
148#define SICRL_UART 0x0C000000
149#define SICRL_GPIO1_A 0x02000000
150#define SICRL_GPIO1_B 0x01000000
151#define SICRL_GPIO1_C 0x00800000
152#define SICRL_GPIO1_D 0x00400000
153#define SICRL_GPIO1_E 0x00200000
154#define SICRL_GPIO1_F 0x00180000
155#define SICRL_GPIO1_G 0x00040000
156#define SICRL_GPIO1_H 0x00020000
157#define SICRL_GPIO1_I 0x00010000
158#define SICRL_GPIO1_J 0x00008000
159#define SICRL_GPIO1_K 0x00004000
160#define SICRL_GPIO1_L 0x00003000
Eran Libertyf046ccd2005-07-28 10:08:46 -0500161
Dave Liue0803132006-12-07 21:11:58 +0800162/* SICRH bits - MPC8349 specific */
163#define SICRH_DDR 0x80000000
164#define SICRH_TSEC1_A 0x10000000
165#define SICRH_TSEC1_B 0x08000000
166#define SICRH_TSEC1_C 0x04000000
167#define SICRH_TSEC1_D 0x02000000
168#define SICRH_TSEC1_E 0x01000000
169#define SICRH_TSEC1_F 0x00800000
170#define SICRH_TSEC2_A 0x00400000
171#define SICRH_TSEC2_B 0x00200000
172#define SICRH_TSEC2_C 0x00100000
173#define SICRH_TSEC2_D 0x00080000
174#define SICRH_TSEC2_E 0x00040000
175#define SICRH_TSEC2_F 0x00020000
176#define SICRH_TSEC2_G 0x00010000
177#define SICRH_TSEC2_H 0x00008000
178#define SICRH_GPIO2_A 0x00004000
179#define SICRH_GPIO2_B 0x00002000
180#define SICRH_GPIO2_C 0x00001000
181#define SICRH_GPIO2_D 0x00000800
182#define SICRH_GPIO2_E 0x00000400
183#define SICRH_GPIO2_F 0x00000200
184#define SICRH_GPIO2_G 0x00000180
185#define SICRH_GPIO2_H 0x00000060
186#define SICRH_TSOBI1 0x00000002
187#define SICRH_TSOBI2 0x00000001
188
Mario Six61abced2019-01-21 09:17:28 +0100189#elif defined(CONFIG_ARCH_MPC8360)
Dave Liue0803132006-12-07 21:11:58 +0800190/* SICRL bits - MPC8360 specific */
191#define SICRL_LDP_A 0xC0000000
192#define SICRL_LCLK_1 0x10000000
193#define SICRL_LCLK_2 0x08000000
194#define SICRL_SRCID_A 0x03000000
195#define SICRL_IRQ_CKSTP_A 0x00C00000
196
197/* SICRH bits - MPC8360 specific */
198#define SICRH_DDR 0x80000000
199#define SICRH_SECONDARY_DDR 0x40000000
200#define SICRH_SDDROE 0x20000000
201#define SICRH_IRQ3 0x10000000
202#define SICRH_UC1EOBI 0x00000004
203#define SICRH_UC2E1OBI 0x00000002
204#define SICRH_UC2E2OBI 0x00000001
Dave Liu24c3aca2006-12-07 21:13:15 +0800205
Mario Sixbd3b8672019-01-21 09:17:26 +0100206#elif defined(CONFIG_ARCH_MPC832X)
Peter Tyser2c7920a2009-05-22 17:23:25 -0500207/* SICRL bits - MPC832x specific */
Dave Liu24c3aca2006-12-07 21:13:15 +0800208#define SICRL_LDP_LCS_A 0x80000000
209#define SICRL_IRQ_CKS 0x20000000
210#define SICRL_PCI_MSRC 0x10000000
211#define SICRL_URT_CTPR 0x06000000
212#define SICRL_IRQ_CTPR 0x00C00000
Scott Woodd87c57b2007-04-16 14:31:55 -0500213
Mario Six9403fc42019-01-21 09:17:25 +0100214#elif defined(CONFIG_ARCH_MPC8313)
Dave Liu555da612007-09-18 12:36:58 +0800215/* SICRL bits - MPC8313 specific */
Scott Woodd87c57b2007-04-16 14:31:55 -0500216#define SICRL_LBC 0x30000000
217#define SICRL_UART 0x0C000000
218#define SICRL_SPI_A 0x03000000
219#define SICRL_SPI_B 0x00C00000
220#define SICRL_SPI_C 0x00300000
221#define SICRL_SPI_D 0x000C0000
Ron Madridf9863252010-06-01 17:00:49 -0700222#define SICRL_USBDR_11 0x00000C00
223#define SICRL_USBDR_10 0x00000800
224#define SICRL_USBDR_01 0x00000400
225#define SICRL_USBDR_00 0x00000000
Scott Woodd87c57b2007-04-16 14:31:55 -0500226#define SICRL_ETSEC1_A 0x0000000C
227#define SICRL_ETSEC2_A 0x00000003
228
Dave Liu555da612007-09-18 12:36:58 +0800229/* SICRH bits - MPC8313 specific */
Scott Woodd87c57b2007-04-16 14:31:55 -0500230#define SICRH_INTR_A 0x02000000
231#define SICRH_INTR_B 0x00C00000
232#define SICRH_IIC 0x00300000
233#define SICRH_ETSEC2_B 0x000C0000
234#define SICRH_ETSEC2_C 0x00030000
235#define SICRH_ETSEC2_D 0x0000C000
236#define SICRH_ETSEC2_E 0x00003000
237#define SICRH_ETSEC2_F 0x00000C00
238#define SICRH_ETSEC2_G 0x00000300
239#define SICRH_ETSEC1_B 0x00000080
240#define SICRH_ETSEC1_C 0x00000060
241#define SICRH_GTX1_DLY 0x00000008
242#define SICRH_GTX2_DLY 0x00000004
243#define SICRH_TSOBI1 0x00000002
244#define SICRH_TSOBI2 0x00000001
245
Mario Six8439e992019-01-21 09:17:29 +0100246#elif defined(CONFIG_ARCH_MPC837X)
247/* SICRL bits - MPC837X specific */
Dave Liu03051c32007-09-18 12:36:11 +0800248#define SICRL_USB_A 0xC0000000
249#define SICRL_USB_B 0x30000000
Andy Fleminge1ac3872008-10-30 16:50:14 -0500250#define SICRL_USB_B_SD 0x20000000
Dave Liu03051c32007-09-18 12:36:11 +0800251#define SICRL_UART 0x0C000000
252#define SICRL_GPIO_A 0x02000000
253#define SICRL_GPIO_B 0x01000000
254#define SICRL_GPIO_C 0x00800000
255#define SICRL_GPIO_D 0x00400000
256#define SICRL_GPIO_E 0x00200000
257#define SICRL_GPIO_F 0x00180000
258#define SICRL_GPIO_G 0x00040000
259#define SICRL_GPIO_H 0x00020000
260#define SICRL_GPIO_I 0x00010000
261#define SICRL_GPIO_J 0x00008000
262#define SICRL_GPIO_K 0x00004000
263#define SICRL_GPIO_L 0x00003000
264#define SICRL_DMA_A 0x00000800
265#define SICRL_DMA_B 0x00000400
266#define SICRL_DMA_C 0x00000200
267#define SICRL_DMA_D 0x00000100
268#define SICRL_DMA_E 0x00000080
269#define SICRL_DMA_F 0x00000040
270#define SICRL_DMA_G 0x00000020
271#define SICRL_DMA_H 0x00000010
272#define SICRL_DMA_I 0x00000008
273#define SICRL_DMA_J 0x00000004
274#define SICRL_LDP_A 0x00000002
275#define SICRL_LDP_B 0x00000001
276
Mario Six8439e992019-01-21 09:17:29 +0100277/* SICRH bits - MPC837X specific */
Dave Liu03051c32007-09-18 12:36:11 +0800278#define SICRH_DDR 0x80000000
279#define SICRH_TSEC1_A 0x10000000
280#define SICRH_TSEC1_B 0x08000000
281#define SICRH_TSEC2_A 0x00400000
282#define SICRH_TSEC2_B 0x00200000
283#define SICRH_TSEC2_C 0x00100000
284#define SICRH_TSEC2_D 0x00080000
285#define SICRH_TSEC2_E 0x00040000
286#define SICRH_TMR 0x00010000
287#define SICRH_GPIO2_A 0x00008000
288#define SICRH_GPIO2_B 0x00004000
289#define SICRH_GPIO2_C 0x00002000
290#define SICRH_GPIO2_D 0x00001000
291#define SICRH_GPIO2_E 0x00000C00
Andy Fleminge1ac3872008-10-30 16:50:14 -0500292#define SICRH_GPIO2_E_SD 0x00000800
Dave Liu03051c32007-09-18 12:36:11 +0800293#define SICRH_GPIO2_F 0x00000300
294#define SICRH_GPIO2_G 0x000000C0
295#define SICRH_GPIO2_H 0x00000030
296#define SICRH_SPI 0x00000003
Andy Fleminge1ac3872008-10-30 16:50:14 -0500297#define SICRH_SPI_SD 0x00000001
Ilya Yanokf3ce2502010-09-17 23:41:48 +0200298
Mario Six4bc97a32019-01-21 09:17:24 +0100299#elif defined(CONFIG_ARCH_MPC8308)
Ilya Yanokf3ce2502010-09-17 23:41:48 +0200300/* SICRL bits - MPC8308 specific */
301#define SICRL_SPI_PF0 (0 << 28)
302#define SICRL_SPI_PF1 (1 << 28)
303#define SICRL_SPI_PF3 (3 << 28)
304#define SICRL_UART_PF0 (0 << 26)
305#define SICRL_UART_PF1 (1 << 26)
306#define SICRL_UART_PF3 (3 << 26)
307#define SICRL_IRQ_PF0 (0 << 24)
308#define SICRL_IRQ_PF1 (1 << 24)
309#define SICRL_I2C2_PF0 (0 << 20)
310#define SICRL_I2C2_PF1 (1 << 20)
311#define SICRL_ETSEC1_TX_CLK (0 << 6)
312#define SICRL_ETSEC1_GTX_CLK125 (1 << 6)
313
314/* SICRH bits - MPC8308 specific */
315#define SICRH_ESDHC_A_SD (0 << 30)
316#define SICRH_ESDHC_A_GTM (1 << 30)
317#define SICRH_ESDHC_A_GPIO (3 << 30)
318#define SICRH_ESDHC_B_SD (0 << 28)
319#define SICRH_ESDHC_B_GTM (1 << 28)
320#define SICRH_ESDHC_B_GPIO (3 << 28)
321#define SICRH_ESDHC_C_SD (0 << 26)
322#define SICRH_ESDHC_C_GTM (1 << 26)
323#define SICRH_ESDHC_C_GPIO (3 << 26)
324#define SICRH_GPIO_A_GPIO (0 << 24)
325#define SICRH_GPIO_A_TSEC2 (1 << 24)
326#define SICRH_GPIO_B_GPIO (0 << 22)
327#define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22)
328#define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22)
329#define SICRH_IEEE1588_A_TMR (1 << 20)
330#define SICRH_IEEE1588_A_GPIO (3 << 20)
331#define SICRH_USB (1 << 18)
332#define SICRH_GTM_GTM (1 << 16)
333#define SICRH_GTM_GPIO (3 << 16)
334#define SICRH_IEEE1588_B_TMR (1 << 14)
335#define SICRH_IEEE1588_B_GPIO (3 << 14)
336#define SICRH_ETSEC2_CRS (1 << 12)
337#define SICRH_ETSEC2_GPIO (3 << 12)
338#define SICRH_GPIOSEL_0 (0 << 8)
339#define SICRH_GPIOSEL_1 (1 << 8)
340#define SICRH_TMROBI_V3P3 (0 << 4)
341#define SICRH_TMROBI_V2P5 (1 << 4)
342#define SICRH_TSOBI1_V3P3 (0 << 1)
343#define SICRH_TSOBI1_V2P5 (1 << 1)
344#define SICRH_TSOBI2_V3P3 (0 << 0)
345#define SICRH_TSOBI2_V2P5 (1 << 0)
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000346
Mario Six4bc97a32019-01-21 09:17:24 +0100347#elif defined(CONFIG_ARCH_MPC8309)
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000348/* SICR_1 */
349#define SICR_1_UART1_UART1S (0 << (30-2))
350#define SICR_1_UART1_UART1RTS (1 << (30-2))
351#define SICR_1_I2C_I2C (0 << (30-4))
352#define SICR_1_I2C_CKSTOP (1 << (30-4))
353#define SICR_1_IRQ_A_IRQ (0 << (30-6))
354#define SICR_1_IRQ_A_MCP (1 << (30-6))
355#define SICR_1_IRQ_B_IRQ (0 << (30-8))
356#define SICR_1_IRQ_B_CKSTOP (1 << (30-8))
357#define SICR_1_GPIO_A_GPIO (0 << (30-10))
358#define SICR_1_GPIO_A_SD (2 << (30-10))
359#define SICR_1_GPIO_A_DDR (3 << (30-10))
360#define SICR_1_GPIO_B_GPIO (0 << (30-12))
361#define SICR_1_GPIO_B_SD (2 << (30-12))
362#define SICR_1_GPIO_B_QE (3 << (30-12))
363#define SICR_1_GPIO_C_GPIO (0 << (30-14))
364#define SICR_1_GPIO_C_CAN (1 << (30-14))
365#define SICR_1_GPIO_C_DDR (2 << (30-14))
366#define SICR_1_GPIO_C_LCS (3 << (30-14))
367#define SICR_1_GPIO_D_GPIO (0 << (30-16))
368#define SICR_1_GPIO_D_CAN (1 << (30-16))
369#define SICR_1_GPIO_D_DDR (2 << (30-16))
370#define SICR_1_GPIO_D_LCS (3 << (30-16))
371#define SICR_1_GPIO_E_GPIO (0 << (30-18))
372#define SICR_1_GPIO_E_CAN (1 << (30-18))
373#define SICR_1_GPIO_E_DDR (2 << (30-18))
374#define SICR_1_GPIO_E_LCS (3 << (30-18))
375#define SICR_1_GPIO_F_GPIO (0 << (30-20))
376#define SICR_1_GPIO_F_CAN (1 << (30-20))
377#define SICR_1_GPIO_F_CK (2 << (30-20))
378#define SICR_1_USB_A_USBDR (0 << (30-22))
379#define SICR_1_USB_A_UART2S (1 << (30-22))
380#define SICR_1_USB_B_USBDR (0 << (30-24))
381#define SICR_1_USB_B_UART2S (1 << (30-24))
382#define SICR_1_USB_B_UART2RTS (2 << (30-24))
383#define SICR_1_USB_C_USBDR (0 << (30-26))
384#define SICR_1_USB_C_QE_EXT (3 << (30-26))
385#define SICR_1_FEC1_FEC1 (0 << (30-28))
386#define SICR_1_FEC1_GTM (1 << (30-28))
387#define SICR_1_FEC1_GPIO (2 << (30-28))
388#define SICR_1_FEC2_FEC2 (0 << (30-30))
389#define SICR_1_FEC2_GTM (1 << (30-30))
390#define SICR_1_FEC2_GPIO (2 << (30-30))
391/* SICR_2 */
392#define SICR_2_FEC3_FEC3 (0 << (30-0))
393#define SICR_2_FEC3_TMR (1 << (30-0))
394#define SICR_2_FEC3_GPIO (2 << (30-0))
395#define SICR_2_HDLC1_A_HDLC1 (0 << (30-2))
396#define SICR_2_HDLC1_A_GPIO (1 << (30-2))
397#define SICR_2_HDLC1_A_TDM1 (2 << (30-2))
398#define SICR_2_ELBC_A_LA (0 << (30-4))
399#define SICR_2_ELBC_B_LCLK (0 << (30-6))
400#define SICR_2_HDLC2_A_HDLC2 (0 << (30-8))
401#define SICR_2_HDLC2_A_GPIO (0 << (30-8))
402#define SICR_2_HDLC2_A_TDM2 (0 << (30-8))
403/* bits 10-11 unused */
404#define SICR_2_USB_D_USBDR (0 << (30-12))
405#define SICR_2_USB_D_GPIO (2 << (30-12))
406#define SICR_2_USB_D_QE_BRG (3 << (30-12))
407#define SICR_2_PCI_PCI (0 << (30-14))
408#define SICR_2_PCI_CPCI_HS (2 << (30-14))
409#define SICR_2_HDLC1_B_HDLC1 (0 << (30-16))
410#define SICR_2_HDLC1_B_GPIO (1 << (30-16))
411#define SICR_2_HDLC1_B_QE_BRG (2 << (30-16))
412#define SICR_2_HDLC1_B_TDM1 (3 << (30-16))
413#define SICR_2_HDLC1_C_HDLC1 (0 << (30-18))
414#define SICR_2_HDLC1_C_GPIO (1 << (30-18))
415#define SICR_2_HDLC1_C_TDM1 (2 << (30-18))
416#define SICR_2_HDLC2_B_HDLC2 (0 << (30-20))
417#define SICR_2_HDLC2_B_GPIO (1 << (30-20))
418#define SICR_2_HDLC2_B_QE_BRG (2 << (30-20))
419#define SICR_2_HDLC2_B_TDM2 (3 << (30-20))
420#define SICR_2_HDLC2_C_HDLC2 (0 << (30-22))
421#define SICR_2_HDLC2_C_GPIO (1 << (30-22))
422#define SICR_2_HDLC2_C_TDM2 (2 << (30-22))
423#define SICR_2_HDLC2_C_QE_BRG (3 << (30-22))
424#define SICR_2_QUIESCE_B (0 << (30-24))
425
Dave Liue0803132006-12-07 21:11:58 +0800426#endif
427
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200428/*
429 * SWCRR - System Watchdog Control Register
Dave Liue0803132006-12-07 21:11:58 +0800430 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200431/* Register offset to immr */
432#define SWCRR 0x0204
433/* Software Watchdog Time Count */
434#define SWCRR_SWTC 0xFFFF0000
435/* Watchdog Enable bit */
436#define SWCRR_SWEN 0x00000004
437/* Software Watchdog Reset/Interrupt Select bit */
438#define SWCRR_SWRI 0x00000002
439/* Software Watchdog Counter Prescale bit */
440#define SWCRR_SWPR 0x00000001
441#define SWCRR_RES (~(SWCRR_SWTC | SWCRR_SWEN | \
442 SWCRR_SWRI | SWCRR_SWPR))
Dave Liue0803132006-12-07 21:11:58 +0800443
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200444/*
445 * SWCNR - System Watchdog Counter Register
Dave Liue0803132006-12-07 21:11:58 +0800446 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200447/* Register offset to immr */
448#define SWCNR 0x0208
449/* Software Watchdog Count mask */
450#define SWCNR_SWCN 0x0000FFFF
Dave Liue0803132006-12-07 21:11:58 +0800451#define SWCNR_RES ~(SWCNR_SWCN)
452
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200453/*
454 * SWSRR - System Watchdog Service Register
Dave Liue0803132006-12-07 21:11:58 +0800455 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200456/* Register offset to immr */
457#define SWSRR 0x020E
Dave Liue0803132006-12-07 21:11:58 +0800458
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200459/*
460 * ACR - Arbiter Configuration Register
Dave Liue0803132006-12-07 21:11:58 +0800461 */
462#define ACR_COREDIS 0x10000000 /* Core disable */
463#define ACR_COREDIS_SHIFT (31-7)
464#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */
465#define ACR_PIPE_DEP_SHIFT (31-15)
466#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */
467#define ACR_PCI_RPTCNT_SHIFT (31-19)
468#define ACR_RPTCNT 0x00000700 /* Repeat count */
469#define ACR_RPTCNT_SHIFT (31-23)
470#define ACR_APARK 0x00000030 /* Address parking */
471#define ACR_APARK_SHIFT (31-27)
472#define ACR_PARKM 0x0000000F /* Parking master */
473#define ACR_PARKM_SHIFT (31-31)
474
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200475/*
476 * ATR - Arbiter Timers Register
Dave Liue0803132006-12-07 21:11:58 +0800477 */
478#define ATR_DTO 0x00FF0000 /* Data time out */
Nick Spence002d27c2008-08-22 23:52:40 -0700479#define ATR_DTO_SHIFT 16
Dave Liue0803132006-12-07 21:11:58 +0800480#define ATR_ATO 0x000000FF /* Address time out */
Nick Spence002d27c2008-08-22 23:52:40 -0700481#define ATR_ATO_SHIFT 0
Dave Liue0803132006-12-07 21:11:58 +0800482
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200483/*
484 * AER - Arbiter Event Register
Dave Liue0803132006-12-07 21:11:58 +0800485 */
486#define AER_ETEA 0x00000020 /* Transfer error */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200487/* Reserved transfer type */
488#define AER_RES 0x00000010
489/* External control word transfer type */
490#define AER_ECW 0x00000008
491/* Address Only transfer type */
492#define AER_AO 0x00000004
Dave Liue0803132006-12-07 21:11:58 +0800493#define AER_DTO 0x00000002 /* Data time out */
494#define AER_ATO 0x00000001 /* Address time out */
495
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200496/*
497 * AEATR - Arbiter Event Address Register
Dave Liue0803132006-12-07 21:11:58 +0800498 */
499#define AEATR_EVENT 0x07000000 /* Event type */
Nick Spence002d27c2008-08-22 23:52:40 -0700500#define AEATR_EVENT_SHIFT 24
Dave Liue0803132006-12-07 21:11:58 +0800501#define AEATR_MSTR_ID 0x001F0000 /* Master Id */
Nick Spence002d27c2008-08-22 23:52:40 -0700502#define AEATR_MSTR_ID_SHIFT 16
Dave Liue0803132006-12-07 21:11:58 +0800503#define AEATR_TBST 0x00000800 /* Transfer burst */
Nick Spence002d27c2008-08-22 23:52:40 -0700504#define AEATR_TBST_SHIFT 11
Dave Liue0803132006-12-07 21:11:58 +0800505#define AEATR_TSIZE 0x00000700 /* Transfer Size */
Nick Spence002d27c2008-08-22 23:52:40 -0700506#define AEATR_TSIZE_SHIFT 8
Dave Liue0803132006-12-07 21:11:58 +0800507#define AEATR_TTYPE 0x0000001F /* Transfer Type */
Nick Spence002d27c2008-08-22 23:52:40 -0700508#define AEATR_TTYPE_SHIFT 0
Dave Liue0803132006-12-07 21:11:58 +0800509
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200510/*
511 * HRCWL - Hard Reset Configuration Word Low
Dave Liue0803132006-12-07 21:11:58 +0800512 */
513#define HRCWL_LBIUCM 0x80000000
514#define HRCWL_LBIUCM_SHIFT 31
515#define HRCWL_LCL_BUS_TO_SCB_CLK_1X1 0x00000000
516#define HRCWL_LCL_BUS_TO_SCB_CLK_2X1 0x80000000
517
518#define HRCWL_DDRCM 0x40000000
519#define HRCWL_DDRCM_SHIFT 30
520#define HRCWL_DDR_TO_SCB_CLK_1X1 0x00000000
521#define HRCWL_DDR_TO_SCB_CLK_2X1 0x40000000
522
523#define HRCWL_SPMF 0x0f000000
524#define HRCWL_SPMF_SHIFT 24
525#define HRCWL_CSB_TO_CLKIN_16X1 0x00000000
526#define HRCWL_CSB_TO_CLKIN_1X1 0x01000000
527#define HRCWL_CSB_TO_CLKIN_2X1 0x02000000
528#define HRCWL_CSB_TO_CLKIN_3X1 0x03000000
529#define HRCWL_CSB_TO_CLKIN_4X1 0x04000000
530#define HRCWL_CSB_TO_CLKIN_5X1 0x05000000
531#define HRCWL_CSB_TO_CLKIN_6X1 0x06000000
532#define HRCWL_CSB_TO_CLKIN_7X1 0x07000000
533#define HRCWL_CSB_TO_CLKIN_8X1 0x08000000
534#define HRCWL_CSB_TO_CLKIN_9X1 0x09000000
535#define HRCWL_CSB_TO_CLKIN_10X1 0x0A000000
536#define HRCWL_CSB_TO_CLKIN_11X1 0x0B000000
537#define HRCWL_CSB_TO_CLKIN_12X1 0x0C000000
538#define HRCWL_CSB_TO_CLKIN_13X1 0x0D000000
539#define HRCWL_CSB_TO_CLKIN_14X1 0x0E000000
540#define HRCWL_CSB_TO_CLKIN_15X1 0x0F000000
541
542#define HRCWL_VCO_BYPASS 0x00000000
543#define HRCWL_VCO_1X2 0x00000000
544#define HRCWL_VCO_1X4 0x00200000
545#define HRCWL_VCO_1X8 0x00400000
546
547#define HRCWL_COREPLL 0x007F0000
548#define HRCWL_COREPLL_SHIFT 16
549#define HRCWL_CORE_TO_CSB_BYPASS 0x00000000
550#define HRCWL_CORE_TO_CSB_1X1 0x00020000
551#define HRCWL_CORE_TO_CSB_1_5X1 0x00030000
552#define HRCWL_CORE_TO_CSB_2X1 0x00040000
553#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
554#define HRCWL_CORE_TO_CSB_3X1 0x00060000
555
Mario Six61abced2019-01-21 09:17:28 +0100556#if defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC832X)
Dave Liue0803132006-12-07 21:11:58 +0800557#define HRCWL_CEVCOD 0x000000C0
558#define HRCWL_CEVCOD_SHIFT 6
559#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
560#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
561#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
562
563#define HRCWL_CEPDF 0x00000020
564#define HRCWL_CEPDF_SHIFT 5
565#define HRCWL_CE_PLL_DIV_1X1 0x00000000
566#define HRCWL_CE_PLL_DIV_2X1 0x00000020
567
568#define HRCWL_CEPMF 0x0000001F
569#define HRCWL_CEPMF_SHIFT 0
570#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
571#define HRCWL_CE_TO_PLL_1X2 0x00000002
572#define HRCWL_CE_TO_PLL_1X3 0x00000003
573#define HRCWL_CE_TO_PLL_1X4 0x00000004
574#define HRCWL_CE_TO_PLL_1X5 0x00000005
575#define HRCWL_CE_TO_PLL_1X6 0x00000006
576#define HRCWL_CE_TO_PLL_1X7 0x00000007
577#define HRCWL_CE_TO_PLL_1X8 0x00000008
578#define HRCWL_CE_TO_PLL_1X9 0x00000009
579#define HRCWL_CE_TO_PLL_1X10 0x0000000A
580#define HRCWL_CE_TO_PLL_1X11 0x0000000B
581#define HRCWL_CE_TO_PLL_1X12 0x0000000C
582#define HRCWL_CE_TO_PLL_1X13 0x0000000D
583#define HRCWL_CE_TO_PLL_1X14 0x0000000E
584#define HRCWL_CE_TO_PLL_1X15 0x0000000F
585#define HRCWL_CE_TO_PLL_1X16 0x00000010
586#define HRCWL_CE_TO_PLL_1X17 0x00000011
587#define HRCWL_CE_TO_PLL_1X18 0x00000012
588#define HRCWL_CE_TO_PLL_1X19 0x00000013
589#define HRCWL_CE_TO_PLL_1X20 0x00000014
590#define HRCWL_CE_TO_PLL_1X21 0x00000015
591#define HRCWL_CE_TO_PLL_1X22 0x00000016
592#define HRCWL_CE_TO_PLL_1X23 0x00000017
593#define HRCWL_CE_TO_PLL_1X24 0x00000018
594#define HRCWL_CE_TO_PLL_1X25 0x00000019
595#define HRCWL_CE_TO_PLL_1X26 0x0000001A
596#define HRCWL_CE_TO_PLL_1X27 0x0000001B
597#define HRCWL_CE_TO_PLL_1X28 0x0000001C
598#define HRCWL_CE_TO_PLL_1X29 0x0000001D
599#define HRCWL_CE_TO_PLL_1X30 0x0000001E
600#define HRCWL_CE_TO_PLL_1X31 0x0000001F
Dave Liu03051c32007-09-18 12:36:11 +0800601
Tom Rini139ff3b2021-05-14 21:34:27 -0400602#elif defined(CONFIG_ARCH_MPC8308)
Dave Liu6f3931a2008-01-10 23:06:05 +0800603#define HRCWL_SVCOD 0x30000000
604#define HRCWL_SVCOD_SHIFT 28
605#define HRCWL_SVCOD_DIV_2 0x00000000
606#define HRCWL_SVCOD_DIV_4 0x10000000
607#define HRCWL_SVCOD_DIV_8 0x20000000
608#define HRCWL_SVCOD_DIV_1 0x30000000
609
Mario Six8439e992019-01-21 09:17:29 +0100610#elif defined(CONFIG_ARCH_MPC837X)
Dave Liu03051c32007-09-18 12:36:11 +0800611#define HRCWL_SVCOD 0x30000000
612#define HRCWL_SVCOD_SHIFT 28
613#define HRCWL_SVCOD_DIV_4 0x00000000
614#define HRCWL_SVCOD_DIV_8 0x10000000
615#define HRCWL_SVCOD_DIV_2 0x20000000
616#define HRCWL_SVCOD_DIV_1 0x30000000
Mario Six4bc97a32019-01-21 09:17:24 +0100617#elif defined(CONFIG_ARCH_MPC8309)
Gerlando Falautoa88731a2012-10-10 22:13:08 +0000618
619#define HRCWL_CEVCOD 0x000000C0
620#define HRCWL_CEVCOD_SHIFT 6
621/*
622 * According to Errata MPC8309RMAD, Rev. 0.2, 9/2012
623 * these are different than with 8360, 832x
624 */
625#define HRCWL_CE_PLL_VCO_DIV_2 0x00000000
626#define HRCWL_CE_PLL_VCO_DIV_4 0x00000040
627#define HRCWL_CE_PLL_VCO_DIV_8 0x00000080
628
629#define HRCWL_CEPDF 0x00000020
630#define HRCWL_CEPDF_SHIFT 5
631#define HRCWL_CE_PLL_DIV_1X1 0x00000000
632#define HRCWL_CE_PLL_DIV_2X1 0x00000020
633
634#define HRCWL_CEPMF 0x0000001F
635#define HRCWL_CEPMF_SHIFT 0
636#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
637#define HRCWL_CE_TO_PLL_1X2 0x00000002
638#define HRCWL_CE_TO_PLL_1X3 0x00000003
639#define HRCWL_CE_TO_PLL_1X4 0x00000004
640#define HRCWL_CE_TO_PLL_1X5 0x00000005
641#define HRCWL_CE_TO_PLL_1X6 0x00000006
642#define HRCWL_CE_TO_PLL_1X7 0x00000007
643#define HRCWL_CE_TO_PLL_1X8 0x00000008
644#define HRCWL_CE_TO_PLL_1X9 0x00000009
645#define HRCWL_CE_TO_PLL_1X10 0x0000000A
646#define HRCWL_CE_TO_PLL_1X11 0x0000000B
647#define HRCWL_CE_TO_PLL_1X12 0x0000000C
648#define HRCWL_CE_TO_PLL_1X13 0x0000000D
649#define HRCWL_CE_TO_PLL_1X14 0x0000000E
650#define HRCWL_CE_TO_PLL_1X15 0x0000000F
651#define HRCWL_CE_TO_PLL_1X16 0x00000010
652#define HRCWL_CE_TO_PLL_1X17 0x00000011
653#define HRCWL_CE_TO_PLL_1X18 0x00000012
654#define HRCWL_CE_TO_PLL_1X19 0x00000013
655#define HRCWL_CE_TO_PLL_1X20 0x00000014
656#define HRCWL_CE_TO_PLL_1X21 0x00000015
657#define HRCWL_CE_TO_PLL_1X22 0x00000016
658#define HRCWL_CE_TO_PLL_1X23 0x00000017
659#define HRCWL_CE_TO_PLL_1X24 0x00000018
660#define HRCWL_CE_TO_PLL_1X25 0x00000019
661#define HRCWL_CE_TO_PLL_1X26 0x0000001A
662#define HRCWL_CE_TO_PLL_1X27 0x0000001B
663#define HRCWL_CE_TO_PLL_1X28 0x0000001C
664#define HRCWL_CE_TO_PLL_1X29 0x0000001D
665#define HRCWL_CE_TO_PLL_1X30 0x0000001E
666#define HRCWL_CE_TO_PLL_1X31 0x0000001F
667
668#define HRCWL_SVCOD 0x30000000
669#define HRCWL_SVCOD_SHIFT 28
670#define HRCWL_SVCOD_DIV_2 0x00000000
671#define HRCWL_SVCOD_DIV_4 0x10000000
672#define HRCWL_SVCOD_DIV_8 0x20000000
673#define HRCWL_SVCOD_DIV_1 0x30000000
Dave Liue0803132006-12-07 21:11:58 +0800674#endif
675
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200676/*
677 * HRCWH - Hardware Reset Configuration Word High
Dave Liue0803132006-12-07 21:11:58 +0800678 */
679#define HRCWH_PCI_HOST 0x80000000
680#define HRCWH_PCI_HOST_SHIFT 31
681#define HRCWH_PCI_AGENT 0x00000000
682
Mario Sixd5cfa4a2019-01-21 09:17:27 +0100683#if defined(CONFIG_ARCH_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +0800684#define HRCWH_32_BIT_PCI 0x00000000
685#define HRCWH_64_BIT_PCI 0x40000000
686#endif
687
688#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
689#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
690
691#define HRCWH_PCI_ARBITER_DISABLE 0x00000000
692#define HRCWH_PCI_ARBITER_ENABLE 0x20000000
693
Mario Sixd5cfa4a2019-01-21 09:17:27 +0100694#if defined(CONFIG_ARCH_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +0800695#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
696#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
697
Mario Six61abced2019-01-21 09:17:28 +0100698#elif defined(CONFIG_ARCH_MPC8360)
Dave Liue0803132006-12-07 21:11:58 +0800699#define HRCWH_PCICKDRV_DISABLE 0x00000000
700#define HRCWH_PCICKDRV_ENABLE 0x10000000
701#endif
702
703#define HRCWH_CORE_DISABLE 0x08000000
704#define HRCWH_CORE_ENABLE 0x00000000
705
706#define HRCWH_FROM_0X00000100 0x00000000
707#define HRCWH_FROM_0XFFF00100 0x04000000
708
709#define HRCWH_BOOTSEQ_DISABLE 0x00000000
710#define HRCWH_BOOTSEQ_NORMAL 0x01000000
711#define HRCWH_BOOTSEQ_EXTENDED 0x02000000
712
713#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
714#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
715
716#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
717#define HRCWH_ROM_LOC_PCI1 0x00100000
Mario Sixd5cfa4a2019-01-21 09:17:27 +0100718#if defined(CONFIG_ARCH_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +0800719#define HRCWH_ROM_LOC_PCI2 0x00200000
720#endif
Mario Six8439e992019-01-21 09:17:29 +0100721#if defined(CONFIG_ARCH_MPC837X)
Dave Liu03051c32007-09-18 12:36:11 +0800722#define HRCWH_ROM_LOC_ON_CHIP_ROM 0x00300000
723#endif
Dave Liue0803132006-12-07 21:11:58 +0800724#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
725#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
726#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
727
Mario Six9403fc42019-01-21 09:17:25 +0100728#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six8439e992019-01-21 09:17:29 +0100729 defined(CONFIG_ARCH_MPC837X)
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200730#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
Scott Woodd87c57b2007-04-16 14:31:55 -0500731#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200732#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000
Scott Woodd87c57b2007-04-16 14:31:55 -0500733#define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000
734
735#define HRCWH_RL_EXT_LEGACY 0x00000000
736#define HRCWH_RL_EXT_NAND 0x00040000
737
Anton Vorontsove6d9c892008-10-02 18:31:59 +0400738#define HRCWH_TSEC1M_MASK 0x0000E000
Scott Woodd87c57b2007-04-16 14:31:55 -0500739#define HRCWH_TSEC1M_IN_MII 0x00000000
740#define HRCWH_TSEC1M_IN_RMII 0x00002000
741#define HRCWH_TSEC1M_IN_RGMII 0x00006000
742#define HRCWH_TSEC1M_IN_RTBI 0x0000A000
743#define HRCWH_TSEC1M_IN_SGMII 0x0000C000
744
Anton Vorontsove6d9c892008-10-02 18:31:59 +0400745#define HRCWH_TSEC2M_MASK 0x00001C00
Scott Woodd87c57b2007-04-16 14:31:55 -0500746#define HRCWH_TSEC2M_IN_MII 0x00000000
747#define HRCWH_TSEC2M_IN_RMII 0x00000400
748#define HRCWH_TSEC2M_IN_RGMII 0x00000C00
749#define HRCWH_TSEC2M_IN_RTBI 0x00001400
750#define HRCWH_TSEC2M_IN_SGMII 0x00001800
751#endif
752
Mario Sixd5cfa4a2019-01-21 09:17:27 +0100753#if defined(CONFIG_ARCH_MPC834X)
Dave Liue0803132006-12-07 21:11:58 +0800754#define HRCWH_TSEC1M_IN_RGMII 0x00000000
755#define HRCWH_TSEC1M_IN_RTBI 0x00004000
756#define HRCWH_TSEC1M_IN_GMII 0x00008000
757#define HRCWH_TSEC1M_IN_TBI 0x0000C000
758#define HRCWH_TSEC2M_IN_RGMII 0x00000000
759#define HRCWH_TSEC2M_IN_RTBI 0x00001000
760#define HRCWH_TSEC2M_IN_GMII 0x00002000
761#define HRCWH_TSEC2M_IN_TBI 0x00003000
762#endif
763
Mario Six61abced2019-01-21 09:17:28 +0100764#if defined(CONFIG_ARCH_MPC8360)
Dave Liue0803132006-12-07 21:11:58 +0800765#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
766#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
767#endif
768
769#define HRCWH_BIG_ENDIAN 0x00000000
770#define HRCWH_LITTLE_ENDIAN 0x00000008
771
772#define HRCWH_LALE_NORMAL 0x00000000
773#define HRCWH_LALE_EARLY 0x00000004
774
775#define HRCWH_LDP_SET 0x00000000
776#define HRCWH_LDP_CLEAR 0x00000002
777
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200778/*
779 * RSR - Reset Status Register
Dave Liue0803132006-12-07 21:11:58 +0800780 */
Mario Six9403fc42019-01-21 09:17:25 +0100781#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
Mario Six8439e992019-01-21 09:17:29 +0100782 defined(CONFIG_ARCH_MPC837X)
Dave Liu03051c32007-09-18 12:36:11 +0800783#define RSR_RSTSRC 0xF0000000 /* Reset source */
784#define RSR_RSTSRC_SHIFT 28
785#else
Dave Liue0803132006-12-07 21:11:58 +0800786#define RSR_RSTSRC 0xE0000000 /* Reset source */
787#define RSR_RSTSRC_SHIFT 29
Dave Liu03051c32007-09-18 12:36:11 +0800788#endif
Dave Liue0803132006-12-07 21:11:58 +0800789#define RSR_BSF 0x00010000 /* Boot seq. fail */
790#define RSR_BSF_SHIFT 16
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200791/* software soft reset */
792#define RSR_SWSR 0x00002000
Dave Liue0803132006-12-07 21:11:58 +0800793#define RSR_SWSR_SHIFT 13
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200794/* software hard reset */
795#define RSR_SWHR 0x00001000
Dave Liue0803132006-12-07 21:11:58 +0800796#define RSR_SWHR_SHIFT 12
797#define RSR_JHRS 0x00000200 /* jtag hreset */
798#define RSR_JHRS_SHIFT 9
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200799/* jtag sreset status */
800#define RSR_JSRS 0x00000100
Dave Liue0803132006-12-07 21:11:58 +0800801#define RSR_JSRS_SHIFT 8
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200802/* checkstop reset status */
803#define RSR_CSHR 0x00000010
Dave Liue0803132006-12-07 21:11:58 +0800804#define RSR_CSHR_SHIFT 4
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200805/* software watchdog reset status */
806#define RSR_SWRS 0x00000008
Dave Liue0803132006-12-07 21:11:58 +0800807#define RSR_SWRS_SHIFT 3
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200808/* bus monitop reset status */
809#define RSR_BMRS 0x00000004
Dave Liue0803132006-12-07 21:11:58 +0800810#define RSR_BMRS_SHIFT 2
811#define RSR_SRS 0x00000002 /* soft reset status */
812#define RSR_SRS_SHIFT 1
813#define RSR_HRS 0x00000001 /* hard reset status */
814#define RSR_HRS_SHIFT 0
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200815#define RSR_RES (~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | \
816 RSR_SWHR | RSR_JHRS | \
817 RSR_JSRS | RSR_CSHR | \
818 RSR_SWRS | RSR_BMRS | \
819 RSR_SRS | RSR_HRS))
820/*
821 * RMR - Reset Mode Register
Dave Liue0803132006-12-07 21:11:58 +0800822 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200823/* checkstop reset enable */
824#define RMR_CSRE 0x00000001
Dave Liue0803132006-12-07 21:11:58 +0800825#define RMR_CSRE_SHIFT 0
826#define RMR_RES ~(RMR_CSRE)
827
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200828/*
829 * RCR - Reset Control Register
Dave Liue0803132006-12-07 21:11:58 +0800830 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200831/* software hard reset */
832#define RCR_SWHR 0x00000002
833/* software soft reset */
834#define RCR_SWSR 0x00000001
Dave Liue0803132006-12-07 21:11:58 +0800835#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
836
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200837/*
838 * RCER - Reset Control Enable Register
Dave Liue0803132006-12-07 21:11:58 +0800839 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200840/* software hard reset */
841#define RCER_CRE 0x00000001
Dave Liue0803132006-12-07 21:11:58 +0800842#define RCER_RES ~(RCER_CRE)
843
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200844/*
845 * SPMR - System PLL Mode Register
Dave Liue0803132006-12-07 21:11:58 +0800846 */
847#define SPMR_LBIUCM 0x80000000
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100848#define SPMR_LBIUCM_SHIFT 31
Dave Liue0803132006-12-07 21:11:58 +0800849#define SPMR_DDRCM 0x40000000
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100850#define SPMR_DDRCM_SHIFT 30
Dave Liue0803132006-12-07 21:11:58 +0800851#define SPMR_SPMF 0x0F000000
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100852#define SPMR_SPMF_SHIFT 24
Dave Liue0803132006-12-07 21:11:58 +0800853#define SPMR_CKID 0x00800000
854#define SPMR_CKID_SHIFT 23
855#define SPMR_COREPLL 0x007F0000
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100856#define SPMR_COREPLL_SHIFT 16
Dave Liue0803132006-12-07 21:11:58 +0800857#define SPMR_CEVCOD 0x000000C0
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100858#define SPMR_CEVCOD_SHIFT 6
Dave Liue0803132006-12-07 21:11:58 +0800859#define SPMR_CEPDF 0x00000020
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100860#define SPMR_CEPDF_SHIFT 5
Dave Liue0803132006-12-07 21:11:58 +0800861#define SPMR_CEPMF 0x0000001F
Joakim Tjernlund26e5f792011-01-27 16:30:54 +0100862#define SPMR_CEPMF_SHIFT 0
Dave Liue0803132006-12-07 21:11:58 +0800863
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200864/*
865 * OCCR - Output Clock Control Register
Dave Liue0803132006-12-07 21:11:58 +0800866 */
867#define OCCR_PCICOE0 0x80000000
868#define OCCR_PCICOE1 0x40000000
869#define OCCR_PCICOE2 0x20000000
870#define OCCR_PCICOE3 0x10000000
871#define OCCR_PCICOE4 0x08000000
872#define OCCR_PCICOE5 0x04000000
873#define OCCR_PCICOE6 0x02000000
874#define OCCR_PCICOE7 0x01000000
875#define OCCR_PCICD0 0x00800000
876#define OCCR_PCICD1 0x00400000
877#define OCCR_PCICD2 0x00200000
878#define OCCR_PCICD3 0x00100000
879#define OCCR_PCICD4 0x00080000
880#define OCCR_PCICD5 0x00040000
881#define OCCR_PCICD6 0x00020000
882#define OCCR_PCICD7 0x00010000
883#define OCCR_PCI1CR 0x00000002
884#define OCCR_PCI2CR 0x00000001
885#define OCCR_PCICR OCCR_PCI1CR
886
Heiko Schocher4e8b7502011-09-26 13:36:53 +0200887/*
888 * SCCR - System Clock Control Register
Dave Liue0803132006-12-07 21:11:58 +0800889 */
890#define SCCR_ENCCM 0x03000000
891#define SCCR_ENCCM_SHIFT 24
892#define SCCR_ENCCM_0 0x00000000
893#define SCCR_ENCCM_1 0x01000000
894#define SCCR_ENCCM_2 0x02000000
895#define SCCR_ENCCM_3 0x03000000
896
897#define SCCR_PCICM 0x00010000
898#define SCCR_PCICM_SHIFT 16
899
Mario Sixd5cfa4a2019-01-21 09:17:27 +0100900#if defined(CONFIG_ARCH_MPC834X)
901/* SCCR bits - MPC834X specific */
Dave Liue0803132006-12-07 21:11:58 +0800902#define SCCR_TSEC1CM 0xc0000000
903#define SCCR_TSEC1CM_SHIFT 30
904#define SCCR_TSEC1CM_0 0x00000000
905#define SCCR_TSEC1CM_1 0x40000000
906#define SCCR_TSEC1CM_2 0x80000000
907#define SCCR_TSEC1CM_3 0xC0000000
908
909#define SCCR_TSEC2CM 0x30000000
910#define SCCR_TSEC2CM_SHIFT 28
911#define SCCR_TSEC2CM_0 0x00000000
912#define SCCR_TSEC2CM_1 0x10000000
913#define SCCR_TSEC2CM_2 0x20000000
914#define SCCR_TSEC2CM_3 0x30000000
Scott Woodd87c57b2007-04-16 14:31:55 -0500915
Dave Liu03051c32007-09-18 12:36:11 +0800916/* The MPH must have the same clock ratio as DR, unless its clock disabled */
917#define SCCR_USBMPHCM 0x00c00000
918#define SCCR_USBMPHCM_SHIFT 22
919#define SCCR_USBDRCM 0x00300000
920#define SCCR_USBDRCM_SHIFT 20
921#define SCCR_USBCM 0x00f00000
922#define SCCR_USBCM_SHIFT 20
923#define SCCR_USBCM_0 0x00000000
924#define SCCR_USBCM_1 0x00500000
925#define SCCR_USBCM_2 0x00A00000
926#define SCCR_USBCM_3 0x00F00000
927
Mario Six9403fc42019-01-21 09:17:25 +0100928#elif defined(CONFIG_ARCH_MPC8313)
Dave Liua8cb43a2008-01-17 18:23:19 +0800929/* TSEC1 bits are for TSEC2 as well */
Scott Woodd87c57b2007-04-16 14:31:55 -0500930#define SCCR_TSEC1CM 0xc0000000
931#define SCCR_TSEC1CM_SHIFT 30
Kim Phillips9e896472008-01-16 12:06:16 -0600932#define SCCR_TSEC1CM_0 0x00000000
Scott Woodd87c57b2007-04-16 14:31:55 -0500933#define SCCR_TSEC1CM_1 0x40000000
934#define SCCR_TSEC1CM_2 0x80000000
935#define SCCR_TSEC1CM_3 0xC0000000
936
937#define SCCR_TSEC1ON 0x20000000
Timur Tabidf33f6b2007-07-03 13:04:34 -0500938#define SCCR_TSEC1ON_SHIFT 29
Scott Woodd87c57b2007-04-16 14:31:55 -0500939#define SCCR_TSEC2ON 0x10000000
Timur Tabidf33f6b2007-07-03 13:04:34 -0500940#define SCCR_TSEC2ON_SHIFT 28
Scott Woodd87c57b2007-04-16 14:31:55 -0500941
Dave Liue0803132006-12-07 21:11:58 +0800942#define SCCR_USBDRCM 0x00300000
943#define SCCR_USBDRCM_SHIFT 20
Dave Liu03051c32007-09-18 12:36:11 +0800944#define SCCR_USBDRCM_0 0x00000000
945#define SCCR_USBDRCM_1 0x00100000
946#define SCCR_USBDRCM_2 0x00200000
947#define SCCR_USBDRCM_3 0x00300000
Dave Liue0803132006-12-07 21:11:58 +0800948
Tom Rini139ff3b2021-05-14 21:34:27 -0400949#elif defined(CONFIG_ARCH_MPC8308)
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400950/* SCCR bits - MPC8315/MPC8308 specific */
Dave Liu555da612007-09-18 12:36:58 +0800951#define SCCR_TSEC1CM 0xc0000000
952#define SCCR_TSEC1CM_SHIFT 30
953#define SCCR_TSEC1CM_0 0x00000000
954#define SCCR_TSEC1CM_1 0x40000000
955#define SCCR_TSEC1CM_2 0x80000000
956#define SCCR_TSEC1CM_3 0xC0000000
957
958#define SCCR_TSEC2CM 0x30000000
959#define SCCR_TSEC2CM_SHIFT 28
960#define SCCR_TSEC2CM_0 0x00000000
961#define SCCR_TSEC2CM_1 0x10000000
962#define SCCR_TSEC2CM_2 0x20000000
963#define SCCR_TSEC2CM_3 0x30000000
964
Ilya Yanok7c619dd2010-06-28 16:44:33 +0400965#define SCCR_SDHCCM 0x0c000000
966#define SCCR_SDHCCM_SHIFT 26
967#define SCCR_SDHCCM_0 0x00000000
968#define SCCR_SDHCCM_1 0x04000000
969#define SCCR_SDHCCM_2 0x08000000
970#define SCCR_SDHCCM_3 0x0c000000
971
Dave Liu6f3931a2008-01-10 23:06:05 +0800972#define SCCR_USBDRCM 0x00c00000
973#define SCCR_USBDRCM_SHIFT 22
Dave Liu555da612007-09-18 12:36:58 +0800974#define SCCR_USBDRCM_0 0x00000000
Dave Liu6f3931a2008-01-10 23:06:05 +0800975#define SCCR_USBDRCM_1 0x00400000
976#define SCCR_USBDRCM_2 0x00800000
977#define SCCR_USBDRCM_3 0x00c00000
Dave Liu555da612007-09-18 12:36:58 +0800978
Dave Liu6f3931a2008-01-10 23:06:05 +0800979#define SCCR_SATA1CM 0x00003000
980#define SCCR_SATA1CM_SHIFT 12
981#define SCCR_SATACM 0x00003c00
982#define SCCR_SATACM_SHIFT 10
Dave Liu555da612007-09-18 12:36:58 +0800983#define SCCR_SATACM_0 0x00000000
Dave Liu6f3931a2008-01-10 23:06:05 +0800984#define SCCR_SATACM_1 0x00001400
985#define SCCR_SATACM_2 0x00002800
986#define SCCR_SATACM_3 0x00003c00
Dave Liu555da612007-09-18 12:36:58 +0800987
Dave Liu6f3931a2008-01-10 23:06:05 +0800988#define SCCR_TDMCM 0x00000030
989#define SCCR_TDMCM_SHIFT 4
Dave Liu555da612007-09-18 12:36:58 +0800990#define SCCR_TDMCM_0 0x00000000
Dave Liu6f3931a2008-01-10 23:06:05 +0800991#define SCCR_TDMCM_1 0x00000010
992#define SCCR_TDMCM_2 0x00000020
993#define SCCR_TDMCM_3 0x00000030
Dave Liu555da612007-09-18 12:36:58 +0800994
Mario Six8439e992019-01-21 09:17:29 +0100995#elif defined(CONFIG_ARCH_MPC837X)
996/* SCCR bits - MPC837X specific */
Dave Liu03051c32007-09-18 12:36:11 +0800997#define SCCR_TSEC1CM 0xc0000000
998#define SCCR_TSEC1CM_SHIFT 30
999#define SCCR_TSEC1CM_0 0x00000000
1000#define SCCR_TSEC1CM_1 0x40000000
1001#define SCCR_TSEC1CM_2 0x80000000
1002#define SCCR_TSEC1CM_3 0xC0000000
1003
1004#define SCCR_TSEC2CM 0x30000000
1005#define SCCR_TSEC2CM_SHIFT 28
1006#define SCCR_TSEC2CM_0 0x00000000
1007#define SCCR_TSEC2CM_1 0x10000000
1008#define SCCR_TSEC2CM_2 0x20000000
1009#define SCCR_TSEC2CM_3 0x30000000
1010
1011#define SCCR_SDHCCM 0x0c000000
1012#define SCCR_SDHCCM_SHIFT 26
1013#define SCCR_SDHCCM_0 0x00000000
1014#define SCCR_SDHCCM_1 0x04000000
1015#define SCCR_SDHCCM_2 0x08000000
1016#define SCCR_SDHCCM_3 0x0c000000
1017
1018#define SCCR_USBDRCM 0x00c00000
1019#define SCCR_USBDRCM_SHIFT 22
1020#define SCCR_USBDRCM_0 0x00000000
1021#define SCCR_USBDRCM_1 0x00400000
1022#define SCCR_USBDRCM_2 0x00800000
1023#define SCCR_USBDRCM_3 0x00c00000
1024
Anton Vorontsovfd6646c2009-01-08 04:26:12 +03001025/* All of the four SATA controllers must have the same clock ratio */
1026#define SCCR_SATA1CM 0x000000c0
1027#define SCCR_SATA1CM_SHIFT 6
1028#define SCCR_SATACM 0x000000ff
1029#define SCCR_SATACM_SHIFT 0
1030#define SCCR_SATACM_0 0x00000000
1031#define SCCR_SATACM_1 0x00000055
1032#define SCCR_SATACM_2 0x000000aa
1033#define SCCR_SATACM_3 0x000000ff
Mario Six4bc97a32019-01-21 09:17:24 +01001034#elif defined(CONFIG_ARCH_MPC8309)
Gerlando Falautoa88731a2012-10-10 22:13:08 +00001035/* SCCR bits - MPC8309 specific */
1036#define SCCR_SDHCCM 0x0c000000
1037#define SCCR_SDHCCM_SHIFT 26
1038#define SCCR_SDHCCM_0 0x00000000
1039#define SCCR_SDHCCM_1 0x04000000
1040#define SCCR_SDHCCM_2 0x08000000
1041#define SCCR_SDHCCM_3 0x0c000000
1042
1043#define SCCR_USBDRCM 0x00c00000
1044#define SCCR_USBDRCM_SHIFT 22
1045#define SCCR_USBDRCM_0 0x00000000
1046#define SCCR_USBDRCM_1 0x00400000
1047#define SCCR_USBDRCM_2 0x00800000
1048#define SCCR_USBDRCM_3 0x00c00000
Anton Vorontsovfd6646c2009-01-08 04:26:12 +03001049#endif
1050
Dave Liu03051c32007-09-18 12:36:11 +08001051#define SCCR_PCIEXP1CM 0x00300000
1052#define SCCR_PCIEXP1CM_SHIFT 20
1053#define SCCR_PCIEXP1CM_0 0x00000000
1054#define SCCR_PCIEXP1CM_1 0x00100000
1055#define SCCR_PCIEXP1CM_2 0x00200000
1056#define SCCR_PCIEXP1CM_3 0x00300000
1057
1058#define SCCR_PCIEXP2CM 0x000c0000
1059#define SCCR_PCIEXP2CM_SHIFT 18
1060#define SCCR_PCIEXP2CM_0 0x00000000
1061#define SCCR_PCIEXP2CM_1 0x00040000
1062#define SCCR_PCIEXP2CM_2 0x00080000
1063#define SCCR_PCIEXP2CM_3 0x000c0000
1064
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001065/*
1066 * CSn_BDNS - Chip Select memory Bounds Register
Dave Liue0803132006-12-07 21:11:58 +08001067 */
1068#define CSBNDS_SA 0x00FF0000
1069#define CSBNDS_SA_SHIFT 8
1070#define CSBNDS_EA 0x000000FF
1071#define CSBNDS_EA_SHIFT 24
1072
Mario Sixe4061552018-08-06 10:23:30 +02001073#ifndef CONFIG_MPC83XX_SDRAM
1074
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001075/*
1076 * CSn_CONFIG - Chip Select Configuration Register
Dave Liue0803132006-12-07 21:11:58 +08001077 */
1078#define CSCONFIG_EN 0x80000000
1079#define CSCONFIG_AP 0x00800000
Mario Six9403fc42019-01-21 09:17:25 +01001080#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X)
Joe Hershberger2fef4022011-10-11 23:57:29 -05001081#define CSCONFIG_ODT_RD_NEVER 0x00000000
1082#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
1083#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
1084#define CSCONFIG_ODT_RD_ALL 0x00400000
1085#define CSCONFIG_ODT_WR_NEVER 0x00000000
1086#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
1087#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
1088#define CSCONFIG_ODT_WR_ALL 0x00040000
Mario Sixbd3b8672019-01-21 09:17:26 +01001089#elif defined(CONFIG_ARCH_MPC832X)
Joe Hershberger2fef4022011-10-11 23:57:29 -05001090#define CSCONFIG_ODT_RD_CFG 0x00400000
Heiko Schocher6d2c26a2009-08-21 16:30:30 -05001091#define CSCONFIG_ODT_WR_CFG 0x00040000
Mario Six8439e992019-01-21 09:17:29 +01001092#elif defined(CONFIG_ARCH_MPC8360) || defined(CONFIG_ARCH_MPC837X)
Joe Hershberger2fef4022011-10-11 23:57:29 -05001093#define CSCONFIG_ODT_RD_NEVER 0x00000000
1094#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
1095#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
1096#define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000
1097#define CSCONFIG_ODT_RD_ALL 0x00400000
1098#define CSCONFIG_ODT_WR_NEVER 0x00000000
1099#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000
1100#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000
1101#define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000
1102#define CSCONFIG_ODT_WR_ALL 0x00040000
Heiko Schocher6d2c26a2009-08-21 16:30:30 -05001103#endif
Tor Krilld82b4fc2008-06-02 15:09:30 +02001104#define CSCONFIG_BANK_BIT_3 0x00004000
Dave Liue0803132006-12-07 21:11:58 +08001105#define CSCONFIG_ROW_BIT 0x00000700
1106#define CSCONFIG_ROW_BIT_12 0x00000000
1107#define CSCONFIG_ROW_BIT_13 0x00000100
1108#define CSCONFIG_ROW_BIT_14 0x00000200
1109#define CSCONFIG_COL_BIT 0x00000007
1110#define CSCONFIG_COL_BIT_8 0x00000000
1111#define CSCONFIG_COL_BIT_9 0x00000001
1112#define CSCONFIG_COL_BIT_10 0x00000002
1113#define CSCONFIG_COL_BIT_11 0x00000003
1114
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001115/*
1116 * TIMING_CFG_0 - DDR SDRAM Timing Configuration 0
Scott Woodd87c57b2007-04-16 14:31:55 -05001117 */
1118#define TIMING_CFG0_RWT 0xC0000000
1119#define TIMING_CFG0_RWT_SHIFT 30
1120#define TIMING_CFG0_WRT 0x30000000
1121#define TIMING_CFG0_WRT_SHIFT 28
1122#define TIMING_CFG0_RRT 0x0C000000
1123#define TIMING_CFG0_RRT_SHIFT 26
1124#define TIMING_CFG0_WWT 0x03000000
1125#define TIMING_CFG0_WWT_SHIFT 24
1126#define TIMING_CFG0_ACT_PD_EXIT 0x00700000
1127#define TIMING_CFG0_ACT_PD_EXIT_SHIFT 20
1128#define TIMING_CFG0_PRE_PD_EXIT 0x00070000
1129#define TIMING_CFG0_PRE_PD_EXIT_SHIFT 16
1130#define TIMING_CFG0_ODT_PD_EXIT 0x00000F00
1131#define TIMING_CFG0_ODT_PD_EXIT_SHIFT 8
Anton Vorontsovd892b2d2008-03-24 20:46:57 +03001132#define TIMING_CFG0_MRS_CYC 0x0000000F
Scott Woodd87c57b2007-04-16 14:31:55 -05001133#define TIMING_CFG0_MRS_CYC_SHIFT 0
1134
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001135/*
1136 * TIMING_CFG_1 - DDR SDRAM Timing Configuration 1
Dave Liue0803132006-12-07 21:11:58 +08001137 */
1138#define TIMING_CFG1_PRETOACT 0x70000000
1139#define TIMING_CFG1_PRETOACT_SHIFT 28
1140#define TIMING_CFG1_ACTTOPRE 0x0F000000
1141#define TIMING_CFG1_ACTTOPRE_SHIFT 24
1142#define TIMING_CFG1_ACTTORW 0x00700000
1143#define TIMING_CFG1_ACTTORW_SHIFT 20
1144#define TIMING_CFG1_CASLAT 0x00070000
1145#define TIMING_CFG1_CASLAT_SHIFT 16
1146#define TIMING_CFG1_REFREC 0x0000F000
1147#define TIMING_CFG1_REFREC_SHIFT 12
1148#define TIMING_CFG1_WRREC 0x00000700
1149#define TIMING_CFG1_WRREC_SHIFT 8
1150#define TIMING_CFG1_ACTTOACT 0x00000070
1151#define TIMING_CFG1_ACTTOACT_SHIFT 4
1152#define TIMING_CFG1_WRTORD 0x00000007
1153#define TIMING_CFG1_WRTORD_SHIFT 0
1154#define TIMING_CFG1_CASLAT_20 0x00030000 /* CAS latency = 2.0 */
1155#define TIMING_CFG1_CASLAT_25 0x00040000 /* CAS latency = 2.5 */
Heiko Schocherfacdad52008-11-19 10:10:30 +01001156#define TIMING_CFG1_CASLAT_30 0x00050000 /* CAS latency = 3.0 */
1157#define TIMING_CFG1_CASLAT_35 0x00060000 /* CAS latency = 3.5 */
1158#define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */
Heiko Schocher2b68b232009-02-11 19:26:15 +01001159#define TIMING_CFG1_CASLAT_45 0x00080000 /* CAS latency = 4.5 */
1160#define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */
Dave Liue0803132006-12-07 21:11:58 +08001161
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001162/*
1163 * TIMING_CFG_2 - DDR SDRAM Timing Configuration 2
Dave Liue0803132006-12-07 21:11:58 +08001164 */
Xie Xiaobo8d172c02007-02-14 18:26:44 +08001165#define TIMING_CFG2_CPO 0x0F800000
1166#define TIMING_CFG2_CPO_SHIFT 23
Dave Liue0803132006-12-07 21:11:58 +08001167#define TIMING_CFG2_ACSM 0x00080000
1168#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
1169#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001170/* default (= CASLAT + 1) */
1171#define TIMING_CFG2_CPO_DEF 0x00000000
Dave Liue0803132006-12-07 21:11:58 +08001172
Scott Woodd87c57b2007-04-16 14:31:55 -05001173#define TIMING_CFG2_ADD_LAT 0x70000000
1174#define TIMING_CFG2_ADD_LAT_SHIFT 28
1175#define TIMING_CFG2_WR_LAT_DELAY 0x00380000
1176#define TIMING_CFG2_WR_LAT_DELAY_SHIFT 19
1177#define TIMING_CFG2_RD_TO_PRE 0x0000E000
1178#define TIMING_CFG2_RD_TO_PRE_SHIFT 13
1179#define TIMING_CFG2_CKE_PLS 0x000001C0
1180#define TIMING_CFG2_CKE_PLS_SHIFT 6
1181#define TIMING_CFG2_FOUR_ACT 0x0000003F
1182#define TIMING_CFG2_FOUR_ACT_SHIFT 0
1183
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001184/*
Heiko Schocherf1ccd102011-09-26 13:36:54 +02001185 * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3
1186 */
1187#define TIMING_CFG3_EXT_REFREC 0x00070000
1188#define TIMING_CFG3_EXT_REFREC_SHIFT 16
1189
1190/*
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001191 * DDR_SDRAM_CFG - DDR SDRAM Control Configuration
Dave Liue0803132006-12-07 21:11:58 +08001192 */
1193#define SDRAM_CFG_MEM_EN 0x80000000
1194#define SDRAM_CFG_SREN 0x40000000
1195#define SDRAM_CFG_ECC_EN 0x20000000
1196#define SDRAM_CFG_RD_EN 0x10000000
Kim Phillipsbbea46f2007-08-16 22:52:48 -05001197#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000
1198#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000
1199#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
Dave Liue0803132006-12-07 21:11:58 +08001200#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
1201#define SDRAM_CFG_DYN_PWR 0x00200000
Mario Six9403fc42019-01-21 09:17:25 +01001202#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
Joe Hershberger2fef4022011-10-11 23:57:29 -05001203#define SDRAM_CFG_DBW_MASK 0x00180000
1204#define SDRAM_CFG_DBW_16 0x00100000
1205#define SDRAM_CFG_DBW_32 0x00080000
1206#else
Dave Liue0803132006-12-07 21:11:58 +08001207#define SDRAM_CFG_32_BE 0x00080000
Joe Hershberger2fef4022011-10-11 23:57:29 -05001208#endif
Mario Six4bc97a32019-01-21 09:17:24 +01001209#if !defined(CONFIG_ARCH_MPC8308)
Dave Liue0803132006-12-07 21:11:58 +08001210#define SDRAM_CFG_8_BE 0x00040000
Joe Hershberger2fef4022011-10-11 23:57:29 -05001211#endif
Dave Liue0803132006-12-07 21:11:58 +08001212#define SDRAM_CFG_NCAP 0x00020000
1213#define SDRAM_CFG_2T_EN 0x00008000
Andre Schwarza7b81262011-04-14 14:53:37 +02001214#define SDRAM_CFG_HSE 0x00000008
Scott Woodd87c57b2007-04-16 14:31:55 -05001215#define SDRAM_CFG_BI 0x00000001
Dave Liue0803132006-12-07 21:11:58 +08001216
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001217/*
1218 * DDR_SDRAM_MODE - DDR SDRAM Mode Register
Dave Liue0803132006-12-07 21:11:58 +08001219 */
1220#define SDRAM_MODE_ESD 0xFFFF0000
1221#define SDRAM_MODE_ESD_SHIFT 16
1222#define SDRAM_MODE_SD 0x0000FFFF
1223#define SDRAM_MODE_SD_SHIFT 0
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001224/* select extended mode reg */
1225#define DDR_MODE_EXT_MODEREG 0x4000
1226/* operating mode, mask */
1227#define DDR_MODE_EXT_OPMODE 0x3FF8
Dave Liue0803132006-12-07 21:11:58 +08001228#define DDR_MODE_EXT_OP_NORMAL 0x0000 /* normal operation */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001229/* QFC / compatibility, mask */
1230#define DDR_MODE_QFC 0x0004
1231/* compatible to older SDRAMs */
1232#define DDR_MODE_QFC_COMP 0x0000
1233/* weak drivers */
1234#define DDR_MODE_WEAK 0x0002
1235/* disable DLL */
1236#define DDR_MODE_DLL_DIS 0x0001
1237/* CAS latency, mask */
1238#define DDR_MODE_CASLAT 0x0070
Dave Liue0803132006-12-07 21:11:58 +08001239#define DDR_MODE_CASLAT_15 0x0010 /* CAS latency 1.5 */
1240#define DDR_MODE_CASLAT_20 0x0020 /* CAS latency 2 */
1241#define DDR_MODE_CASLAT_25 0x0060 /* CAS latency 2.5 */
1242#define DDR_MODE_CASLAT_30 0x0030 /* CAS latency 3 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001243/* sequential burst */
1244#define DDR_MODE_BTYPE_SEQ 0x0000
1245/* interleaved burst */
1246#define DDR_MODE_BTYPE_ILVD 0x0008
Dave Liue0803132006-12-07 21:11:58 +08001247#define DDR_MODE_BLEN_2 0x0001 /* burst length 2 */
1248#define DDR_MODE_BLEN_4 0x0002 /* burst length 4 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001249/* exact value for 7.8125us */
1250#define DDR_REFINT_166MHZ_7US 1302
1251/* use 256 cycles as a starting point */
1252#define DDR_BSTOPRE 256
1253/* select mode register */
1254#define DDR_MODE_MODEREG 0x0000
Dave Liue0803132006-12-07 21:11:58 +08001255
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001256/*
1257 * DDR_SDRAM_INTERVAL - DDR SDRAM Interval Register
Dave Liue0803132006-12-07 21:11:58 +08001258 */
1259#define SDRAM_INTERVAL_REFINT 0x3FFF0000
1260#define SDRAM_INTERVAL_REFINT_SHIFT 16
Dave Liue0803132006-12-07 21:11:58 +08001261#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
1262
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001263/*
1264 * DDR_SDRAM_CLK_CNTL - DDR SDRAM Clock Control Register
Dave Liue0803132006-12-07 21:11:58 +08001265 */
1266#define DDR_SDRAM_CLK_CNTL_SS_EN 0x80000000
1267#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025 0x01000000
1268#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 0x02000000
1269#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 0x03000000
1270#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1 0x04000000
1271
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001272/*
1273 * ECC_ERR_INJECT - Memory data path error injection mask ECC
Dave Liue0803132006-12-07 21:11:58 +08001274 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001275/* ECC Mirror Byte */
1276#define ECC_ERR_INJECT_EMB (0x80000000 >> 22)
1277/* Error Injection Enable */
1278#define ECC_ERR_INJECT_EIEN (0x80000000 >> 23)
1279/* ECC Erroe Injection Enable */
1280#define ECC_ERR_INJECT_EEIM (0xff000000 >> 24)
Dave Liue0803132006-12-07 21:11:58 +08001281#define ECC_ERR_INJECT_EEIM_SHIFT 0
1282
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001283/*
1284 * CAPTURE_ECC - Memory data path read capture ECC
Dave Liue0803132006-12-07 21:11:58 +08001285 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001286#define CAPTURE_ECC_ECE (0xff000000 >> 24)
Dave Liue0803132006-12-07 21:11:58 +08001287#define CAPTURE_ECC_ECE_SHIFT 0
1288
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001289/*
1290 * ERR_DETECT - Memory error detect
Dave Liue0803132006-12-07 21:11:58 +08001291 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001292/* Multiple Memory Errors */
1293#define ECC_ERROR_DETECT_MME (0x80000000 >> 0)
1294/* Multiple-Bit Error */
1295#define ECC_ERROR_DETECT_MBE (0x80000000 >> 28)
1296/* Single-Bit ECC Error Pickup */
1297#define ECC_ERROR_DETECT_SBE (0x80000000 >> 29)
1298/* Memory Select Error */
1299#define ECC_ERROR_DETECT_MSE (0x80000000 >> 31)
Dave Liue0803132006-12-07 21:11:58 +08001300
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001301/*
1302 * ERR_DISABLE - Memory error disable
Dave Liue0803132006-12-07 21:11:58 +08001303 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001304/* Multiple-Bit ECC Error Disable */
1305#define ECC_ERROR_DISABLE_MBED (0x80000000 >> 28)
1306/* Sinle-Bit ECC Error disable */
1307#define ECC_ERROR_DISABLE_SBED (0x80000000 >> 29)
1308/* Memory Select Error Disable */
1309#define ECC_ERROR_DISABLE_MSED (0x80000000 >> 31)
1310#define ECC_ERROR_ENABLE (~(ECC_ERROR_DISABLE_MSED | \
1311 ECC_ERROR_DISABLE_SBED | \
1312 ECC_ERROR_DISABLE_MBED))
1313
1314/*
1315 * ERR_INT_EN - Memory error interrupt enable
Dave Liue0803132006-12-07 21:11:58 +08001316 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001317/* Multiple-Bit ECC Error Interrupt Enable */
1318#define ECC_ERR_INT_EN_MBEE (0x80000000 >> 28)
1319/* Single-Bit ECC Error Interrupt Enable */
1320#define ECC_ERR_INT_EN_SBEE (0x80000000 >> 29)
1321/* Memory Select Error Interrupt Enable */
1322#define ECC_ERR_INT_EN_MSEE (0x80000000 >> 31)
1323#define ECC_ERR_INT_DISABLE (~(ECC_ERR_INT_EN_MBEE | \
1324 ECC_ERR_INT_EN_SBEE | \
1325 ECC_ERR_INT_EN_MSEE))
1326
1327/*
1328 * CAPTURE_ATTRIBUTES - Memory error attributes capture
Dave Liue0803132006-12-07 21:11:58 +08001329 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001330/* Data Beat Num */
1331#define ECC_CAPT_ATTR_BNUM (0xe0000000 >> 1)
Dave Liue0803132006-12-07 21:11:58 +08001332#define ECC_CAPT_ATTR_BNUM_SHIFT 28
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001333/* Transaction Size */
1334#define ECC_CAPT_ATTR_TSIZ (0xc0000000 >> 6)
Dave Liue0803132006-12-07 21:11:58 +08001335#define ECC_CAPT_ATTR_TSIZ_FOUR_DW 0
1336#define ECC_CAPT_ATTR_TSIZ_ONE_DW 1
1337#define ECC_CAPT_ATTR_TSIZ_TWO_DW 2
1338#define ECC_CAPT_ATTR_TSIZ_THREE_DW 3
1339#define ECC_CAPT_ATTR_TSIZ_SHIFT 24
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001340/* Transaction Source */
1341#define ECC_CAPT_ATTR_TSRC (0xf8000000 >> 11)
Dave Liue0803132006-12-07 21:11:58 +08001342#define ECC_CAPT_ATTR_TSRC_E300_CORE_DT 0x0
1343#define ECC_CAPT_ATTR_TSRC_E300_CORE_IF 0x2
1344#define ECC_CAPT_ATTR_TSRC_TSEC1 0x4
1345#define ECC_CAPT_ATTR_TSRC_TSEC2 0x5
1346#define ECC_CAPT_ATTR_TSRC_USB (0x06|0x07)
1347#define ECC_CAPT_ATTR_TSRC_ENCRYPT 0x8
1348#define ECC_CAPT_ATTR_TSRC_I2C 0x9
1349#define ECC_CAPT_ATTR_TSRC_JTAG 0xA
1350#define ECC_CAPT_ATTR_TSRC_PCI1 0xD
1351#define ECC_CAPT_ATTR_TSRC_PCI2 0xE
1352#define ECC_CAPT_ATTR_TSRC_DMA 0xF
1353#define ECC_CAPT_ATTR_TSRC_SHIFT 16
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001354/* Transaction Type */
1355#define ECC_CAPT_ATTR_TTYP (0xe0000000 >> 18)
Dave Liue0803132006-12-07 21:11:58 +08001356#define ECC_CAPT_ATTR_TTYP_WRITE 0x1
1357#define ECC_CAPT_ATTR_TTYP_READ 0x2
1358#define ECC_CAPT_ATTR_TTYP_R_M_W 0x3
1359#define ECC_CAPT_ATTR_TTYP_SHIFT 12
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001360#define ECC_CAPT_ATTR_VLD (0x80000000 >> 31) /* Valid */
Dave Liue0803132006-12-07 21:11:58 +08001361
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001362/*
1363 * ERR_SBE - Single bit ECC memory error management
Dave Liue0803132006-12-07 21:11:58 +08001364 */
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001365/* Single-Bit Error Threshold 0..255 */
1366#define ECC_ERROR_MAN_SBET (0xff000000 >> 8)
Dave Liue0803132006-12-07 21:11:58 +08001367#define ECC_ERROR_MAN_SBET_SHIFT 16
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001368/* Single Bit Error Counter 0..255 */
1369#define ECC_ERROR_MAN_SBEC (0xff000000 >> 24)
Dave Liue0803132006-12-07 21:11:58 +08001370#define ECC_ERROR_MAN_SBEC_SHIFT 0
1371
Mario Sixe4061552018-08-06 10:23:30 +02001372#endif /* !CONFIG_MPC83XX_SDRAM */
1373
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001374/*
Tom Rini0c1b10f2021-08-19 15:15:06 -04001375 * PCI_CONFIG_ADDRESS - PCI Config Address Register
Dave Liue0803132006-12-07 21:11:58 +08001376 */
1377#define PCI_CONFIG_ADDRESS_EN 0x80000000
1378#define PCI_CONFIG_ADDRESS_BN_SHIFT 16
1379#define PCI_CONFIG_ADDRESS_BN_MASK 0x00ff0000
1380#define PCI_CONFIG_ADDRESS_DN_SHIFT 11
1381#define PCI_CONFIG_ADDRESS_DN_MASK 0x0000f800
1382#define PCI_CONFIG_ADDRESS_FN_SHIFT 8
1383#define PCI_CONFIG_ADDRESS_FN_MASK 0x00000700
1384#define PCI_CONFIG_ADDRESS_RN_SHIFT 0
1385#define PCI_CONFIG_ADDRESS_RN_MASK 0x000000fc
Dave Liu5f820432006-11-03 19:33:44 -06001386
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001387/*
1388 * POTAR - PCI Outbound Translation Address Register
Dave Liue0803132006-12-07 21:11:58 +08001389 */
1390#define POTAR_TA_MASK 0x000fffff
1391
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001392/*
1393 * POBAR - PCI Outbound Base Address Register
Dave Liue0803132006-12-07 21:11:58 +08001394 */
1395#define POBAR_BA_MASK 0x000fffff
1396
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001397/*
1398 * POCMR - PCI Outbound Comparision Mask Register
Dave Liue0803132006-12-07 21:11:58 +08001399 */
1400#define POCMR_EN 0x80000000
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001401/* 0-memory space 1-I/O space */
1402#define POCMR_IO 0x40000000
Dave Liue0803132006-12-07 21:11:58 +08001403#define POCMR_SE 0x20000000 /* streaming enable */
1404#define POCMR_DST 0x10000000 /* 0-PCI1 1-PCI2 */
1405#define POCMR_CM_MASK 0x000fffff
1406#define POCMR_CM_4G 0x00000000
1407#define POCMR_CM_2G 0x00080000
1408#define POCMR_CM_1G 0x000C0000
1409#define POCMR_CM_512M 0x000E0000
1410#define POCMR_CM_256M 0x000F0000
1411#define POCMR_CM_128M 0x000F8000
1412#define POCMR_CM_64M 0x000FC000
1413#define POCMR_CM_32M 0x000FE000
1414#define POCMR_CM_16M 0x000FF000
1415#define POCMR_CM_8M 0x000FF800
1416#define POCMR_CM_4M 0x000FFC00
1417#define POCMR_CM_2M 0x000FFE00
1418#define POCMR_CM_1M 0x000FFF00
1419#define POCMR_CM_512K 0x000FFF80
1420#define POCMR_CM_256K 0x000FFFC0
1421#define POCMR_CM_128K 0x000FFFE0
1422#define POCMR_CM_64K 0x000FFFF0
1423#define POCMR_CM_32K 0x000FFFF8
1424#define POCMR_CM_16K 0x000FFFFC
1425#define POCMR_CM_8K 0x000FFFFE
1426#define POCMR_CM_4K 0x000FFFFF
1427
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001428/*
1429 * PITAR - PCI Inbound Translation Address Register
Dave Liue0803132006-12-07 21:11:58 +08001430 */
1431#define PITAR_TA_MASK 0x000fffff
1432
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001433/*
1434 * PIBAR - PCI Inbound Base/Extended Address Register
Dave Liue0803132006-12-07 21:11:58 +08001435 */
1436#define PIBAR_MASK 0xffffffff
1437#define PIEBAR_EBA_MASK 0x000fffff
1438
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001439/*
1440 * PIWAR - PCI Inbound Windows Attributes Register
Dave Liue0803132006-12-07 21:11:58 +08001441 */
1442#define PIWAR_EN 0x80000000
1443#define PIWAR_PF 0x20000000
1444#define PIWAR_RTT_MASK 0x000f0000
1445#define PIWAR_RTT_NO_SNOOP 0x00040000
1446#define PIWAR_RTT_SNOOP 0x00050000
1447#define PIWAR_WTT_MASK 0x0000f000
1448#define PIWAR_WTT_NO_SNOOP 0x00004000
1449#define PIWAR_WTT_SNOOP 0x00005000
1450#define PIWAR_IWS_MASK 0x0000003F
1451#define PIWAR_IWS_4K 0x0000000B
1452#define PIWAR_IWS_8K 0x0000000C
1453#define PIWAR_IWS_16K 0x0000000D
1454#define PIWAR_IWS_32K 0x0000000E
1455#define PIWAR_IWS_64K 0x0000000F
1456#define PIWAR_IWS_128K 0x00000010
1457#define PIWAR_IWS_256K 0x00000011
1458#define PIWAR_IWS_512K 0x00000012
1459#define PIWAR_IWS_1M 0x00000013
1460#define PIWAR_IWS_2M 0x00000014
1461#define PIWAR_IWS_4M 0x00000015
1462#define PIWAR_IWS_8M 0x00000016
1463#define PIWAR_IWS_16M 0x00000017
1464#define PIWAR_IWS_32M 0x00000018
1465#define PIWAR_IWS_64M 0x00000019
1466#define PIWAR_IWS_128M 0x0000001A
1467#define PIWAR_IWS_256M 0x0000001B
1468#define PIWAR_IWS_512M 0x0000001C
1469#define PIWAR_IWS_1G 0x0000001D
1470#define PIWAR_IWS_2G 0x0000001E
Dave Liuf6eda7f2006-10-25 14:41:21 -05001471
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001472/*
1473 * PMCCR1 - PCI Configuration Register 1
Scott Woodd87c57b2007-04-16 14:31:55 -05001474 */
1475#define PMCCR1_POWER_OFF 0x00000020
1476
Mario Sixe4061552018-08-06 10:23:30 +02001477#ifndef CONFIG_RAM
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001478/*
1479 * DDRCDR - DDR Control Driver Register
Scott Woodd87c57b2007-04-16 14:31:55 -05001480 */
Kim Phillips9e896472008-01-16 12:06:16 -06001481#define DDRCDR_DHC_EN 0x80000000
Scott Woodd87c57b2007-04-16 14:31:55 -05001482#define DDRCDR_EN 0x40000000
1483#define DDRCDR_PZ 0x3C000000
1484#define DDRCDR_PZ_MAXZ 0x00000000
1485#define DDRCDR_PZ_HIZ 0x20000000
1486#define DDRCDR_PZ_NOMZ 0x30000000
1487#define DDRCDR_PZ_LOZ 0x38000000
1488#define DDRCDR_PZ_MINZ 0x3C000000
1489#define DDRCDR_NZ 0x3C000000
1490#define DDRCDR_NZ_MAXZ 0x00000000
1491#define DDRCDR_NZ_HIZ 0x02000000
1492#define DDRCDR_NZ_NOMZ 0x03000000
1493#define DDRCDR_NZ_LOZ 0x03800000
1494#define DDRCDR_NZ_MINZ 0x03C00000
1495#define DDRCDR_ODT 0x00080000
1496#define DDRCDR_DDR_CFG 0x00040000
1497#define DDRCDR_M_ODR 0x00000002
1498#define DDRCDR_Q_DRN 0x00000001
Mario Sixe4061552018-08-06 10:23:30 +02001499#endif /* !CONFIG_RAM */
Scott Woodd87c57b2007-04-16 14:31:55 -05001500
Heiko Schocher4e8b7502011-09-26 13:36:53 +02001501/*
1502 * PCIE Bridge Register
1503 */
Anton Vorontsovfd6646c2009-01-08 04:26:12 +03001504#define PEX_CSB_CTRL_OBPIOE 0x00000001
1505#define PEX_CSB_CTRL_IBPIOE 0x00000002
1506#define PEX_CSB_CTRL_WDMAE 0x00000004
1507#define PEX_CSB_CTRL_RDMAE 0x00000008
1508
1509#define PEX_CSB_OBCTRL_PIOE 0x00000001
1510#define PEX_CSB_OBCTRL_MEMWE 0x00000002
1511#define PEX_CSB_OBCTRL_IOWE 0x00000004
1512#define PEX_CSB_OBCTRL_CFGWE 0x00000008
1513
1514#define PEX_CSB_IBCTRL_PIOE 0x00000001
1515
1516#define PEX_OWAR_EN 0x00000001
1517#define PEX_OWAR_TYPE_CFG 0x00000000
1518#define PEX_OWAR_TYPE_IO 0x00000002
1519#define PEX_OWAR_TYPE_MEM 0x00000004
1520#define PEX_OWAR_RLXO 0x00000008
1521#define PEX_OWAR_NANP 0x00000010
1522#define PEX_OWAR_SIZE 0xFFFFF000
1523
1524#define PEX_IWAR_EN 0x00000001
1525#define PEX_IWAR_TYPE_INT 0x00000000
1526#define PEX_IWAR_TYPE_PF 0x00000004
1527#define PEX_IWAR_TYPE_NO_PF 0x00000006
1528#define PEX_IWAR_NSOV 0x00000008
1529#define PEX_IWAR_NSNP 0x00000010
1530#define PEX_IWAR_SIZE 0xFFFFF000
1531#define PEX_IWAR_SIZE_1M 0x000FF000
1532#define PEX_IWAR_SIZE_2M 0x001FF000
1533#define PEX_IWAR_SIZE_4M 0x003FF000
1534#define PEX_IWAR_SIZE_8M 0x007FF000
1535#define PEX_IWAR_SIZE_16M 0x00FFF000
1536#define PEX_IWAR_SIZE_32M 0x01FFF000
1537#define PEX_IWAR_SIZE_64M 0x03FFF000
1538#define PEX_IWAR_SIZE_128M 0x07FFF000
1539#define PEX_IWAR_SIZE_256M 0x0FFFF000
1540
1541#define PEX_GCLK_RATIO 0x440
1542
Scott Wood49ea3b62007-04-16 14:34:21 -05001543#ifndef __ASSEMBLY__
1544struct pci_region;
Peter Tyser6aa3d3b2010-09-14 19:13:50 -05001545void mpc83xx_pci_init(int num_buses, struct pci_region **reg);
Ira Snyder75f35202009-01-12 13:32:26 -08001546void mpc83xx_pcislave_unlock(int bus);
Peter Tyser6aa3d3b2010-09-14 19:13:50 -05001547void mpc83xx_pcie_init(int num_buses, struct pci_region **reg);
Scott Wood49ea3b62007-04-16 14:34:21 -05001548#endif
1549
Eran Libertyf046ccd2005-07-28 10:08:46 -05001550#endif /* __MPC83XX_H__ */