blob: 9eac7de0dcbd0d014cb1109f018ca4bc9e6b6f96 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simek38716182014-02-05 08:06:29 +01002/*
3 * Copyright (c) 2004-2008 Texas Instruments
4 *
5 * (C) Copyright 2002
6 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
Michal Simek38716182014-02-05 08:06:29 +01007 */
8
9OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
10OUTPUT_ARCH(arm)
11ENTRY(_start)
12SECTIONS
13{
14 . = 0x00000000;
15
16 . = ALIGN(4);
17 .text :
18 {
19 *(.__image_copy_start)
Masahiro Yamadaa811db52014-06-05 19:47:45 +090020 *(.vectors)
Michal Simek38716182014-02-05 08:06:29 +010021 CPUDIR/start.o (.text*)
Alexander Graf7e21fbc2018-06-12 07:48:37 +020022 }
23
24 /* This needs to come before *(.text*) */
Ilias Apalodimasc0802102024-03-15 08:43:49 +020025 .efi_runtime ALIGN(4) : {
26 __efi_runtime_start = .;
Alexander Graf7e21fbc2018-06-12 07:48:37 +020027 *(.text.efi_runtime*)
28 *(.rodata.efi_runtime*)
29 *(.data.efi_runtime*)
Ilias Apalodimasc0802102024-03-15 08:43:49 +020030 __efi_runtime_stop = .;
Alexander Graf7e21fbc2018-06-12 07:48:37 +020031 }
32
33 .text_rest :
34 {
Michal Simek38716182014-02-05 08:06:29 +010035 *(.text*)
36 }
37
38 . = ALIGN(4);
39 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
40
41 . = ALIGN(4);
42 .data : {
43 *(.data*)
44 }
45
46 . = ALIGN(4);
47
48 . = .;
49
50 . = ALIGN(4);
Andrew Scull99e2fbc2022-05-30 10:00:04 +000051 __u_boot_list : {
52 KEEP(*(SORT(__u_boot_list*)));
Michal Simek38716182014-02-05 08:06:29 +010053 }
54
Ilias Apalodimas6b7f91c2024-03-15 08:43:47 +020055 .efi_runtime_rel ALIGN(4) : {
56 __efi_runtime_rel_start = .;
Alexander Graf7e21fbc2018-06-12 07:48:37 +020057 *(.rel*.efi_runtime)
58 *(.rel*.efi_runtime.*)
Ilias Apalodimas6b7f91c2024-03-15 08:43:47 +020059 __efi_runtime_rel_stop = .;
Alexander Graff5e46b42017-07-03 13:41:34 +020060 }
61
Michal Simekbe3a73c2022-08-31 11:28:59 +020062 . = ALIGN(8);
Michal Simek38716182014-02-05 08:06:29 +010063 .image_copy_end :
64 {
65 *(.__image_copy_end)
66 }
67
Ilias Apalodimas742752a2024-03-15 08:43:48 +020068 .rel.dyn ALIGN(8) : {
69 __rel_dyn_start = .;
Michal Simek38716182014-02-05 08:06:29 +010070 *(.rel*)
Ilias Apalodimas742752a2024-03-15 08:43:48 +020071 __rel_dyn_end = .;
Michal Simek38716182014-02-05 08:06:29 +010072 }
73
Albert ARIBAUDd0b5d9d2014-02-22 17:53:42 +010074 .end :
75 {
76 *(.__end)
77 }
78
79 _image_binary_end = .;
Michal Simek38716182014-02-05 08:06:29 +010080
81/*
Ilias Apalodimasfaf396a2024-03-15 08:43:46 +020082 * These sections occupy the same memory, but their lifetimes do
83 * not overlap: U-Boot initializes .bss only after applying dynamic
84 * relocations and therefore after it doesn't need .rel.dyn any more.
Michal Simek38716182014-02-05 08:06:29 +010085 */
Ilias Apalodimasfaf396a2024-03-15 08:43:46 +020086 .bss ADDR(.rel.dyn) (OVERLAY): {
87 __bss_start = .;
Michal Simek38716182014-02-05 08:06:29 +010088 *(.bss*)
Ilias Apalodimasfaf396a2024-03-15 08:43:46 +020089 . = ALIGN(8);
90 __bss_end = .;
Michal Simek38716182014-02-05 08:06:29 +010091 }
92
93 /*
Albert ARIBAUD41623c92014-04-15 16:13:51 +020094 * Zynq needs to discard these sections because the user
Michal Simek38716182014-02-05 08:06:29 +010095 * is expected to pass this image on to tools for boot.bin
96 * generation that require them to be dropped.
97 */
98 /DISCARD/ : { *(.dynsym) }
99 /DISCARD/ : { *(.dynbss*) }
100 /DISCARD/ : { *(.dynstr*) }
101 /DISCARD/ : { *(.dynamic*) }
102 /DISCARD/ : { *(.plt*) }
103 /DISCARD/ : { *(.interp*) }
104 /DISCARD/ : { *(.gnu*) }
105 /DISCARD/ : { *(.ARM.exidx*) }
106 /DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
107}