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Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +02001/*
2 * Copyright (C) 2014 Samsung Electronics
3 * Przemyslaw Marczak <p.marczak@samsung.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/arch/pinmux.h>
10#include <asm/arch/power.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/gpio.h>
13#include <asm/gpio.h>
14#include <asm/arch/cpu.h>
Przemyslaw Marczakca2b9332015-05-13 13:38:25 +020015#include <dm.h>
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +020016#include <power/pmic.h>
Przemyslaw Marczakca2b9332015-05-13 13:38:25 +020017#include <power/regulator.h>
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +020018#include <power/max77686_pmic.h>
19#include <errno.h>
Inha Song2474b7f2015-02-17 12:24:12 +010020#include <mmc.h>
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +020021#include <usb.h>
22#include <usb/s3c_udc.h>
23#include <samsung/misc.h>
24#include "setup.h"
25
26DECLARE_GLOBAL_DATA_PTR;
27
28#ifdef CONFIG_BOARD_TYPES
29/* Odroid board types */
30enum {
31 ODROID_TYPE_U3,
32 ODROID_TYPE_X2,
33 ODROID_TYPES,
34};
35
36void set_board_type(void)
37{
38 /* Set GPA1 pin 1 to HI - enable XCL205 output */
39 writel(XCL205_EN_GPIO_CON_CFG, XCL205_EN_GPIO_CON);
40 writel(XCL205_EN_GPIO_DAT_CFG, XCL205_EN_GPIO_CON + 0x4);
41 writel(XCL205_EN_GPIO_PUD_CFG, XCL205_EN_GPIO_CON + 0x8);
42 writel(XCL205_EN_GPIO_DRV_CFG, XCL205_EN_GPIO_CON + 0xc);
43
44 /* Set GPC1 pin 2 to IN - check XCL205 output state */
45 writel(XCL205_STATE_GPIO_CON_CFG, XCL205_STATE_GPIO_CON);
46 writel(XCL205_STATE_GPIO_PUD_CFG, XCL205_STATE_GPIO_CON + 0x8);
47
48 /* XCL205 - needs some latch time */
49 sdelay(200000);
50
51 /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
52 if (readl(XCL205_STATE_GPIO_DAT) & (1 << XCL205_STATE_GPIO_PIN))
53 gd->board_type = ODROID_TYPE_X2;
54 else
55 gd->board_type = ODROID_TYPE_U3;
56}
57
58const char *get_board_type(void)
59{
60 const char *board_type[] = {"u3", "x2"};
61
62 return board_type[gd->board_type];
63}
64#endif
65
66#ifdef CONFIG_SET_DFU_ALT_INFO
Inha Song2474b7f2015-02-17 12:24:12 +010067char *get_dfu_alt_system(char *interface, char *devstr)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +020068{
69 return getenv("dfu_alt_system");
70}
71
Inha Song2474b7f2015-02-17 12:24:12 +010072char *get_dfu_alt_boot(char *interface, char *devstr)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +020073{
Inha Song2474b7f2015-02-17 12:24:12 +010074 struct mmc *mmc;
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +020075 char *alt_boot;
Inha Song2474b7f2015-02-17 12:24:12 +010076 int dev_num;
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +020077
Inha Song2474b7f2015-02-17 12:24:12 +010078 dev_num = simple_strtoul(devstr, NULL, 10);
79
80 mmc = find_mmc_device(dev_num);
81 if (!mmc)
82 return NULL;
83
84 if (mmc_init(mmc))
85 return NULL;
86
87 alt_boot = IS_SD(mmc) ? CONFIG_DFU_ALT_BOOT_SD :
88 CONFIG_DFU_ALT_BOOT_EMMC;
89
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +020090 return alt_boot;
91}
92#endif
93
94static void board_clock_init(void)
95{
96 unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
97 struct exynos4x12_clock *clk = (struct exynos4x12_clock *)
98 samsung_get_base_clock();
99
100 /*
101 * CMU_CPU clocks src to MPLL
102 * Bit values: 0 ; 1
103 * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL
104 * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL
105 * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C
106 * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL
107 */
108 clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) |
109 MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1);
110 set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |
111 MUX_MPLL_USER_SEL_C(1);
112
113 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
114
115 /* Wait for mux change */
116 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
117 continue;
118
119 /* Set APLL to 1000MHz */
120 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1);
121 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
122
123 clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
124
125 /* Wait for PLL to be locked */
126 while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))
127 continue;
128
129 /* Set CMU_CPU clocks src to APLL */
130 set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |
131 MUX_MPLL_USER_SEL_C(1);
132 clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
133
134 /* Wait for mux change */
135 while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)
136 continue;
137
138 set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |
139 PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
140 APLL_RATIO(0) | CORE2_RATIO(0);
141 /*
142 * Set dividers for MOUTcore = 1000 MHz
143 * coreout = MOUT / (ratio + 1) = 1000 MHz (0)
144 * corem0 = armclk / (ratio + 1) = 333 MHz (2)
145 * corem1 = armclk / (ratio + 1) = 166 MHz (5)
146 * periph = armclk / (ratio + 1) = 1000 MHz (0)
147 * atbout = MOUT / (ratio + 1) = 200 MHz (4)
148 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
149 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
150 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
151 */
152 clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) |
153 PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) |
154 APLL_RATIO(7) | CORE2_RATIO(7);
155
156 clrsetbits_le32(&clk->div_cpu0, clr, set);
157
158 /* Wait for divider ready status */
159 while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)
160 continue;
161
162 /*
163 * For MOUThpm = 1000 MHz (MOUTapll)
164 * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
165 * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
Przemyslaw Marczakb2197732014-09-23 12:46:43 +0200166 * cores_out = armclk / (ratio + 1) = 200 (4)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200167 */
168 clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7);
Przemyslaw Marczakb2197732014-09-23 12:46:43 +0200169 set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4);
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200170
171 clrsetbits_le32(&clk->div_cpu1, clr, set);
172
173 /* Wait for divider ready status */
174 while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)
175 continue;
176
177 /*
178 * Set CMU_DMC clocks src to APLL
179 * Bit values: 0 ; 1
180 * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL
181 * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL
182 * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL
183 * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT
184 * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
185 * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
186 * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
187 * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1
188 */
189 clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) |
190 MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) |
191 MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) |
192 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
193 set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |
194 MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
195 MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
196
197 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
198
199 /* Wait for mux change */
200 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
201 continue;
202
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900203 /* Set MPLL to 800MHz */
204 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200205
206 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
207
208 /* Wait for PLL to be locked */
209 while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))
210 continue;
211
212 /* Switch back CMU_DMC mux */
213 set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |
214 MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
215 MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
216
217 clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
218
219 /* Wait for mux change */
220 while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)
221 continue;
222
223 /* CLK_DIV_DMC0 */
224 clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) |
225 DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7);
226 /*
227 * For:
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900228 * MOUTdmc = 800 MHz
229 * MOUTdphy = 800 MHz
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200230 *
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900231 * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
232 * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
233 * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
234 * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
235 * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
236 * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200237 */
238 set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |
239 DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
240
241 clrsetbits_le32(&clk->div_dmc0, clr, set);
242
243 /* Wait for divider ready status */
244 while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)
245 continue;
246
247 /* CLK_DIV_DMC1 */
248 clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) |
249 C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127);
250 /*
251 * For:
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900252 * MOUTg2d = 800 MHz
253 * MOUTc2c = 800 Mhz
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200254 * MOUTpwi = 108 MHz
255 *
Joonyoung Shimb00f8ed2015-01-23 17:30:07 +0900256 * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3)
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900257 * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
258 * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200259 * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
260 */
Joonyoung Shimb00f8ed2015-01-23 17:30:07 +0900261 set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) |
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200262 C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
263
264 clrsetbits_le32(&clk->div_dmc1, clr, set);
265
266 /* Wait for divider ready status */
267 while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)
268 continue;
269
270 /* CLK_SRC_PERIL0 */
271 clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) |
272 UART3_SEL(15) | UART4_SEL(15);
273 /*
274 * Set CLK_SRC_PERIL0 clocks src to MPLL
275 * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
276 * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
277 * 8(SCLK_VPLL)
278 *
279 * Set all to SCLK_MPLL_USER_T
280 */
281 set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |
282 UART4_SEL(6);
283
284 clrsetbits_le32(&clk->src_peril0, clr, set);
285
286 /* CLK_DIV_PERIL0 */
287 clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) |
288 UART3_RATIO(15) | UART4_RATIO(15);
289 /*
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900290 * For MOUTuart0-4: 800MHz
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200291 *
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900292 * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200293 */
294 set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |
295 UART3_RATIO(7) | UART4_RATIO(7);
296
297 clrsetbits_le32(&clk->div_peril0, clr, set);
298
299 while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)
300 continue;
301
302 /* CLK_DIV_FSYS1 */
303 clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) |
304 MMC1_PRE_RATIO(255);
305 /*
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900306 * For MOUTmmc0-3 = 800 MHz (MPLL)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200307 *
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900308 * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
309 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
310 * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
311 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200312 */
313 set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |
314 MMC1_PRE_RATIO(1);
315
316 clrsetbits_le32(&clk->div_fsys1, clr, set);
317
318 /* Wait for divider ready status */
319 while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)
320 continue;
321
322 /* CLK_DIV_FSYS2 */
323 clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) |
324 MMC3_PRE_RATIO(255);
325 /*
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900326 * For MOUTmmc0-3 = 800 MHz (MPLL)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200327 *
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900328 * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
329 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
330 * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
331 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200332 */
333 set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |
334 MMC3_PRE_RATIO(1);
335
336 clrsetbits_le32(&clk->div_fsys2, clr, set);
337
338 /* Wait for divider ready status */
339 while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)
340 continue;
341
342 /* CLK_DIV_FSYS3 */
343 clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255);
344 /*
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900345 * For MOUTmmc4 = 800 MHz (MPLL)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200346 *
Minkyu Kangbd99e6d2014-09-11 14:02:03 +0900347 * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
348 * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200349 */
350 set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
351
352 clrsetbits_le32(&clk->div_fsys3, clr, set);
353
354 /* Wait for divider ready status */
355 while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)
356 continue;
357
358 return;
359}
360
361static void board_gpio_init(void)
362{
363 /* eMMC Reset Pin */
Przemyslaw Marczak4aa97312014-10-28 17:31:07 +0100364 gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset");
365
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200366 gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
367 gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
368 gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
369
370 /* Enable FAN (Odroid U3) */
Przemyslaw Marczak4aa97312014-10-28 17:31:07 +0100371 gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control");
372
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200373 gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
374 gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
375 gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);
376
377 /* OTG Vbus output (Odroid U3+) */
Przemyslaw Marczak4aa97312014-10-28 17:31:07 +0100378 gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus");
379
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200380 gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE);
381 gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X);
382 gpio_direction_output(EXYNOS4X12_GPIO_L20, 0);
383
384 /* OTG INT (Odroid U3+) */
Przemyslaw Marczak4aa97312014-10-28 17:31:07 +0100385 gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT");
386
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200387 gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP);
388 gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X);
389 gpio_direction_input(EXYNOS4X12_GPIO_X31);
Suriyan Ramasamif2cca342014-11-20 17:26:30 -0800390
Suriyan Ramasamidf963372014-11-23 22:15:32 -0800391 /* Blue LED (Odroid X2/U2/U3) */
392 gpio_request(EXYNOS4X12_GPIO_C10, "Blue LED");
393
394 gpio_direction_output(EXYNOS4X12_GPIO_C10, 0);
395
Suriyan Ramasamif2cca342014-11-20 17:26:30 -0800396#ifdef CONFIG_CMD_USB
397 /* USB3503A Reference frequency */
398 gpio_request(EXYNOS4X12_GPIO_X30, "USB3503A RefFreq");
399
400 /* USB3503A Connect */
401 gpio_request(EXYNOS4X12_GPIO_X34, "USB3503A Connect");
402
403 /* USB3503A Reset */
404 gpio_request(EXYNOS4X12_GPIO_X35, "USB3503A Reset");
405#endif
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200406}
407
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200408int exynos_early_init_f(void)
409{
410 board_clock_init();
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200411
412 return 0;
413}
414
415int exynos_init(void)
416{
Przemyslaw Marczak4aa97312014-10-28 17:31:07 +0100417 board_gpio_init();
418
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200419 return 0;
420}
421
422int exynos_power_init(void)
423{
Minkyu Kang1d839702015-10-23 16:15:04 +0900424 const char *mmc_regulators[] = {
425 "VDDQ_EMMC_1.8V",
426 "VDDQ_EMMC_2.8V",
427 "TFLASH_2.8V",
428 NULL,
429 };
430
Przemyslaw Marczak3b880752015-05-13 13:38:27 +0200431 if (regulator_list_autoset(mmc_regulators, NULL, true))
Przemyslaw Marczakca2b9332015-05-13 13:38:25 +0200432 error("Unable to init all mmc regulators");
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200433
434 return 0;
435}
436
437#ifdef CONFIG_USB_GADGET
438static int s5pc210_phy_control(int on)
439{
Przemyslaw Marczakca2b9332015-05-13 13:38:25 +0200440 struct udevice *dev;
441 int ret;
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200442
Przemyslaw Marczak3b880752015-05-13 13:38:27 +0200443 ret = regulator_get_by_platname("VDD_UOTG_3.0V", &dev);
Przemyslaw Marczakca2b9332015-05-13 13:38:25 +0200444 if (ret) {
445 error("Regulator get error: %d", ret);
446 return ret;
447 }
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200448
449 if (on)
Przemyslaw Marczakca2b9332015-05-13 13:38:25 +0200450 return regulator_set_mode(dev, OPMODE_ON);
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200451 else
Przemyslaw Marczakca2b9332015-05-13 13:38:25 +0200452 return regulator_set_mode(dev, OPMODE_LPM);
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200453}
454
Marek Vasutc0982872015-12-04 02:23:29 +0100455struct dwc2_plat_otg_data s5pc210_otg_data = {
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200456 .phy_control = s5pc210_phy_control,
457 .regs_phy = EXYNOS4X12_USBPHY_BASE,
458 .regs_otg = EXYNOS4X12_USBOTG_BASE,
459 .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
460 .usb_flags = PHY0_SLEEP,
461};
Suriyan Ramasami6a23c652014-10-29 09:22:43 -0700462#endif
463
464#if defined(CONFIG_USB_GADGET) || defined(CONFIG_CMD_USB)
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200465
466int board_usb_init(int index, enum usb_init_type init)
467{
Suriyan Ramasami6a23c652014-10-29 09:22:43 -0700468#ifdef CONFIG_CMD_USB
Przemyslaw Marczakca2b9332015-05-13 13:38:25 +0200469 struct udevice *dev;
470 int ret;
Suriyan Ramasami6a23c652014-10-29 09:22:43 -0700471
472 /* Set Ref freq 0 => 24MHz, 1 => 26MHz*/
473 /* Odroid Us have it at 24MHz, Odroid Xs at 26MHz */
474 if (gd->board_type == ODROID_TYPE_U3)
475 gpio_direction_output(EXYNOS4X12_GPIO_X30, 0);
476 else
477 gpio_direction_output(EXYNOS4X12_GPIO_X30, 1);
478
479 /* Disconnect, Reset, Connect */
480 gpio_direction_output(EXYNOS4X12_GPIO_X34, 0);
481 gpio_direction_output(EXYNOS4X12_GPIO_X35, 0);
482 gpio_direction_output(EXYNOS4X12_GPIO_X35, 1);
483 gpio_direction_output(EXYNOS4X12_GPIO_X34, 1);
484
485 /* Power off and on BUCK8 for LAN9730 */
486 debug("LAN9730 - Turning power buck 8 OFF and ON.\n");
487
Przemyslaw Marczak3b880752015-05-13 13:38:27 +0200488 ret = regulator_get_by_platname("VCC_P3V3_2.85V", &dev);
Przemyslaw Marczakca2b9332015-05-13 13:38:25 +0200489 if (ret) {
490 error("Regulator get error: %d", ret);
491 return ret;
Suriyan Ramasami6a23c652014-10-29 09:22:43 -0700492 }
493
Przemyslaw Marczakca2b9332015-05-13 13:38:25 +0200494 ret = regulator_set_enable(dev, true);
495 if (ret) {
496 error("Regulator %s enable setting error: %d", dev->name, ret);
497 return ret;
498 }
Suriyan Ramasami6a23c652014-10-29 09:22:43 -0700499
Przemyslaw Marczakca2b9332015-05-13 13:38:25 +0200500 ret = regulator_set_value(dev, 750000);
501 if (ret) {
502 error("Regulator %s value setting error: %d", dev->name, ret);
503 return ret;
504 }
505
506 ret = regulator_set_value(dev, 3300000);
507 if (ret) {
508 error("Regulator %s value setting error: %d", dev->name, ret);
509 return ret;
510 }
511#endif
Przemyslaw Marczakbf3a08b2014-09-01 13:50:51 +0200512 debug("USB_udc_probe\n");
513 return s3c_udc_probe(&s5pc210_otg_data);
514}
515#endif