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Masahiro Yamada0b11dbf2015-07-26 02:46:26 +09001#
2# Multifunction miscellaneous devices
3#
4
5menu "Multifunction device drivers"
6
Thomas Chou4395e062015-10-07 20:20:51 +08007config MISC
8 bool "Enable Driver Model for Misc drivers"
9 depends on DM
10 help
11 Enable driver model for miscellaneous devices. This class is
12 used only for those do not fit other more general classes. A
13 set of generic read, write and ioctl methods may be used to
14 access the device.
15
Simon Glassaaba7032018-11-18 08:14:27 -070016config SPL_MISC
17 bool "Enable Driver Model for Misc drivers in SPL"
18 depends on SPL_DM
19 help
20 Enable driver model for miscellaneous devices. This class is
21 used only for those do not fit other more general classes. A
22 set of generic read, write and ioctl methods may be used to
23 access the device.
24
25config TPL_MISC
26 bool "Enable Driver Model for Misc drivers in TPL"
27 depends on TPL_DM
28 help
29 Enable driver model for miscellaneous devices. This class is
30 used only for those do not fit other more general classes. A
31 set of generic read, write and ioctl methods may be used to
32 access the device.
33
Thomas Chouca844dd2015-10-14 08:43:31 +080034config ALTERA_SYSID
35 bool "Altera Sysid support"
36 depends on MISC
37 help
38 Select this to enable a sysid for Altera devices. Please find
39 details on the "Embedded Peripherals IP User Guide" of Altera.
40
Marek BehĂșnaa5eb9a2017-06-09 19:28:44 +020041config ATSHA204A
42 bool "Support for Atmel ATSHA204A module"
43 depends on MISC
44 help
45 Enable support for I2C connected Atmel's ATSHA204A
46 CryptoAuthentication module found for example on the Turris Omnia
47 board.
48
Philipp Tomsich49cd8e82017-05-05 19:21:38 +020049config ROCKCHIP_EFUSE
50 bool "Rockchip e-fuse support"
51 depends on MISC
52 help
53 Enable (read-only) access for the e-fuse block found in Rockchip
54 SoCs: accesses can either be made using byte addressing and a length
55 or through child-nodes that are generated based on the e-fuse map
56 retrieved from the DTS.
57
58 This driver currently supports the RK3399 only, but can easily be
59 extended (by porting the read function from the Linux kernel sources)
60 to support other recent Rockchip devices.
61
Finley Xiaoa907dc32019-09-25 17:57:49 +020062config ROCKCHIP_OTP
63 bool "Rockchip OTP Support"
64 depends on MISC
65 help
66 Enable (read-only) access for the one-time-programmable memory block
67 found in Rockchip SoCs: accesses can either be made using byte
68 addressing and a length or through child-nodes that are generated
69 based on the e-fuse map retrieved from the DTS.
70
Liviu Dudau0fabfeb2018-09-28 13:43:31 +010071config VEXPRESS_CONFIG
72 bool "Enable support for Arm Versatile Express config bus"
73 depends on MISC
74 help
75 If you say Y here, you will get support for accessing the
76 configuration bus on the Arm Versatile Express boards via
77 a sysreg driver.
78
Simon Glass6fb9ac12015-02-13 12:20:47 -070079config CMD_CROS_EC
80 bool "Enable crosec command"
81 depends on CROS_EC
82 help
83 Enable command-line access to the Chrome OS EC (Embedded
84 Controller). This provides the 'crosec' command which has
85 a number of sub-commands for performing EC tasks such as
86 updating its flash, accessing a small saved context area
87 and talking to the I2C bus behind the EC (if there is one).
88
89config CROS_EC
90 bool "Enable Chrome OS EC"
91 help
92 Enable access to the Chrome OS EC. This is a separate
93 microcontroller typically available on a SPI bus on Chromebooks. It
94 provides access to the keyboard, some internal storage and may
95 control access to the battery and main PMIC depending on the
96 device. You can use the 'crosec' command to access it.
97
Simon Glassaaba7032018-11-18 08:14:27 -070098config SPL_CROS_EC
99 bool "Enable Chrome OS EC in SPL"
Adam Forda0746672019-08-24 13:50:34 -0500100 depends on SPL
Simon Glassaaba7032018-11-18 08:14:27 -0700101 help
102 Enable access to the Chrome OS EC in SPL. This is a separate
103 microcontroller typically available on a SPI bus on Chromebooks. It
104 provides access to the keyboard, some internal storage and may
105 control access to the battery and main PMIC depending on the
106 device. You can use the 'crosec' command to access it.
107
108config TPL_CROS_EC
109 bool "Enable Chrome OS EC in TPL"
Adam Forda0746672019-08-24 13:50:34 -0500110 depends on TPL
Simon Glassaaba7032018-11-18 08:14:27 -0700111 help
112 Enable access to the Chrome OS EC in TPL. This is a separate
113 microcontroller typically available on a SPI bus on Chromebooks. It
114 provides access to the keyboard, some internal storage and may
115 control access to the battery and main PMIC depending on the
116 device. You can use the 'crosec' command to access it.
117
Simon Glass6fb9ac12015-02-13 12:20:47 -0700118config CROS_EC_I2C
119 bool "Enable Chrome OS EC I2C driver"
120 depends on CROS_EC
121 help
122 Enable I2C access to the Chrome OS EC. This is used on older
123 ARM Chromebooks such as snow and spring before the standard bus
124 changed to SPI. The EC will accept commands across the I2C using
125 a special message protocol, and provide responses.
126
127config CROS_EC_LPC
128 bool "Enable Chrome OS EC LPC driver"
129 depends on CROS_EC
130 help
131 Enable I2C access to the Chrome OS EC. This is used on x86
132 Chromebooks such as link and falco. The keyboard is provided
133 through a legacy port interface, so on x86 machines the main
134 function of the EC is power and thermal management.
135
Simon Glassaaba7032018-11-18 08:14:27 -0700136config SPL_CROS_EC_LPC
137 bool "Enable Chrome OS EC LPC driver in SPL"
138 depends on CROS_EC
139 help
140 Enable I2C access to the Chrome OS EC. This is used on x86
141 Chromebooks such as link and falco. The keyboard is provided
142 through a legacy port interface, so on x86 machines the main
143 function of the EC is power and thermal management.
144
145config TPL_CROS_EC_LPC
146 bool "Enable Chrome OS EC LPC driver in TPL"
147 depends on CROS_EC
148 help
149 Enable I2C access to the Chrome OS EC. This is used on x86
150 Chromebooks such as link and falco. The keyboard is provided
151 through a legacy port interface, so on x86 machines the main
152 function of the EC is power and thermal management.
153
Simon Glass47cb8c62015-03-26 09:29:40 -0600154config CROS_EC_SANDBOX
155 bool "Enable Chrome OS EC sandbox driver"
156 depends on CROS_EC && SANDBOX
157 help
158 Enable a sandbox emulation of the Chrome OS EC. This supports
159 keyboard (use the -l flag to enable the LCD), verified boot context,
160 EC flash read/write/erase support and a few other things. It is
161 enough to perform a Chrome OS verified boot on sandbox.
162
Simon Glassaaba7032018-11-18 08:14:27 -0700163config SPL_CROS_EC_SANDBOX
164 bool "Enable Chrome OS EC sandbox driver in SPL"
165 depends on SPL_CROS_EC && SANDBOX
166 help
167 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
168 keyboard (use the -l flag to enable the LCD), verified boot context,
169 EC flash read/write/erase support and a few other things. It is
170 enough to perform a Chrome OS verified boot on sandbox.
171
172config TPL_CROS_EC_SANDBOX
173 bool "Enable Chrome OS EC sandbox driver in TPL"
174 depends on TPL_CROS_EC && SANDBOX
175 help
176 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
177 keyboard (use the -l flag to enable the LCD), verified boot context,
178 EC flash read/write/erase support and a few other things. It is
179 enough to perform a Chrome OS verified boot on sandbox.
180
Simon Glass6fb9ac12015-02-13 12:20:47 -0700181config CROS_EC_SPI
182 bool "Enable Chrome OS EC SPI driver"
183 depends on CROS_EC
184 help
185 Enable SPI access to the Chrome OS EC. This is used on newer
186 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
187 provides a faster and more robust interface than I2C but the bugs
188 are less interesting.
189
Simon Glass879704d2017-05-17 03:25:02 -0600190config DS4510
191 bool "Enable support for DS4510 CPU supervisor"
192 help
193 Enable support for the Maxim DS4510 CPU supervisor. It has an
194 integrated 64-byte EEPROM, four programmable non-volatile I/O pins
195 and a configurable timer for the supervisor function. The device is
196 connected over I2C.
197
Peng Fanc12e0d92015-08-26 15:41:33 +0800198config FSL_SEC_MON
gaurav ranafe783782015-02-27 09:44:22 +0530199 bool "Enable FSL SEC_MON Driver"
200 help
201 Freescale Security Monitor block is responsible for monitoring
202 system states.
203 Security Monitor can be transitioned on any security failures,
204 like software violations or hardware security violations.
Stefan Roese1cdd9412015-03-12 11:22:46 +0100205
Simon Glass79d66a62019-12-06 21:41:58 -0700206config IRQ
207 bool "Intel Interrupt controller"
208 depends on X86 || SANDBOX
209 help
210 This enables support for Intel interrupt controllers, including ITSS.
211 Some devices have extra features, such as Apollo Lake. The
212 device has its own uclass since there are several operations
213 involved.
214
Paul Burtonb5392c52018-12-16 19:25:19 -0300215config JZ4780_EFUSE
216 bool "Ingenic JZ4780 eFUSE support"
217 depends on ARCH_JZ47XX
218 help
219 This selects support for the eFUSE on Ingenic JZ4780 SoCs.
220
Peng Fan3e020f02015-08-27 14:49:05 +0800221config MXC_OCOTP
222 bool "Enable MXC OCOTP Driver"
Peng Fan994ab732019-07-22 01:24:55 +0000223 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
Marcel Ziswiler0a6f6252019-03-25 17:24:57 +0100224 default y
Peng Fan3e020f02015-08-27 14:49:05 +0800225 help
226 If you say Y here, you will get support for the One Time
227 Programmable memory pages that are stored on the some
228 Freescale i.MX processors.
229
Stefan Roese4cf9e462016-07-19 07:45:46 +0200230config NUVOTON_NCT6102D
231 bool "Enable Nuvoton NCT6102D Super I/O driver"
232 help
233 If you say Y here, you will get support for the Nuvoton
234 NCT6102D Super I/O driver. This can be used to enable or
235 disable the legacy UART, the watchdog or other devices
236 in the Nuvoton Super IO chips on X86 platforms.
237
Simon Glass5bee27a2019-12-06 21:41:55 -0700238config P2SB
239 bool "Intel Primary-to-Sideband Bus"
240 depends on X86 || SANDBOX
241 help
242 This enables support for the Intel Primary-to-Sideband bus,
243 abbreviated to P2SB. The P2SB is used to access various peripherals
244 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
245 space. The space is segmented into different channels and peripherals
246 are accessed by device-specific means within those channels. Devices
247 should be added in the device tree as subnodes of the P2SB. A
248 Peripheral Channel Register? (PCR) API is provided to access those
249 devices - see pcr_readl(), etc.
250
251config SPL_P2SB
252 bool "Intel Primary-to-Sideband Bus in SPL"
253 depends on SPL && (X86 || SANDBOX)
254 help
255 The Primary-to-Sideband bus is used to access various peripherals
256 through memory-mapped I/O in a large chunk of PCI space. The space is
257 segmented into different channels and peripherals are accessed by
258 device-specific means within those channels. Devices should be added
259 in the device tree as subnodes of the p2sb.
260
261config TPL_P2SB
262 bool "Intel Primary-to-Sideband Bus in TPL"
263 depends on TPL && (X86 || SANDBOX)
264 help
265 The Primary-to-Sideband bus is used to access various peripherals
266 through memory-mapped I/O in a large chunk of PCI space. The space is
267 segmented into different channels and peripherals are accessed by
268 device-specific means within those channels. Devices should be added
269 in the device tree as subnodes of the p2sb.
270
Simon Glass5fd6bad2016-01-21 19:43:31 -0700271config PWRSEQ
272 bool "Enable power-sequencing drivers"
273 depends on DM
274 help
275 Power-sequencing drivers provide support for controlling power for
276 devices. They are typically referenced by a phandle from another
277 device. When the device is started up, its power sequence can be
278 initiated.
279
280config SPL_PWRSEQ
281 bool "Enable power-sequencing drivers for SPL"
282 depends on PWRSEQ
283 help
284 Power-sequencing drivers provide support for controlling power for
285 devices. They are typically referenced by a phandle from another
286 device. When the device is started up, its power sequence can be
287 initiated.
288
Stefan Roese1cdd9412015-03-12 11:22:46 +0100289config PCA9551_LED
290 bool "Enable PCA9551 LED driver"
291 help
292 Enable driver for PCA9551 LED controller. This controller
293 is connected via I2C. So I2C needs to be enabled.
294
295config PCA9551_I2C_ADDR
296 hex "I2C address of PCA9551 LED controller"
297 depends on PCA9551_LED
298 default 0x60
299 help
300 The I2C address of the PCA9551 LED controller.
Simon Glassf9917452015-06-23 15:39:13 -0600301
Patrick Delaunayc3600e12018-05-17 15:24:06 +0200302config STM32MP_FUSE
303 bool "Enable STM32MP fuse wrapper providing the fuse API"
304 depends on ARCH_STM32MP && MISC
305 default y if CMD_FUSE
306 help
307 If you say Y here, you will get support for the fuse API (OTP)
308 for STM32MP architecture.
309 This API is needed for CMD_FUSE.
310
Christophe Kerello4e280b92017-09-13 18:00:08 +0200311config STM32_RCC
312 bool "Enable RCC driver for the STM32 SoC's family"
Patrick Delaunayd090cba2018-07-09 15:17:20 +0200313 depends on (STM32 || ARCH_STM32MP) && MISC
Christophe Kerello4e280b92017-09-13 18:00:08 +0200314 help
315 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
316 block) is responsible of the management of the clock and reset
317 generation.
318 This driver is similar to an MFD driver in the Linux kernel.
319
Stephen Warrenbd3ee842016-09-13 10:45:57 -0600320config TEGRA_CAR
321 bool "Enable support for the Tegra CAR driver"
322 depends on TEGRA_NO_BPMP
323 help
324 The Tegra CAR (Clock and Reset Controller) is a HW module that
325 controls almost all clocks and resets in a Tegra SoC.
326
Stephen Warren73dd5c42016-08-08 09:41:34 -0600327config TEGRA186_BPMP
328 bool "Enable support for the Tegra186 BPMP driver"
329 depends on TEGRA186
330 help
331 The Tegra BPMP (Boot and Power Management Processor) is a separate
332 auxiliary CPU embedded into Tegra to perform power management work,
333 and controls related features such as clocks, resets, power domains,
334 PMIC I2C bus, etc. This driver provides the core low-level
335 communication path by which feature-specific drivers (such as clock)
336 can make requests to the BPMP. This driver is similar to an MFD
337 driver in the Linux kernel.
338
Adam Fordcc3fedb2018-08-06 14:26:50 -0500339config TWL4030_LED
340 bool "Enable TWL4030 LED controller"
341 help
342 Enable this to add support for the TWL4030 LED controller.
343
Stefan Roese85056932016-01-19 14:05:10 +0100344config WINBOND_W83627
345 bool "Enable Winbond Super I/O driver"
346 help
347 If you say Y here, you will get support for the Winbond
348 W83627 Super I/O driver. This can be used to enable the
349 legacy UART or other devices in the Winbond Super IO chips
350 on X86 platforms.
351
Miao Yanfcf5c042016-05-22 19:37:14 -0700352config QFW
353 bool
354 help
355 Hidden option to enable QEMU fw_cfg interface. This will be selected by
Miao Yan18686592016-05-22 19:37:17 -0700356 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
Miao Yanfcf5c042016-05-22 19:37:14 -0700357
mario.six@gdsys.ccd7e28912016-06-22 15:14:16 +0200358config I2C_EEPROM
359 bool "Enable driver for generic I2C-attached EEPROMs"
360 depends on MISC
361 help
362 Enable a generic driver for EEPROMs attached via I2C.
Adam Forde3f24d42017-08-13 09:00:28 -0500363
Wenyou Yangd81a1de2017-09-06 13:08:14 +0800364
365config SPL_I2C_EEPROM
366 bool "Enable driver for generic I2C-attached EEPROMs for SPL"
367 depends on MISC && SPL && SPL_DM
368 help
369 This option is an SPL-variant of the I2C_EEPROM option.
370 See the help of I2C_EEPROM for details.
371
Vipul Kumar5c32de22018-02-16 19:07:21 +0530372config ZYNQ_GEM_I2C_MAC_OFFSET
373 hex "Set the I2C MAC offset"
374 default 0x0
Michal Simek027b1132019-01-22 15:55:46 +0100375 depends on DM_I2C
Vipul Kumar5c32de22018-02-16 19:07:21 +0530376 help
377 Set the MAC offset for i2C.
378
Adam Forde3f24d42017-08-13 09:00:28 -0500379if I2C_EEPROM
380
381config SYS_I2C_EEPROM_ADDR
382 hex "Chip address of the EEPROM device"
383 default 0
384
385config SYS_I2C_EEPROM_BUS
386 int "I2C bus of the EEPROM device."
387 default 0
388
389config SYS_EEPROM_SIZE
390 int "Size in bytes of the EEPROM device"
391 default 256
392
393config SYS_EEPROM_PAGE_WRITE_BITS
394 int "Number of bits used to address bytes in a single page"
395 default 0
396 help
397 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
398 A 64 byte page, for example would require six bits.
399
400config SYS_EEPROM_PAGE_WRITE_DELAY_MS
401 int "Number of milliseconds to delay between page writes"
402 default 0
403
404config SYS_I2C_EEPROM_ADDR_LEN
405 int "Length in bytes of the EEPROM memory array address"
406 default 1
407 help
408 Note: This is NOT the chip address length!
409
410config SYS_I2C_EEPROM_ADDR_OVERFLOW
411 hex "EEPROM Address Overflow"
412 default 0
413 help
414 EEPROM chips that implement "address overflow" are ones
415 like Catalyst 24WC04/08/16 which has 9/10/11 bits of
416 address and the extra bits end up in the "chip address" bit
417 slots. This makes a 24WC08 (1Kbyte) chip look like four 256
418 byte chips.
419
420endif
421
Mario Six86da8c12018-04-27 14:53:33 +0200422config GDSYS_RXAUI_CTRL
423 bool "Enable gdsys RXAUI control driver"
424 depends on MISC
425 help
426 Support gdsys FPGA's RXAUI control.
Mario Six7e862422018-07-31 14:24:15 +0200427
428config GDSYS_IOEP
429 bool "Enable gdsys IOEP driver"
430 depends on MISC
431 help
432 Support gdsys FPGA's IO endpoint driver.
Mario Sixd2166312018-08-06 10:23:46 +0200433
434config MPC83XX_SERDES
435 bool "Enable MPC83xx serdes driver"
436 depends on MISC
437 help
438 Support for serdes found on MPC83xx SoCs.
439
Tien Fong Chee62030002018-07-06 16:28:03 +0800440config FS_LOADER
441 bool "Enable loader driver for file system"
442 help
443 This is file system generic loader which can be used to load
444 the file image from the storage into target such as memory.
445
446 The consumer driver would then use this loader to program whatever,
447 ie. the FPGA device.
448
Mario Sixc0a2b082018-10-04 09:00:54 +0200449config GDSYS_SOC
450 bool "Enable gdsys SOC driver"
451 depends on MISC
452 help
453 Support for gdsys IHS SOC, a simple bus associated with each gdsys
454 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
455 register maps are contained within the FPGA's register map.
456
Mario Sixab88bd22018-10-04 09:00:55 +0200457config IHS_FPGA
458 bool "Enable IHS FPGA driver"
459 depends on MISC
460 help
461 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
462 gdsys devices, which supply the majority of the functionality offered
463 by the devices. This driver supports both CON and CPU variants of the
464 devices, depending on the device tree entry.
Tero Kristo344eb6d2020-02-14 11:18:15 +0200465config ESM_K3
466 bool "Enable K3 ESM driver"
467 depends on ARCH_K3
468 help
469 Support ESM (Error Signaling Module) on TI K3 SoCs.
Mario Sixab88bd22018-10-04 09:00:55 +0200470
Eugen Hristevf8164952019-10-09 09:23:39 +0000471config MICROCHIP_FLEXCOM
472 bool "Enable Microchip Flexcom driver"
473 depends on MISC
474 help
475 The Atmel Flexcom is just a wrapper which embeds a SPI controller,
476 an I2C controller and an USART.
477 Only one function can be used at a time and is chosen at boot time
478 according to the device tree.
479
Tero Kristo9d233b42019-10-24 15:00:46 +0530480config K3_AVS0
481 depends on ARCH_K3 && SPL_DM_REGULATOR
482 bool "AVS class 0 support for K3 devices"
483 help
484 K3 devices have the optimized voltage values for the main voltage
485 domains stored in efuse within the VTM IP. This driver reads the
486 optimized voltage from the efuse, so that it can be programmed
487 to the PMIC on board.
488
Tero Kristo3b36b382020-02-14 11:18:16 +0200489config ESM_PMIC
490 bool "Enable PMIC ESM driver"
491 depends on DM_PMIC
492 help
493 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
494 typically to reboot the board in error condition.
495
Masahiro Yamada0b11dbf2015-07-26 02:46:26 +0900496endmenu