Masahiro Yamada | 0b11dbf | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 1 | # |
| 2 | # I2C subsystem configuration |
| 3 | # |
| 4 | |
Simon Glass | 59e11eb | 2021-07-10 21:14:35 -0600 | [diff] [blame] | 5 | menuconfig I2C |
| 6 | bool "I2C support" |
| 7 | default y |
| 8 | help |
| 9 | Note: |
| 10 | This is a stand-in for an option to enable I2C support. In fact this |
| 11 | simply enables building of the I2C directory for U-Boot. The actual |
| 12 | I2C feature is enabled by DM_I2C (for driver model) and |
| 13 | the #define CONFIG_SYS_I2C_LEGACY (for the legacy I2C stack). |
| 14 | |
| 15 | So at present there is no need to ever disable this option. |
| 16 | |
| 17 | Eventually it will: |
| 18 | |
| 19 | Enable support for the I2C (Inter-Integrated Circuit) bus in U-Boot. |
| 20 | I2C works with a clock and data line which can be driven by a |
| 21 | one or more masters or slaves. It is a fairly complex bus but is |
| 22 | widely used as it only needs two lines for communication. Speeds of |
| 23 | 400kbps are typical but up to 3.4Mbps is supported by some |
| 24 | hardware. Enable this option to build the drivers in drivers/i2c as |
| 25 | part of a U-Boot build. |
| 26 | |
| 27 | if I2C |
Masahiro Yamada | 0b11dbf | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 28 | |
Masahiro Yamada | b6036bc | 2015-01-13 12:44:35 +0900 | [diff] [blame] | 29 | config DM_I2C |
| 30 | bool "Enable Driver Model for I2C drivers" |
| 31 | depends on DM |
| 32 | help |
Przemyslaw Marczak | 705fcf4 | 2015-03-31 18:57:17 +0200 | [diff] [blame] | 33 | Enable driver model for I2C. The I2C uclass interface: probe, read, |
| 34 | write and speed, is implemented with the bus drivers operations, |
| 35 | which provide methods for bus setting and data transfer. Each chip |
Simon Glass | caa4daa | 2020-12-03 16:55:18 -0700 | [diff] [blame] | 36 | device (bus child) info is kept as parent plat. The interface |
Bartosz Golaszewski | e311482 | 2019-07-29 08:58:00 +0200 | [diff] [blame] | 37 | is defined in include/i2c.h. |
Simon Glass | 4bba9d3 | 2015-02-13 12:20:48 -0700 | [diff] [blame] | 38 | |
Igor Opaniuk | d1f3abe | 2021-02-09 13:52:43 +0200 | [diff] [blame] | 39 | config SPL_DM_I2C |
| 40 | bool "Enable Driver Model for I2C drivers in SPL" |
| 41 | depends on SPL_DM && DM_I2C |
| 42 | default y |
| 43 | help |
| 44 | Enable driver model for I2C. The I2C uclass interface: probe, read, |
| 45 | write and speed, is implemented with the bus drivers operations, |
| 46 | which provide methods for bus setting and data transfer. Each chip |
| 47 | device (bus child) info is kept as parent platdata. The interface |
| 48 | is defined in include/i2c.h. |
| 49 | |
Simon Glass | 747093d | 2022-04-30 00:56:53 -0600 | [diff] [blame] | 50 | config VPL_DM_I2C |
| 51 | bool "Enable Driver Model for I2C drivers in VPL" |
| 52 | depends on VPL_DM && DM_I2C |
| 53 | default y |
| 54 | help |
| 55 | Enable driver model for I2C. The I2C uclass interface: probe, read, |
| 56 | write and speed, is implemented with the bus drivers operations, |
| 57 | which provide methods for bus setting and data transfer. Each chip |
| 58 | device (bus child) info is kept as parent platdata. The interface |
| 59 | is defined in include/i2c.h. |
| 60 | |
Tom Rini | 55dabcc | 2021-08-18 23:12:24 -0400 | [diff] [blame] | 61 | config SYS_I2C_LEGACY |
| 62 | bool "Enable legacy I2C subsystem and drivers" |
| 63 | depends on !DM_I2C |
| 64 | help |
| 65 | Enable the legacy I2C subsystem and drivers. While this is |
| 66 | deprecated in U-Boot itself, this can be useful in some situations |
| 67 | in SPL or TPL. |
| 68 | |
| 69 | config SPL_SYS_I2C_LEGACY |
| 70 | bool "Enable legacy I2C subsystem and drivers in SPL" |
| 71 | depends on SUPPORT_SPL && !SPL_DM_I2C |
| 72 | help |
| 73 | Enable the legacy I2C subsystem and drivers in SPL. This is useful |
| 74 | in some size constrained situations. |
| 75 | |
| 76 | config TPL_SYS_I2C_LEGACY |
| 77 | bool "Enable legacy I2C subsystem and drivers in TPL" |
| 78 | depends on SUPPORT_TPL && !SPL_DM_I2C |
| 79 | help |
| 80 | Enable the legacy I2C subsystem and drivers in TPL. This is useful |
| 81 | in some size constrained situations. |
| 82 | |
Tom Rini | 52c7e37 | 2021-08-18 23:12:25 -0400 | [diff] [blame] | 83 | config SYS_I2C_EARLY_INIT |
| 84 | bool "Enable legacy I2C subsystem early in boot" |
| 85 | depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC |
| 86 | help |
| 87 | Add the function prototype for i2c_early_init_f which is called in |
| 88 | board_early_init_f. |
| 89 | |
Simon Glass | cc456bd | 2015-08-03 08:19:23 -0600 | [diff] [blame] | 90 | config I2C_CROS_EC_TUNNEL |
| 91 | tristate "Chrome OS EC tunnel I2C bus" |
| 92 | depends on CROS_EC |
| 93 | help |
| 94 | This provides an I2C bus that will tunnel i2c commands through to |
| 95 | the other side of the Chrome OS EC to the I2C bus connected there. |
| 96 | This will work whatever the interface used to talk to the EC (SPI, |
| 97 | I2C or LPC). Some Chromebooks use this when the hardware design |
| 98 | does not allow direct access to the main PMIC from the AP. |
| 99 | |
Simon Glass | f48eaf0 | 2015-08-03 08:19:24 -0600 | [diff] [blame] | 100 | config I2C_CROS_EC_LDO |
| 101 | bool "Provide access to LDOs on the Chrome OS EC" |
| 102 | depends on CROS_EC |
| 103 | ---help--- |
| 104 | On many Chromebooks the main PMIC is inaccessible to the AP. This is |
| 105 | often dealt with by using an I2C pass-through interface provided by |
| 106 | the EC. On some unfortunate models (e.g. Spring) the pass-through |
| 107 | is not available, and an LDO message is available instead. This |
| 108 | option enables a driver which provides very basic access to those |
| 109 | regulators, via the EC. We implement this as an I2C bus which |
| 110 | emulates just the TPS65090 messages we know about. This is done to |
| 111 | avoid duplicating the logic in the TPS65090 regulator driver for |
| 112 | enabling/disabling an LDO. |
Simon Glass | cc456bd | 2015-08-03 08:19:23 -0600 | [diff] [blame] | 113 | |
Lukasz Majewski | e46f8a3 | 2017-03-21 12:08:25 +0100 | [diff] [blame] | 114 | config I2C_SET_DEFAULT_BUS_NUM |
| 115 | bool "Set default I2C bus number" |
| 116 | depends on DM_I2C |
| 117 | help |
| 118 | Set default number of I2C bus to be accessed. This option provides |
| 119 | behaviour similar to old (i.e. pre DM) I2C bus driver. |
| 120 | |
| 121 | config I2C_DEFAULT_BUS_NUMBER |
| 122 | hex "I2C default bus number" |
| 123 | depends on I2C_SET_DEFAULT_BUS_NUM |
| 124 | default 0x0 |
| 125 | help |
| 126 | Number of default I2C bus to use |
| 127 | |
Przemyslaw Marczak | c54473c | 2015-03-31 18:57:18 +0200 | [diff] [blame] | 128 | config DM_I2C_GPIO |
| 129 | bool "Enable Driver Model for software emulated I2C bus driver" |
| 130 | depends on DM_I2C && DM_GPIO |
| 131 | help |
| 132 | Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO |
| 133 | configuration is given by the device tree. Kernel-style device tree |
| 134 | bindings are supported. |
| 135 | Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt |
| 136 | |
Igor Opaniuk | d1f3abe | 2021-02-09 13:52:43 +0200 | [diff] [blame] | 137 | config SPL_DM_I2C_GPIO |
| 138 | bool "Enable Driver Model for software emulated I2C bus driver in SPL" |
Simon Glass | 83061db | 2021-07-10 21:14:30 -0600 | [diff] [blame] | 139 | depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO |
Igor Opaniuk | d1f3abe | 2021-02-09 13:52:43 +0200 | [diff] [blame] | 140 | default y |
| 141 | help |
| 142 | Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO |
| 143 | configuration is given by the device tree. Kernel-style device tree |
| 144 | bindings are supported. |
| 145 | Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt |
| 146 | |
Songjun Wu | 8800e0f | 2016-06-20 13:22:38 +0800 | [diff] [blame] | 147 | config SYS_I2C_AT91 |
| 148 | bool "Atmel I2C driver" |
| 149 | depends on DM_I2C && ARCH_AT91 |
| 150 | help |
| 151 | Add support for the Atmel I2C driver. A serious problem is that there |
| 152 | is no documented way to issue repeated START conditions for more than |
| 153 | two messages, as needed to support combined I2C messages. Use the |
| 154 | i2c-gpio driver unless your system can cope with this limitation. |
| 155 | Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt |
| 156 | |
Rayagonda Kokatanur | 956d57a | 2020-04-08 11:12:27 +0530 | [diff] [blame] | 157 | config SYS_I2C_IPROC |
| 158 | bool "Broadcom I2C driver" |
| 159 | depends on DM_I2C |
| 160 | help |
| 161 | Broadcom I2C driver. |
| 162 | Add support for Broadcom I2C driver. |
| 163 | Say yes here to to enable the Broadco I2C driver. |
| 164 | |
mario.six@gdsys.cc | dbc82ce | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 165 | config SYS_I2C_FSL |
| 166 | bool "Freescale I2C bus driver" |
mario.six@gdsys.cc | dbc82ce | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 167 | help |
| 168 | Add support for Freescale I2C busses as used on MPC8240, MPC8245, and |
| 169 | MPC85xx processors. |
| 170 | |
Tom Rini | 6d5d0c9 | 2021-08-18 23:12:35 -0400 | [diff] [blame] | 171 | if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) |
| 172 | config SYS_FSL_I2C_OFFSET |
| 173 | hex "Offset from the IMMR of the address of the first I2C controller" |
| 174 | |
| 175 | config SYS_FSL_HAS_I2C2_OFFSET |
| 176 | bool "Support a second I2C controller" |
| 177 | |
| 178 | config SYS_FSL_I2C2_OFFSET |
| 179 | hex "Offset from the IMMR of the address of the second I2C controller" |
| 180 | depends on SYS_FSL_HAS_I2C2_OFFSET |
| 181 | |
| 182 | config SYS_FSL_HAS_I2C3_OFFSET |
| 183 | bool "Support a third I2C controller" |
| 184 | |
| 185 | config SYS_FSL_I2C3_OFFSET |
| 186 | hex "Offset from the IMMR of the address of the third I2C controller" |
| 187 | depends on SYS_FSL_HAS_I2C3_OFFSET |
| 188 | |
| 189 | config SYS_FSL_HAS_I2C4_OFFSET |
| 190 | bool "Support a fourth I2C controller" |
| 191 | |
| 192 | config SYS_FSL_I2C4_OFFSET |
| 193 | hex "Offset from the IMMR of the address of the fourth I2C controller" |
| 194 | depends on SYS_FSL_HAS_I2C4_OFFSET |
| 195 | endif |
| 196 | |
Moritz Fischer | fdec2d2 | 2015-12-28 09:47:11 -0800 | [diff] [blame] | 197 | config SYS_I2C_CADENCE |
| 198 | tristate "Cadence I2C Controller" |
Michal Simek | 664e16c | 2020-08-06 15:18:36 +0200 | [diff] [blame] | 199 | depends on DM_I2C |
Moritz Fischer | fdec2d2 | 2015-12-28 09:47:11 -0800 | [diff] [blame] | 200 | help |
| 201 | Say yes here to select Cadence I2C Host Controller. This controller is |
| 202 | e.g. used by Xilinx Zynq. |
| 203 | |
Arthur Li | 7f5ea25 | 2020-06-01 12:56:31 -0700 | [diff] [blame] | 204 | config SYS_I2C_CA |
| 205 | tristate "Cortina-Access I2C Controller" |
| 206 | depends on DM_I2C && CORTINA_PLATFORM |
Arthur Li | 7f5ea25 | 2020-06-01 12:56:31 -0700 | [diff] [blame] | 207 | help |
| 208 | Add support for the Cortina Access I2C host controller. |
| 209 | Say yes here to select Cortina-Access I2C Host Controller. |
| 210 | |
Adam Ford | 9f8cf76 | 2018-08-10 05:05:22 -0500 | [diff] [blame] | 211 | config SYS_I2C_DAVINCI |
| 212 | bool "Davinci I2C Controller" |
| 213 | depends on (ARCH_KEYSTONE || ARCH_DAVINCI) |
| 214 | help |
| 215 | Say yes here to add support for Davinci and Keystone I2C controller |
| 216 | |
Stefan Roese | e32d0db | 2016-04-28 09:47:17 +0200 | [diff] [blame] | 217 | config SYS_I2C_DW |
| 218 | bool "Designware I2C Controller" |
Stefan Roese | e32d0db | 2016-04-28 09:47:17 +0200 | [diff] [blame] | 219 | help |
| 220 | Say yes here to select the Designware I2C Host Controller. This |
| 221 | controller is used in various SoCs, e.g. the ST SPEAr, Altera |
| 222 | SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs. |
| 223 | |
Ryan Chen | 4088f5f | 2023-01-30 14:19:24 +0800 | [diff] [blame] | 224 | config SYS_I2C_AST2600 |
| 225 | bool "AST2600 I2C Controller" |
| 226 | depends on DM_I2C && ARCH_ASPEED |
| 227 | help |
| 228 | Say yes here to select AST2600 I2C Host Controller. The driver |
| 229 | support AST2600 I2C new mode register. This I2C controller supports: |
| 230 | _Standard-mode (up to 100 kHz) |
| 231 | _Fast-mode (up to 400 kHz) |
| 232 | _Fast-mode Plus (up to 1 MHz) |
| 233 | |
maxims@google.com | 4dc038f | 2017-04-17 12:00:30 -0700 | [diff] [blame] | 234 | config SYS_I2C_ASPEED |
| 235 | bool "Aspeed I2C Controller" |
| 236 | depends on DM_I2C && ARCH_ASPEED |
| 237 | help |
| 238 | Say yes here to select Aspeed I2C Host Controller. The driver |
| 239 | supports AST2500 and AST2400 controllers, but is very limited. |
| 240 | Only single master mode is supported and only byte-by-byte |
| 241 | synchronous reads and writes are supported, no Pool Buffers or DMA. |
| 242 | |
Simon Glass | abb0b01 | 2016-01-17 16:11:44 -0700 | [diff] [blame] | 243 | config SYS_I2C_INTEL |
| 244 | bool "Intel I2C/SMBUS driver" |
| 245 | depends on DM_I2C |
| 246 | help |
| 247 | Add support for the Intel SMBUS driver. So far this driver is just |
| 248 | a stub which perhaps some basic init. There is no implementation of |
| 249 | the I2C API meaning that any I2C operations will immediately fail |
| 250 | for now. |
| 251 | |
Peng Fan | 7ee3f14 | 2017-02-24 09:54:18 +0800 | [diff] [blame] | 252 | config SYS_I2C_IMX_LPI2C |
| 253 | bool "NXP i.MX LPI2C driver" |
Peng Fan | 7ee3f14 | 2017-02-24 09:54:18 +0800 | [diff] [blame] | 254 | help |
| 255 | Add support for the NXP i.MX LPI2C driver. |
| 256 | |
Trevor Woerner | 0705556 | 2021-06-10 22:37:08 -0400 | [diff] [blame] | 257 | config SYS_I2C_LPC32XX |
| 258 | bool "LPC32XX I2C driver" |
| 259 | depends on ARCH_LPC32XX |
| 260 | help |
| 261 | Enable support for the LPC32xx I2C driver. |
| 262 | |
Beniamino Galvani | f8d9ca1 | 2017-10-29 10:09:00 +0100 | [diff] [blame] | 263 | config SYS_I2C_MESON |
| 264 | bool "Amlogic Meson I2C driver" |
| 265 | depends on DM_I2C && ARCH_MESON |
| 266 | help |
Beniamino Galvani | 4ecbb8b | 2017-11-26 17:40:54 +0100 | [diff] [blame] | 267 | Add support for the I2C controller available in Amlogic Meson |
| 268 | SoCs. The controller supports programmable bus speed including |
| 269 | standard (100kbits/s) and fast (400kbit/s) speed and allows the |
| 270 | software to define a flexible format of the bit streams. It has an |
| 271 | internal buffer holding up to 8 bytes for transfers and supports |
| 272 | both 7-bit and 10-bit addresses. |
Beniamino Galvani | f8d9ca1 | 2017-10-29 10:09:00 +0100 | [diff] [blame] | 273 | |
Weijie Gao | 9ad71f6 | 2022-09-09 19:59:48 +0800 | [diff] [blame] | 274 | config SYS_I2C_MTK |
| 275 | bool "MediaTek I2C driver" |
| 276 | help |
| 277 | This selects the MediaTek Integrated Inter Circuit bus driver. |
| 278 | The I2C bus adapter is the base for some other I2C client, |
| 279 | eg: touch, sensors. |
| 280 | If you want to use MediaTek I2C interface, say Y here. |
| 281 | If unsure, say N. |
| 282 | |
Padmarao Begari | 0dc0d1e | 2021-11-17 18:21:16 +0530 | [diff] [blame] | 283 | config SYS_I2C_MICROCHIP |
| 284 | bool "Microchip I2C driver" |
| 285 | help |
| 286 | Add support for the Microchip I2C driver. This is operating on |
| 287 | standard mode up to 100 kbits/s and fast mode up to 400 kbits/s. |
| 288 | |
Jagan Teki | 72c8c10 | 2016-12-06 00:00:57 +0100 | [diff] [blame] | 289 | config SYS_I2C_MXC |
Sriram Dash | 942ecc8 | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 290 | bool "NXP MXC I2C driver" |
Jagan Teki | 72c8c10 | 2016-12-06 00:00:57 +0100 | [diff] [blame] | 291 | help |
Chris Packham | 7475145 | 2019-01-13 22:13:25 +1300 | [diff] [blame] | 292 | Add support for the NXP I2C driver. This supports up to four bus |
| 293 | channels and operating on standard mode up to 100 kbits/s and fast |
| 294 | mode up to 400 kbits/s. |
Jagan Teki | 72c8c10 | 2016-12-06 00:00:57 +0100 | [diff] [blame] | 295 | |
Tom Rini | 15e7b76 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 296 | if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) |
Sriram Dash | 942ecc8 | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 297 | config SYS_I2C_MXC_I2C1 |
| 298 | bool "NXP MXC I2C1" |
| 299 | help |
| 300 | Add support for NXP MXC I2C Controller 1. |
| 301 | Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A |
| 302 | |
| 303 | config SYS_I2C_MXC_I2C2 |
| 304 | bool "NXP MXC I2C2" |
| 305 | help |
| 306 | Add support for NXP MXC I2C Controller 2. |
| 307 | Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A |
| 308 | |
| 309 | config SYS_I2C_MXC_I2C3 |
| 310 | bool "NXP MXC I2C3" |
| 311 | help |
| 312 | Add support for NXP MXC I2C Controller 3. |
| 313 | Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A |
| 314 | |
| 315 | config SYS_I2C_MXC_I2C4 |
| 316 | bool "NXP MXC I2C4" |
| 317 | help |
| 318 | Add support for NXP MXC I2C Controller 4. |
| 319 | Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A |
Sriram Dash | fa45219 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 320 | |
| 321 | config SYS_I2C_MXC_I2C5 |
| 322 | bool "NXP MXC I2C5" |
| 323 | help |
| 324 | Add support for NXP MXC I2C Controller 5. |
| 325 | Required for SoCs which have I2C MXC controller 5 eg LX2160A |
| 326 | |
| 327 | config SYS_I2C_MXC_I2C6 |
| 328 | bool "NXP MXC I2C6" |
| 329 | help |
| 330 | Add support for NXP MXC I2C Controller 6. |
| 331 | Required for SoCs which have I2C MXC controller 6 eg LX2160A |
| 332 | |
| 333 | config SYS_I2C_MXC_I2C7 |
| 334 | bool "NXP MXC I2C7" |
| 335 | help |
| 336 | Add support for NXP MXC I2C Controller 7. |
| 337 | Required for SoCs which have I2C MXC controller 7 eg LX2160A |
| 338 | |
| 339 | config SYS_I2C_MXC_I2C8 |
| 340 | bool "NXP MXC I2C8" |
| 341 | help |
| 342 | Add support for NXP MXC I2C Controller 8. |
| 343 | Required for SoCs which have I2C MXC controller 8 eg LX2160A |
Sriram Dash | 942ecc8 | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 344 | endif |
| 345 | |
| 346 | if SYS_I2C_MXC_I2C1 |
| 347 | config SYS_MXC_I2C1_SPEED |
| 348 | int "I2C Channel 1 speed" |
Tom Rini | 2ce7b65 | 2021-02-09 08:03:10 -0500 | [diff] [blame] | 349 | default 40000000 if TARGET_LS2080A_EMU |
Sriram Dash | 942ecc8 | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 350 | default 100000 |
| 351 | help |
| 352 | MXC I2C Channel 1 speed |
| 353 | |
| 354 | config SYS_MXC_I2C1_SLAVE |
Tom Rini | 15e7b76 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 355 | hex "I2C1 Slave" |
Sriram Dash | 942ecc8 | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 356 | default 0 |
| 357 | help |
| 358 | MXC I2C1 Slave |
| 359 | endif |
| 360 | |
| 361 | if SYS_I2C_MXC_I2C2 |
| 362 | config SYS_MXC_I2C2_SPEED |
| 363 | int "I2C Channel 2 speed" |
Tom Rini | 2ce7b65 | 2021-02-09 08:03:10 -0500 | [diff] [blame] | 364 | default 40000000 if TARGET_LS2080A_EMU |
Sriram Dash | 942ecc8 | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 365 | default 100000 |
| 366 | help |
| 367 | MXC I2C Channel 2 speed |
| 368 | |
| 369 | config SYS_MXC_I2C2_SLAVE |
Tom Rini | 15e7b76 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 370 | hex "I2C2 Slave" |
Sriram Dash | 942ecc8 | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 371 | default 0 |
| 372 | help |
| 373 | MXC I2C2 Slave |
| 374 | endif |
| 375 | |
| 376 | if SYS_I2C_MXC_I2C3 |
| 377 | config SYS_MXC_I2C3_SPEED |
| 378 | int "I2C Channel 3 speed" |
| 379 | default 100000 |
| 380 | help |
| 381 | MXC I2C Channel 3 speed |
| 382 | |
| 383 | config SYS_MXC_I2C3_SLAVE |
Tom Rini | 15e7b76 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 384 | hex "I2C3 Slave" |
Sriram Dash | 942ecc8 | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 385 | default 0 |
| 386 | help |
| 387 | MXC I2C3 Slave |
| 388 | endif |
| 389 | |
| 390 | if SYS_I2C_MXC_I2C4 |
| 391 | config SYS_MXC_I2C4_SPEED |
| 392 | int "I2C Channel 4 speed" |
| 393 | default 100000 |
| 394 | help |
| 395 | MXC I2C Channel 4 speed |
| 396 | |
| 397 | config SYS_MXC_I2C4_SLAVE |
Tom Rini | 15e7b76 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 398 | hex "I2C4 Slave" |
Sriram Dash | 942ecc8 | 2018-02-06 11:26:30 +0530 | [diff] [blame] | 399 | default 0 |
| 400 | help |
| 401 | MXC I2C4 Slave |
| 402 | endif |
| 403 | |
Sriram Dash | fa45219 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 404 | if SYS_I2C_MXC_I2C5 |
| 405 | config SYS_MXC_I2C5_SPEED |
| 406 | int "I2C Channel 5 speed" |
| 407 | default 100000 |
| 408 | help |
| 409 | MXC I2C Channel 5 speed |
| 410 | |
| 411 | config SYS_MXC_I2C5_SLAVE |
Tom Rini | 15e7b76 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 412 | hex "I2C5 Slave" |
Sriram Dash | fa45219 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 413 | default 0 |
| 414 | help |
| 415 | MXC I2C5 Slave |
| 416 | endif |
| 417 | |
| 418 | if SYS_I2C_MXC_I2C6 |
| 419 | config SYS_MXC_I2C6_SPEED |
| 420 | int "I2C Channel 6 speed" |
| 421 | default 100000 |
| 422 | help |
| 423 | MXC I2C Channel 6 speed |
| 424 | |
| 425 | config SYS_MXC_I2C6_SLAVE |
Tom Rini | 15e7b76 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 426 | hex "I2C6 Slave" |
Sriram Dash | fa45219 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 427 | default 0 |
| 428 | help |
| 429 | MXC I2C6 Slave |
| 430 | endif |
| 431 | |
| 432 | if SYS_I2C_MXC_I2C7 |
| 433 | config SYS_MXC_I2C7_SPEED |
| 434 | int "I2C Channel 7 speed" |
| 435 | default 100000 |
| 436 | help |
| 437 | MXC I2C Channel 7 speed |
| 438 | |
| 439 | config SYS_MXC_I2C7_SLAVE |
Tom Rini | 15e7b76 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 440 | hex "I2C7 Slave" |
Sriram Dash | fa45219 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 441 | default 0 |
| 442 | help |
| 443 | MXC I2C7 Slave |
| 444 | endif |
| 445 | |
| 446 | if SYS_I2C_MXC_I2C8 |
| 447 | config SYS_MXC_I2C8_SPEED |
| 448 | int "I2C Channel 8 speed" |
| 449 | default 100000 |
| 450 | help |
| 451 | MXC I2C Channel 8 speed |
| 452 | |
| 453 | config SYS_MXC_I2C8_SLAVE |
Tom Rini | 15e7b76 | 2021-08-18 23:12:33 -0400 | [diff] [blame] | 454 | hex "I2C8 Slave" |
Sriram Dash | fa45219 | 2018-02-06 11:26:31 +0530 | [diff] [blame] | 455 | default 0 |
| 456 | help |
| 457 | MXC I2C8 Slave |
| 458 | endif |
| 459 | |
Stefan Bosch | c25e9e0 | 2020-07-10 19:07:28 +0200 | [diff] [blame] | 460 | config SYS_I2C_NEXELL |
| 461 | bool "Nexell I2C driver" |
| 462 | depends on DM_I2C |
| 463 | help |
| 464 | Add support for the Nexell I2C driver. This is used with various |
| 465 | Nexell parts such as S5Pxx18 series SoCs. All chips |
| 466 | have several I2C ports and all are provided, controlled by the |
| 467 | device tree. |
| 468 | |
Jim Liu | 2b77eea | 2022-06-23 13:31:42 +0800 | [diff] [blame] | 469 | config SYS_I2C_NPCM |
| 470 | bool "Nuvoton NPCM I2C driver" |
| 471 | help |
| 472 | Support for Nuvoton I2C controller driver. |
| 473 | |
Pragnesh Patel | b2d4cbe | 2020-11-14 14:42:34 +0530 | [diff] [blame] | 474 | config SYS_I2C_OCORES |
| 475 | bool "ocores I2C driver" |
| 476 | depends on DM_I2C |
| 477 | help |
| 478 | Add support for ocores I2C controller. For details see |
| 479 | https://opencores.org/projects/i2c |
| 480 | |
Adam Ford | daa0f05 | 2017-08-07 13:11:34 -0500 | [diff] [blame] | 481 | config SYS_I2C_OMAP24XX |
| 482 | bool "TI OMAP2+ I2C driver" |
Vignesh R | 14106bc | 2019-06-04 18:08:11 -0500 | [diff] [blame] | 483 | depends on ARCH_OMAP2PLUS || ARCH_K3 |
Adam Ford | daa0f05 | 2017-08-07 13:11:34 -0500 | [diff] [blame] | 484 | help |
| 485 | Add support for the OMAP2+ I2C driver. |
| 486 | |
Marek Vasut | a06a0ac | 2018-04-21 18:57:28 +0200 | [diff] [blame] | 487 | config SYS_I2C_RCAR_I2C |
| 488 | bool "Renesas RCar I2C driver" |
| 489 | depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C |
| 490 | help |
| 491 | Support for Renesas RCar I2C controller. |
| 492 | |
Marek Vasut | 9e75ea4 | 2017-11-28 08:02:27 +0100 | [diff] [blame] | 493 | config SYS_I2C_RCAR_IIC |
| 494 | bool "Renesas RCar Gen3 IIC driver" |
Marek Vasut | f51155e | 2018-02-17 02:17:40 +0100 | [diff] [blame] | 495 | depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C |
Marek Vasut | 9e75ea4 | 2017-11-28 08:02:27 +0100 | [diff] [blame] | 496 | help |
| 497 | Support for Renesas RCar Gen3 IIC controller. |
| 498 | |
Simon Glass | 3437469 | 2015-08-30 16:55:39 -0600 | [diff] [blame] | 499 | config SYS_I2C_ROCKCHIP |
| 500 | bool "Rockchip I2C driver" |
| 501 | depends on DM_I2C |
| 502 | help |
| 503 | Add support for the Rockchip I2C driver. This is used with various |
| 504 | Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips |
Chris Packham | 7475145 | 2019-01-13 22:13:25 +1300 | [diff] [blame] | 505 | have several I2C ports and all are provided, controlled by the |
Simon Glass | 3437469 | 2015-08-30 16:55:39 -0600 | [diff] [blame] | 506 | device tree. |
| 507 | |
Simon Glass | 1174aad | 2015-03-06 13:19:04 -0700 | [diff] [blame] | 508 | config SYS_I2C_SANDBOX |
| 509 | bool "Sandbox I2C driver" |
| 510 | depends on SANDBOX && DM_I2C |
| 511 | help |
| 512 | Enable I2C support for sandbox. This is an emulation of a real I2C |
| 513 | bus. Devices can be attached to the bus using the device tree |
Masahiro Yamada | c77c7db | 2017-02-11 12:39:55 +0900 | [diff] [blame] | 514 | which specifies the driver to use. See sandbox.dts as an example. |
Simon Glass | 1174aad | 2015-03-06 13:19:04 -0700 | [diff] [blame] | 515 | |
Tom Rini | 6aa0754 | 2021-08-18 23:12:34 -0400 | [diff] [blame] | 516 | config SYS_I2C_SH |
| 517 | bool "Legacy SuperH I2C interface" |
| 518 | depends on ARCH_RMOBILE && SYS_I2C_LEGACY |
| 519 | help |
| 520 | Enable the legacy SuperH I2C interface. |
| 521 | |
| 522 | if SYS_I2C_SH |
| 523 | config SYS_I2C_SH_NUM_CONTROLLERS |
| 524 | int |
| 525 | default 5 |
| 526 | |
| 527 | config SYS_I2C_SH_BASE0 |
| 528 | hex |
| 529 | default 0xE6820000 |
| 530 | |
| 531 | config SYS_I2C_SH_BASE1 |
| 532 | hex |
| 533 | default 0xE6822000 |
| 534 | |
| 535 | config SYS_I2C_SH_BASE2 |
| 536 | hex |
| 537 | default 0xE6824000 |
| 538 | |
| 539 | config SYS_I2C_SH_BASE3 |
| 540 | hex |
| 541 | default 0xE6826000 |
| 542 | |
| 543 | config SYS_I2C_SH_BASE4 |
| 544 | hex |
| 545 | default 0xE6828000 |
| 546 | |
| 547 | config SH_I2C_8BIT |
| 548 | bool |
| 549 | default y |
| 550 | |
| 551 | config SH_I2C_DATA_HIGH |
| 552 | int |
| 553 | default 4 |
| 554 | |
| 555 | config SH_I2C_DATA_LOW |
| 556 | int |
| 557 | default 5 |
| 558 | |
| 559 | config SH_I2C_CLOCK |
| 560 | int |
| 561 | default 104000000 |
| 562 | endif |
| 563 | |
Tom Rini | de69572 | 2021-08-17 17:59:46 -0400 | [diff] [blame] | 564 | config SYS_I2C_SOFT |
| 565 | bool "Legacy software I2C interface" |
| 566 | help |
| 567 | Enable the legacy software defined I2C interface |
| 568 | |
| 569 | config SYS_I2C_SOFT_SPEED |
| 570 | int "Software I2C bus speed" |
| 571 | depends on SYS_I2C_SOFT |
| 572 | default 100000 |
| 573 | help |
| 574 | Speed of the software I2C bus |
| 575 | |
| 576 | config SYS_I2C_SOFT_SLAVE |
| 577 | hex "Software I2C slave address" |
| 578 | depends on SYS_I2C_SOFT |
| 579 | default 0xfe |
| 580 | help |
| 581 | Slave address of the software I2C bus |
| 582 | |
Suneel Garapati | 5c2c3e8 | 2020-05-26 14:13:07 +0200 | [diff] [blame] | 583 | config SYS_I2C_OCTEON |
| 584 | bool "Octeon II/III/TX/TX2 I2C driver" |
| 585 | depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C |
| 586 | default y |
| 587 | help |
| 588 | Add support for the Marvell Octeon I2C driver. This is used with |
| 589 | various Octeon parts such as Octeon II/III and OcteonTX/TX2. All |
| 590 | chips have several I2C ports and all are provided, controlled by |
| 591 | the device tree. |
| 592 | |
Sumit Garg | 9bdec96 | 2023-02-01 19:29:00 +0530 | [diff] [blame] | 593 | config SYS_I2C_QUP |
| 594 | bool "Qualcomm QUP I2C controller" |
| 595 | depends on ARCH_SNAPDRAGON |
| 596 | help |
| 597 | Support for Qualcomm QUP I2C controller based on Qualcomm Universal |
| 598 | Peripherals (QUP) engine. The QUP engine is an advanced high |
| 599 | performance slave port that provides a common data path (an output |
| 600 | FIFO and an input FIFO) for I2C and SPI interfaces. The I2C/SPI QUP |
| 601 | controller is publicly documented in the Snapdragon 410E (APQ8016E) |
| 602 | Technical Reference Manual, chapter "6.1 Qualcomm Universal |
| 603 | Peripherals Engine (QUP)". |
| 604 | |
Jaehoon Chung | 1d61ad9 | 2017-01-09 14:47:52 +0900 | [diff] [blame] | 605 | config SYS_I2C_S3C24X0 |
| 606 | bool "Samsung I2C driver" |
Tom Rini | 0283da4 | 2021-08-17 17:59:42 -0400 | [diff] [blame] | 607 | depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C |
Jaehoon Chung | 1d61ad9 | 2017-01-09 14:47:52 +0900 | [diff] [blame] | 608 | help |
| 609 | Support for Samsung I2C controller as Samsung SoCs. |
Simon Glass | 1174aad | 2015-03-06 13:19:04 -0700 | [diff] [blame] | 610 | |
Patrice Chotard | 4fadcaf | 2017-08-09 14:45:27 +0200 | [diff] [blame] | 611 | config SYS_I2C_STM32F7 |
| 612 | bool "STMicroelectronics STM32F7 I2C support" |
Patrick Delaunay | 2514c2d | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 613 | depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C |
Patrice Chotard | 4fadcaf | 2017-08-09 14:45:27 +0200 | [diff] [blame] | 614 | help |
| 615 | Enable this option to add support for STM32 I2C controller |
| 616 | introduced with STM32F7/H7 SoCs. This I2C controller supports : |
| 617 | _ Slave and master modes |
| 618 | _ Multimaster capability |
| 619 | _ Standard-mode (up to 100 kHz) |
| 620 | _ Fast-mode (up to 400 kHz) |
| 621 | _ Fast-mode Plus (up to 1 MHz) |
| 622 | _ 7-bit and 10-bit addressing mode |
| 623 | _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) |
| 624 | _ All 7-bit addresses acknowledge mode |
| 625 | _ General call |
| 626 | _ Programmable setup and hold times |
| 627 | _ Easy to use event management |
| 628 | _ Optional clock stretching |
| 629 | _ Software reset |
| 630 | |
Samuel Holland | 104950a | 2021-10-08 00:17:20 -0500 | [diff] [blame] | 631 | config SYS_I2C_SUN6I_P2WI |
| 632 | bool "Allwinner sun6i P2WI controller" |
| 633 | depends on ARCH_SUNXI |
| 634 | help |
| 635 | Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded |
| 636 | in the Allwinner A31 and A31s SOCs. This interface is used to connect |
| 637 | to specific devices like the X-Powers AXP221 PMIC. |
| 638 | |
Samuel Holland | 3227c85 | 2021-10-08 00:17:21 -0500 | [diff] [blame] | 639 | config SYS_I2C_SUN8I_RSB |
| 640 | bool "Allwinner sun8i Reduced Serial Bus controller" |
| 641 | depends on ARCH_SUNXI |
| 642 | help |
| 643 | Support for Allwinner's Reduced Serial Bus (RSB) controller. This |
| 644 | controller is responsible for communicating with various RSB based |
| 645 | devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs. |
| 646 | |
Jassi Brar | 4483fba | 2021-06-04 18:44:48 +0900 | [diff] [blame] | 647 | config SYS_I2C_SYNQUACER |
| 648 | bool "Socionext SynQuacer I2C controller" |
| 649 | depends on ARCH_SYNQUACER && DM_I2C |
| 650 | help |
| 651 | Support for Socionext Synquacer I2C controller. This I2C controller |
| 652 | will be used for RTC and LS-connector on DeveloperBox. |
| 653 | |
Peter Robinson | 02253d4 | 2019-02-20 12:17:26 +0000 | [diff] [blame] | 654 | config SYS_I2C_TEGRA |
| 655 | bool "NVIDIA Tegra internal I2C controller" |
Trevor Woerner | 18138ab | 2020-05-06 08:02:41 -0400 | [diff] [blame] | 656 | depends on ARCH_TEGRA |
Peter Robinson | 02253d4 | 2019-02-20 12:17:26 +0000 | [diff] [blame] | 657 | help |
| 658 | Support for NVIDIA I2C controller available in Tegra SoCs. |
| 659 | |
Masahiro Yamada | 26f820f | 2015-01-13 12:44:36 +0900 | [diff] [blame] | 660 | config SYS_I2C_UNIPHIER |
| 661 | bool "UniPhier I2C driver" |
| 662 | depends on ARCH_UNIPHIER && DM_I2C |
| 663 | default y |
| 664 | help |
Masahiro Yamada | b6ef3a3 | 2015-05-29 17:30:01 +0900 | [diff] [blame] | 665 | Support for UniPhier I2C controller driver. This I2C controller |
| 666 | is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. |
Masahiro Yamada | 238bd0b | 2015-01-13 12:44:37 +0900 | [diff] [blame] | 667 | |
| 668 | config SYS_I2C_UNIPHIER_F |
| 669 | bool "UniPhier FIFO-builtin I2C driver" |
| 670 | depends on ARCH_UNIPHIER && DM_I2C |
| 671 | default y |
| 672 | help |
Masahiro Yamada | b6ef3a3 | 2015-05-29 17:30:01 +0900 | [diff] [blame] | 673 | Support for UniPhier FIFO-builtin I2C controller driver. |
Masahiro Yamada | 238bd0b | 2015-01-13 12:44:37 +0900 | [diff] [blame] | 674 | This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. |
Simon Glass | 3d1957f | 2015-08-03 08:19:21 -0600 | [diff] [blame] | 675 | |
Heiko Schocher | e3bc4bb | 2018-10-11 07:26:33 +0200 | [diff] [blame] | 676 | config SYS_I2C_VERSATILE |
| 677 | bool "Arm Ltd Versatile I2C bus driver" |
Tom Rini | c6c26a0 | 2021-02-20 20:05:47 -0500 | [diff] [blame] | 678 | depends on DM_I2C && TARGET_VEXPRESS64_JUNO |
Heiko Schocher | e3bc4bb | 2018-10-11 07:26:33 +0200 | [diff] [blame] | 679 | help |
| 680 | Add support for the Arm Ltd Versatile Express I2C driver. The I2C host |
| 681 | controller is present in the development boards manufactured by Arm Ltd. |
| 682 | |
Marek BehĂșn | 999ac22 | 2021-10-09 19:33:37 +0200 | [diff] [blame] | 683 | config SYS_I2C_MV |
| 684 | bool "Marvell PXA (Armada 3720) I2C driver" |
| 685 | help |
| 686 | Support for PXA based I2C controller used on Armada 3720 SoC. |
| 687 | In Linux, this driver is called i2c-pxa. |
| 688 | |
mario.six@gdsys.cc | 14a6ff2 | 2016-07-21 11:57:10 +0200 | [diff] [blame] | 689 | config SYS_I2C_MVTWSI |
| 690 | bool "Marvell I2C driver" |
mario.six@gdsys.cc | 14a6ff2 | 2016-07-21 11:57:10 +0200 | [diff] [blame] | 691 | help |
| 692 | Support for Marvell I2C controllers as used on the orion5x and |
| 693 | kirkwood SoC families. |
| 694 | |
Stephen Warren | 34f1c9f | 2016-08-08 11:28:27 -0600 | [diff] [blame] | 695 | config TEGRA186_BPMP_I2C |
| 696 | bool "Enable Tegra186 BPMP-based I2C driver" |
| 697 | depends on TEGRA186_BPMP |
| 698 | help |
| 699 | Support for Tegra I2C controllers managed by the BPMP (Boot and |
| 700 | Power Management Processor). On Tegra186, some I2C controllers are |
| 701 | directly controlled by the main CPU, whereas others are controlled |
| 702 | by the BPMP, and can only be accessed by the main CPU via IPC |
| 703 | requests to the BPMP. This driver covers the latter case. |
| 704 | |
Tom Rini | a5752f8 | 2021-08-18 23:12:32 -0400 | [diff] [blame] | 705 | config SYS_I2C_SLAVE |
| 706 | hex "I2C Slave address channel (all buses)" |
| 707 | depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY |
| 708 | default 0xfe |
| 709 | help |
| 710 | I2C Slave address channel 0 for all buses in the legacy drivers. |
| 711 | Many boards/controllers/drivers don't support an I2C slave |
| 712 | interface so provide a default slave address for them for use in |
| 713 | common code. A real value for CONFIG_SYS_I2C_SLAVE should be |
| 714 | defined for any board which does support a slave interface and |
| 715 | this default used otherwise. |
| 716 | |
| 717 | config SYS_I2C_SPEED |
| 718 | int "I2C Slave channel 0 speed (all buses)" |
| 719 | depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY |
| 720 | default 100000 |
| 721 | help |
| 722 | I2C Slave speed channel 0 for all buses in the legacy drivers. |
| 723 | |
Adam Ford | fc760cc | 2017-08-11 06:39:34 -0500 | [diff] [blame] | 724 | config SYS_I2C_BUS_MAX |
| 725 | int "Max I2C busses" |
Tom Rini | cb42c1f | 2022-06-27 13:35:50 -0400 | [diff] [blame] | 726 | depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA |
Adam Ford | fc760cc | 2017-08-11 06:39:34 -0500 | [diff] [blame] | 727 | default 2 if TI816X |
Tom Rini | cb42c1f | 2022-06-27 13:35:50 -0400 | [diff] [blame] | 728 | default 3 if OMAP34XX || AM33XX || AM43XX |
Tom Rini | f552816 | 2022-12-02 16:42:41 -0500 | [diff] [blame] | 729 | default 4 if ARCH_SOCFPGA || OMAP44XX |
Adam Ford | fc760cc | 2017-08-11 06:39:34 -0500 | [diff] [blame] | 730 | default 5 if OMAP54XX |
| 731 | help |
| 732 | Define the maximum number of available I2C buses. |
| 733 | |
Marek Vasut | ad827a5 | 2018-12-19 12:26:27 +0100 | [diff] [blame] | 734 | config SYS_I2C_XILINX_XIIC |
| 735 | bool "Xilinx AXI I2C driver" |
| 736 | depends on DM_I2C |
| 737 | help |
| 738 | Support for Xilinx AXI I2C controller. |
| 739 | |
Mario Six | 9216421 | 2018-01-15 11:08:11 +0100 | [diff] [blame] | 740 | config SYS_I2C_IHS |
| 741 | bool "gdsys IHS I2C driver" |
| 742 | depends on DM_I2C |
| 743 | help |
| 744 | Support for gdsys IHS I2C driver on FPGA bus. |
| 745 | |
Simon Glass | 3d1957f | 2015-08-03 08:19:21 -0600 | [diff] [blame] | 746 | source "drivers/i2c/muxes/Kconfig" |
Masahiro Yamada | 0b11dbf | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 747 | |
Simon Glass | 59e11eb | 2021-07-10 21:14:35 -0600 | [diff] [blame] | 748 | endif |