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wdenkf4675562002-10-02 14:20:15 +00001/*
Wolfgang Denk29f8f582008-08-09 23:17:32 +02002 * (C) Copyright 2000-2008
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
37#define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */
38
39#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
40#undef CONFIG_8xx_CONS_SMC2
41#undef CONFIG_8xx_CONS_NONE
42
43#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
44
wdenkae3af052003-08-07 22:18:11 +000045#define CONFIG_BOOTCOUNT_LIMIT
wdenkf4675562002-10-02 14:20:15 +000046
wdenkae3af052003-08-07 22:18:11 +000047#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf4675562002-10-02 14:20:15 +000048
49#define CONFIG_BOARD_TYPES 1 /* support board types */
50
51#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010052 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenk6aff3112002-12-17 01:51:00 +000053 "echo"
wdenkf4675562002-10-02 14:20:15 +000054
55#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000056
57#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000058 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000059 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060 "nfsroot=${serverip}:${rootpath}\0" \
wdenk6aff3112002-12-17 01:51:00 +000061 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "addip=setenv bootargs ${bootargs} " \
63 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
64 ":${hostname}:${netdev}:off panic=1\0" \
wdenk6aff3112002-12-17 01:51:00 +000065 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066 "bootm ${kernel_addr}\0" \
wdenk6aff3112002-12-17 01:51:00 +000067 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010068 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
69 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk6aff3112002-12-17 01:51:00 +000070 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020071 "hostname=TQM860L\0" \
72 "bootfile=TQM860L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020073 "fdt_addr=40040000\0" \
74 "kernel_addr=40060000\0" \
75 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020076 "u-boot=TQM860L/u-image.bin\0" \
77 "load=tftp 200000 ${u-boot}\0" \
78 "update=prot off 40000000 +${filesize};" \
79 "era 40000000 +${filesize};" \
80 "cp.b 200000 40000000 ${filesize};" \
81 "sete filesize;save\0" \
wdenk6aff3112002-12-17 01:51:00 +000082 ""
83#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000084
85#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf4675562002-10-02 14:20:15 +000087
88#undef CONFIG_WATCHDOG /* watchdog disabled */
89
90#define CONFIG_STATUS_LED 1 /* Status LED enabled */
91
92#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
93
Jon Loeliger37d4bb72007-07-09 21:38:02 -050094/*
95 * BOOTP options
96 */
97#define CONFIG_BOOTP_SUBNETMASK
98#define CONFIG_BOOTP_GATEWAY
99#define CONFIG_BOOTP_HOSTNAME
100#define CONFIG_BOOTP_BOOTPATH
101#define CONFIG_BOOTP_BOOTFILESIZE
102
wdenkf4675562002-10-02 14:20:15 +0000103
104#define CONFIG_MAC_PARTITION
105#define CONFIG_DOS_PARTITION
106
107#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
108
Jon Loeliger26946902007-07-04 22:30:50 -0500109
110/*
111 * Command line configuration.
112 */
113#include <config_cmd_default.h>
114
115#define CONFIG_CMD_ASKENV
116#define CONFIG_CMD_DATE
117#define CONFIG_CMD_DHCP
118#define CONFIG_CMD_ELF
119#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200120#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500121#define CONFIG_CMD_NFS
122#define CONFIG_CMD_SNTP
123
wdenkf4675562002-10-02 14:20:15 +0000124
wdenk68ceb292004-08-02 21:11:11 +0000125#define CONFIG_NETCONSOLE
126
wdenkf4675562002-10-02 14:20:15 +0000127/*
128 * Miscellaneous configurable options
129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_LONGHELP /* undef to save memory */
131#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenkf4675562002-10-02 14:20:15 +0000132
Wolfgang Denk2751a952006-10-28 02:29:14 +0200133#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
135#ifdef CONFIG_SYS_HUSH_PARSER
136#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenkf4675562002-10-02 14:20:15 +0000137#endif
138
Jon Loeliger26946902007-07-04 22:30:50 -0500139#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000141#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000143#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
145#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
146#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
149#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf4675562002-10-02 14:20:15 +0000150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf4675562002-10-02 14:20:15 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkf4675562002-10-02 14:20:15 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkf4675562002-10-02 14:20:15 +0000156
157/*
158 * Low Level Configuration Settings
159 * (address mappings, register initial values, etc.)
160 * You should know what you are doing if you make changes here.
161 */
162/*-----------------------------------------------------------------------
163 * Internal Memory Mapped Register
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf4675562002-10-02 14:20:15 +0000166
167/*-----------------------------------------------------------------------
168 * Definitions for initial stack pointer and data area (in DPRAM)
169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
171#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
172#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
173#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
174#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf4675562002-10-02 14:20:15 +0000175
176/*-----------------------------------------------------------------------
177 * Start addresses for the final memory configuration
178 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf4675562002-10-02 14:20:15 +0000180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_SDRAM_BASE 0x00000000
182#define CONFIG_SYS_FLASH_BASE 0x40000000
183#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
184#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
185#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf4675562002-10-02 14:20:15 +0000186
187/*
188 * For booting Linux, the board info and command line data
189 * have to be in the first 8 MB of memory, since this is
190 * the maximum mapped by the Linux kernel during initialization.
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf4675562002-10-02 14:20:15 +0000193
194/*-----------------------------------------------------------------------
195 * FLASH organization
196 */
wdenkf4675562002-10-02 14:20:15 +0000197
Martin Krausee318d9e2007-09-27 11:10:08 +0200198/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200200#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
202#define CONFIG_SYS_FLASH_EMPTY_INFO
203#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
204#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
205#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000206
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200207#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200208#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
209#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkf4675562002-10-02 14:20:15 +0000210
211/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200212#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
213#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf4675562002-10-02 14:20:15 +0000214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200216
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200217#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
218
wdenkf4675562002-10-02 14:20:15 +0000219/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200220 * Dynamic MTD partition support
221 */
222#define CONFIG_JFFS2_CMDLINE
223#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
224
225#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
226 "128k(dtb)," \
227 "1664k(kernel)," \
228 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200229 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200230
231/*-----------------------------------------------------------------------
wdenkf4675562002-10-02 14:20:15 +0000232 * Hardware Information Block
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
235#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
236#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf4675562002-10-02 14:20:15 +0000237
238/*-----------------------------------------------------------------------
239 * Cache Configuration
240 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500242#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf4675562002-10-02 14:20:15 +0000244#endif
245
246/*-----------------------------------------------------------------------
247 * SYPCR - System Protection Control 11-9
248 * SYPCR can only be written once after reset!
249 *-----------------------------------------------------------------------
250 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
251 */
252#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf4675562002-10-02 14:20:15 +0000254 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
255#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf4675562002-10-02 14:20:15 +0000257#endif
258
259/*-----------------------------------------------------------------------
260 * SIUMCR - SIU Module Configuration 11-6
261 *-----------------------------------------------------------------------
262 * PCMCIA config., multi-function pin tri-state
263 */
264#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000266#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000268#endif /* CONFIG_CAN_DRIVER */
269
270/*-----------------------------------------------------------------------
271 * TBSCR - Time Base Status and Control 11-26
272 *-----------------------------------------------------------------------
273 * Clear Reference Interrupt Status, Timebase freezing enabled
274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf4675562002-10-02 14:20:15 +0000276
277/*-----------------------------------------------------------------------
278 * RTCSC - Real-Time Clock Status and Control Register 11-27
279 *-----------------------------------------------------------------------
280 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf4675562002-10-02 14:20:15 +0000282
283/*-----------------------------------------------------------------------
284 * PISCR - Periodic Interrupt Status and Control 11-31
285 *-----------------------------------------------------------------------
286 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
287 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf4675562002-10-02 14:20:15 +0000289
290/*-----------------------------------------------------------------------
291 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
292 *-----------------------------------------------------------------------
293 * Reset PLL lock status sticky bit, timer expired status bit and timer
294 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000295 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000297
298/*-----------------------------------------------------------------------
299 * SCCR - System Clock and reset Control Register 15-27
300 *-----------------------------------------------------------------------
301 * Set clock output, timebase and RTC source and divider,
302 * power management and some other internal clocks
303 */
304#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000306 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
307 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000308
309/*-----------------------------------------------------------------------
310 * PCMCIA stuff
311 *-----------------------------------------------------------------------
312 *
313 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
315#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
316#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
317#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
318#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
319#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
320#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
321#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf4675562002-10-02 14:20:15 +0000322
323/*-----------------------------------------------------------------------
324 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
325 *-----------------------------------------------------------------------
326 */
327
328#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
329
330#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
331#undef CONFIG_IDE_LED /* LED for ide not supported */
332#undef CONFIG_IDE_RESET /* reset for ide not supported */
333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
335#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf4675562002-10-02 14:20:15 +0000336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf4675562002-10-02 14:20:15 +0000338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf4675562002-10-02 14:20:15 +0000340
341/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000343
344/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000346
347/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf4675562002-10-02 14:20:15 +0000349
350/*-----------------------------------------------------------------------
351 *
352 *-----------------------------------------------------------------------
353 *
354 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_DER 0
wdenkf4675562002-10-02 14:20:15 +0000356
357/*
358 * Init Memory Controller:
359 *
360 * BR0/1 and OR0/1 (FLASH)
361 */
362
363#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
364#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
365
366/* used to re-map FLASH both when starting from SRAM or FLASH:
367 * restrict access enough to keep SRAM working (if any)
368 * but not too much to meddle with FLASH accesses
369 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
371#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf4675562002-10-02 14:20:15 +0000372
373/*
374 * FLASH timing:
375 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf4675562002-10-02 14:20:15 +0000377 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
380#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
381#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
384#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
385#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000386
387/*
388 * BR2/3 and OR2/3 (SDRAM)
389 *
390 */
391#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
392#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
393#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
394
395/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf4675562002-10-02 14:20:15 +0000397
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
399#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000400
401#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
403#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000404#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
406#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
407#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
408#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf4675562002-10-02 14:20:15 +0000409 BR_PS_8 | BR_MS_UPMB | BR_V )
410#endif /* CONFIG_CAN_DRIVER */
411
412/*
413 * Memory Periodic Timer Prescaler
414 *
415 * The Divider for PTA (refresh timer) configuration is based on an
416 * example SDRAM configuration (64 MBit, one bank). The adjustment to
417 * the number of chip selects (NCS) and the actually needed refresh
418 * rate is done by setting MPTPR.
419 *
420 * PTA is calculated from
421 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
422 *
423 * gclk CPU clock (not bus clock!)
424 * Trefresh Refresh cycle * 4 (four word bursts used)
425 *
426 * 4096 Rows from SDRAM example configuration
427 * 1000 factor s -> ms
428 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
429 * 4 Number of refresh cycles per period
430 * 64 Refresh cycle in ms per number of rows
431 * --------------------------------------------
432 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
433 *
434 * 50 MHz => 50.000.000 / Divider = 98
435 * 66 Mhz => 66.000.000 / Divider = 129
436 * 80 Mhz => 80.000.000 / Divider = 156
437 */
wdenke9132ea2004-04-24 23:23:30 +0000438
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
440#define CONFIG_SYS_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000441
442/*
443 * For 16 MBit, refresh rates could be 31.3 us
444 * (= 64 ms / 2K = 125 / quad bursts).
445 * For a simpler initialization, 15.6 us is used instead.
446 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
448 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf4675562002-10-02 14:20:15 +0000449 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
451#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000452
453/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
455#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000456
457/*
458 * MAMR settings for SDRAM
459 */
460
461/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000463 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
464 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
465/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000467 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
468 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
469
470
471/*
472 * Internal Definitions
473 *
474 * Boot Flags
475 */
476#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
477#define BOOTFLAG_WARM 0x02 /* Software reboot */
478
479#define CONFIG_SCC1_ENET
480#define CONFIG_FEC_ENET
481#define CONFIG_ETHPRIME "SCC ETHERNET"
482
483#endif /* __CONFIG_H */