blob: 95c68bce3cbde94206602dce5ce5d0c858ca256e [file] [log] [blame]
wdenk10a36a92004-07-10 23:02:23 +00001/*
2 * (C) Copyright 2002,2003 Motorola,Inc.
3 * Xianghua Xiao <X.Xiao@motorola.com>
4 *
5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
6 * Added support for Wind River SBC8560 board
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
Paul Gortmaker928435d2009-09-21 17:19:17 -040027/*
28 * sbc8560 board configuration file.
wdenk10a36a92004-07-10 23:02:23 +000029 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
Paul Gortmaker928435d2009-09-21 17:19:17 -040034/*
35 * Top level Makefile configuration choices
36 */
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020037#ifdef CONFIG_66
Paul Gortmaker928435d2009-09-21 17:19:17 -040038#define CONFIG_PCI_66
39#endif
40
41/*
42 * High Level Configuration Options
43 */
wdenk10a36a92004-07-10 23:02:23 +000044#define CONFIG_BOOKE 1 /* BOOKE */
45#define CONFIG_E500 1 /* BOOKE e500 family */
46#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
47#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
48
Wolfgang Denk2ae18242010-10-06 09:05:45 +020049#define CONFIG_SYS_TEXT_BASE 0xfffc0000
50
wdenk10a36a92004-07-10 23:02:23 +000051
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050052#define CONFIG_CPM2 1 /* has CPM2 */
wdenk10a36a92004-07-10 23:02:23 +000053#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
Kumar Galaf0600542008-06-11 00:44:10 -050054#define CONFIG_MPC8560 1
wdenk10a36a92004-07-10 23:02:23 +000055
56/* XXX flagging this as something I might want to delete */
57#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
58
59#define CONFIG_TSEC_ENET /* tsec ethernet support */
60#undef CONFIG_PCI /* pci ethernet support */
61#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
62
Kumar Galae2b159d2008-01-16 09:05:27 -060063#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk10a36a92004-07-10 23:02:23 +000064
65#define CONFIG_ENV_OVERWRITE
66
67/* Using Localbus SDRAM to emulate flash before we can program the flash,
68 * normally you need a flash-boot image(u-boot.bin), if so undef this.
69 */
70#undef CONFIG_RAM_AS_FLASH
71
72#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
73 #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
74#else
75 #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
76#endif
77
78/* below can be toggled for performance analysis. otherwise use default */
79#define CONFIG_L2_CACHE /* toggle L2 cache */
80#undef CONFIG_BTB /* toggle branch predition */
wdenk10a36a92004-07-10 23:02:23 +000081
82#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Peter Tyser004eca02009-09-16 22:03:08 -050083#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
wdenk10a36a92004-07-10 23:02:23 +000084
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
86#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
87#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk10a36a92004-07-10 23:02:23 +000088
89#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
90 defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
91 defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
92#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
93#endif
94
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
wdenk10a36a92004-07-10 23:02:23 +000096
Kumar Gala8e553132008-08-26 23:52:58 -050097/* DDR Setup */
98#define CONFIG_FSL_DDR1
99#undef CONFIG_FSL_DDR_INTERACTIVE
100#undef CONFIG_DDR_ECC /* only for ECC DDR module */
101#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
102#undef CONFIG_DDR_SPD
wdenk10a36a92004-07-10 23:02:23 +0000103
104#if defined(CONFIG_MPC85xx_REV1)
Becky Bruce810c4422010-12-17 17:17:58 -0600105#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
wdenk10a36a92004-07-10 23:02:23 +0000106#endif
107
Kumar Gala8e553132008-08-26 23:52:58 -0500108#undef CONFIG_DDR_ECC /* only for ECC DDR module */
109#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
110#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
113#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala8e553132008-08-26 23:52:58 -0500114#define CONFIG_VERY_BIG_RAM
115
116#define CONFIG_NUM_DDR_CONTROLLERS 1
117#define CONFIG_DIMM_SLOTS_PER_CTLR 1
118#define CONFIG_CHIP_SELECTS_PER_CTRL 2
119
120/* I2C addresses of SPD EEPROMs */
121#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
122
wdenk10a36a92004-07-10 23:02:23 +0000123#undef CONFIG_CLOCKS_IN_MHZ
124
125#if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126 #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
127 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
128 #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
129 #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
wdenk10a36a92004-07-10 23:02:23 +0000130#else /* Boot from real Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
132 #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
133 #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
134 #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
wdenk10a36a92004-07-10 23:02:23 +0000135#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk10a36a92004-07-10 23:02:23 +0000137
138/* local bus definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
140#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
wdenk10a36a92004-07-10 23:02:23 +0000141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
143#define CONFIG_SYS_OR2_PRELIM 0x00000000
wdenk10a36a92004-07-10 23:02:23 +0000144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
146#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
wdenk10a36a92004-07-10 23:02:23 +0000147
148#if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149 #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
wdenk10a36a92004-07-10 23:02:23 +0000150#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151 #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
wdenk10a36a92004-07-10 23:02:23 +0000152#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
wdenk10a36a92004-07-10 23:02:23 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
wdenk10a36a92004-07-10 23:02:23 +0000156#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
wdenk10a36a92004-07-10 23:02:23 +0000158#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159 #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
wdenk10a36a92004-07-10 23:02:23 +0000160#endif
161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
163#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
164#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
165#define CONFIG_SYS_LBC_LBCR 0x00000000
166#define CONFIG_SYS_LBC_LSRT 0x20000000
167#define CONFIG_SYS_LBC_MRTPR 0x20000000
168#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
169#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
170#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
171#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
172#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
wdenk10a36a92004-07-10 23:02:23 +0000173
174/* just hijack the MOT BCSR def for SBC8560 misc devices */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
wdenk10a36a92004-07-10 23:02:23 +0000176/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_INIT_RAM_LOCK 1
179#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200180#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk10a36a92004-07-10 23:02:23 +0000181
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200182#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk10a36a92004-07-10 23:02:23 +0000184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
186#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk10a36a92004-07-10 23:02:23 +0000187
188/* Serial Port */
Paul Gortmakerc158bca2008-07-11 15:33:05 -0400189#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
190#undef CONFIG_CONS_NONE /* define if console on something else */
wdenk10a36a92004-07-10 23:02:23 +0000191
192#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_NS16550
194#define CONFIG_SYS_NS16550_SERIAL
195#define CONFIG_SYS_NS16550_REG_SIZE 1
196#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
wdenk10a36a92004-07-10 23:02:23 +0000197#define CONFIG_BAUDRATE 9600
198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk10a36a92004-07-10 23:02:23 +0000200 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
203#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
wdenk10a36a92004-07-10 23:02:23 +0000204
205/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_HUSH_PARSER
207#ifdef CONFIG_SYS_HUSH_PARSER
208#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk10a36a92004-07-10 23:02:23 +0000209#endif
210
Paul Gortmakerc3ca7e52008-07-11 15:33:08 -0400211/* pass open firmware flat tree */
212#define CONFIG_OF_LIBFDT 1
213#define CONFIG_OF_BOARD_SETUP 1
214#define CONFIG_OF_STDOUT_VIA_ALIAS 1
215
Jon Loeliger20476722006-10-20 15:50:15 -0500216/*
217 * I2C
218 */
219#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
220#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk10a36a92004-07-10 23:02:23 +0000221#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
223#define CONFIG_SYS_I2C_SLAVE 0x7F
224#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
225#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk10a36a92004-07-10 23:02:23 +0000226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
228#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
229#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
wdenk10a36a92004-07-10 23:02:23 +0000230
Paul Gortmaker6de5bf22008-07-11 15:33:03 -0400231#ifdef CONFIG_TSEC_ENET
wdenk10a36a92004-07-10 23:02:23 +0000232
Paul Gortmaker6de5bf22008-07-11 15:33:03 -0400233#ifndef CONFIG_MII
234#define CONFIG_MII 1 /* MII PHY management */
235#endif
236#define CONFIG_TSEC1 1
237#define CONFIG_TSEC1_NAME "TSEC0"
238#define CONFIG_TSEC2 1
239#define CONFIG_TSEC2_NAME "TSEC1"
240#define TSEC1_PHY_ADDR 0x19
241#define TSEC2_PHY_ADDR 0x1a
242#define TSEC1_PHYIDX 0
243#define TSEC2_PHYIDX 0
244#define TSEC1_FLAGS TSEC_GIGABIT
245#define TSEC2_FLAGS TSEC_GIGABIT
246
247/* Options are: TSEC[0-1] */
248#define CONFIG_ETHPRIME "TSEC0"
wdenk10a36a92004-07-10 23:02:23 +0000249
250#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
251
252 #undef CONFIG_ETHER_NONE /* define if ether on something else */
253 #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
254 #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
255
256 #if (CONFIG_ETHER_INDEX == 2)
257 /*
258 * - Rx-CLK is CLK13
259 * - Tx-CLK is CLK14
260 * - Select bus for bd/buffers
261 * - Full duplex
262 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000263 #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
264 #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265 #define CONFIG_SYS_CPMFCR_RAMTYPE 0
266 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
wdenk10a36a92004-07-10 23:02:23 +0000267
268 #elif (CONFIG_ETHER_INDEX == 3)
269 /* need more definitions here for FE3 */
270 #endif /* CONFIG_ETHER_INDEX */
271
272 #define CONFIG_MII /* MII PHY management */
273 #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
274 /*
275 * GPIO pins used for bit-banged MII communications
276 */
277 #define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200278 #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
279 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
280 #define MDC_DECLARE MDIO_DECLARE
281
wdenk10a36a92004-07-10 23:02:23 +0000282 #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
283 #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
284 #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
285
286 #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
287 else iop->pdat &= ~0x00400000
288
289 #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
290 else iop->pdat &= ~0x00200000
291
292 #define MIIDELAY udelay(1)
293
294#endif
295
296/*-----------------------------------------------------------------------
297 * FLASH and environment organization
298 */
299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200301#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
wdenk10a36a92004-07-10 23:02:23 +0000302#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
304#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
wdenk10a36a92004-07-10 23:02:23 +0000305#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
307#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk10a36a92004-07-10 23:02:23 +0000308
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#undef CONFIG_SYS_FLASH_CHECKSUM
310#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
311#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
wdenk10a36a92004-07-10 23:02:23 +0000312
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200313#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk10a36a92004-07-10 23:02:23 +0000314
315#if 0
316/* XXX This doesn't work and I don't want to fix it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
318 #define CONFIG_SYS_RAMBOOT
wdenk10a36a92004-07-10 23:02:23 +0000319#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320 #undef CONFIG_SYS_RAMBOOT
wdenk10a36a92004-07-10 23:02:23 +0000321#endif
322#endif
323
324/* Environment */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#if !defined(CONFIG_SYS_RAMBOOT)
wdenk10a36a92004-07-10 23:02:23 +0000326 #if defined(CONFIG_RAM_AS_FLASH)
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200327 #define CONFIG_ENV_IS_NOWHERE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200329 #define CONFIG_ENV_SIZE 0x2000
wdenk10a36a92004-07-10 23:02:23 +0000330 #else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200331 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200332 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200334 #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
wdenk10a36a92004-07-10 23:02:23 +0000335 #endif
336#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200338 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200340 #define CONFIG_ENV_SIZE 0x2000
wdenk10a36a92004-07-10 23:02:23 +0000341#endif
342
Paul Gortmakerc158bca2008-07-11 15:33:05 -0400343#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600"
wdenk10a36a92004-07-10 23:02:23 +0000344/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
wdenk10a36a92004-07-10 23:02:23 +0000345#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
346
347#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200348#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk10a36a92004-07-10 23:02:23 +0000349
Jon Loeliger2835e512007-06-13 13:22:08 -0500350
351/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500352 * BOOTP options
353 */
354#define CONFIG_BOOTP_BOOTFILESIZE
355#define CONFIG_BOOTP_BOOTPATH
356#define CONFIG_BOOTP_GATEWAY
357#define CONFIG_BOOTP_HOSTNAME
358
359
360/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500361 * Command line configuration.
362 */
363#include <config_cmd_default.h>
364
365#define CONFIG_CMD_PING
366#define CONFIG_CMD_I2C
Becky Bruce199e2622010-06-17 11:37:25 -0500367#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500368
369#if defined(CONFIG_PCI)
370 #define CONFIG_CMD_PCI
wdenk10a36a92004-07-10 23:02:23 +0000371#endif
372
Jon Loeliger2835e512007-06-13 13:22:08 -0500373#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
374 #define CONFIG_CMD_MII
375#endif
376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500378 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500379 #undef CONFIG_CMD_LOADS
380#endif
381
wdenk10a36a92004-07-10 23:02:23 +0000382
383#undef CONFIG_WATCHDOG /* watchdog disabled */
384
385/*
386 * Miscellaneous configurable options
387 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200388#define CONFIG_SYS_LONGHELP /* undef to save memory */
389#define CONFIG_SYS_PROMPT "SBC8560=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500390#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk10a36a92004-07-10 23:02:23 +0000392#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk10a36a92004-07-10 23:02:23 +0000394#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
396#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
397#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
398#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
399#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk10a36a92004-07-10 23:02:23 +0000400
401/*
402 * For booting Linux, the board info and command line data
403 * have to be in the first 8 MB of memory, since this is
404 * the maximum mapped by the Linux kernel during initialization.
405 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200406#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk10a36a92004-07-10 23:02:23 +0000407
Jon Loeliger2835e512007-06-13 13:22:08 -0500408#if defined(CONFIG_CMD_KGDB)
Paul Gortmaker37fef492008-07-11 15:33:07 -0400409#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
410#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
wdenk10a36a92004-07-10 23:02:23 +0000411#endif
412
wdenk10a36a92004-07-10 23:02:23 +0000413#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
Paul Gortmakerc158bca2008-07-11 15:33:05 -0400414#define CONFIG_HAS_ETH0
415#define CONFIG_HAS_ETH1
wdenk10a36a92004-07-10 23:02:23 +0000416#endif
417
Paul Gortmakerc158bca2008-07-11 15:33:05 -0400418/* You can compile in a MAC address and your custom net settings by using
419 * the following syntax. Your board should be marked with the assigned
420 * MAC addresses directly on it.
421 *
422 * #define CONFIG_ETHADDR de:ad:be:ef:00:00
423 * #define CONFIG_ETH1ADDR fa:ke:ad:dr:es:s!
424 * #define CONFIG_SERVERIP <server ip>
425 * #define CONFIG_IPADDR <board ip>
426 * #define CONFIG_GATEWAYIP <gateway ip>
427 * #define CONFIG_NETMASK <your netmask>
428 */
429
wdenk10a36a92004-07-10 23:02:23 +0000430#define CONFIG_HOSTNAME SBC8560
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000431#define CONFIG_ROOTPATH "/home/ppc"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000432#define CONFIG_BOOTFILE "uImage"
Paul Gortmaker37fef492008-07-11 15:33:07 -0400433
434#define CONFIG_EXTRA_ENV_SETTINGS \
435 "netdev=eth0\0" \
436 "consoledev=ttyS0\0" \
437 "ramdiskaddr=2000000\0" \
438 "ramdiskfile=ramdisk.uboot\0" \
439 "fdtaddr=c00000\0" \
440 "fdtfile=sbc8560.dtb\0"
441
442#define CONFIG_NFSBOOTCOMMAND \
443 "setenv bootargs root=/dev/nfs rw " \
444 "nfsroot=$serverip:$rootpath " \
445 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
446 "console=$consoledev,$baudrate $othbootargs;" \
447 "tftp $loadaddr $bootfile;" \
448 "tftp $fdtaddr $fdtfile;" \
449 "bootm $loadaddr - $fdtaddr"
450
451
452#define CONFIG_RAMBOOTCOMMAND \
453 "setenv bootargs root=/dev/ram rw " \
454 "console=$consoledev,$baudrate $othbootargs;" \
455 "tftp $ramdiskaddr $ramdiskfile;" \
456 "tftp $loadaddr $bootfile;" \
457 "tftp $fdtaddr $fdtfile;" \
458 "bootm $loadaddr $ramdiskaddr $fdtaddr"
459
460#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk10a36a92004-07-10 23:02:23 +0000461
462#endif /* __CONFIG_H */