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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Chander Kashyape21185b2011-05-24 20:02:56 +00002/*
3 * Copyright (C) 2011 Samsung Electronics
4 *
Chander Kashyap393cb362011-12-06 23:34:12 +00005 * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board.
Chander Kashyape21185b2011-05-24 20:02:56 +00006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Simon Glass1d551102014-10-07 22:01:49 -060011#include "exynos4-common.h"
12
13#undef CONFIG_BOARD_COMMON
Marek Vasute30824f2015-08-19 23:27:26 +020014#undef CONFIG_USB_GADGET_DWC2_OTG_PHY
Simon Glass1d551102014-10-07 22:01:49 -060015#undef CONFIG_REVISION_TAG
Simon Glass1d551102014-10-07 22:01:49 -060016
Chander Kashyape21185b2011-05-24 20:02:56 +000017/* High Level Configuration Options */
Chander Kashyap393cb362011-12-06 23:34:12 +000018#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */
Chander Kashyape21185b2011-05-24 20:02:56 +000019
Chander Kashyapb3c5a492011-09-20 21:25:01 +000020/* Mach Type */
21#define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310
22
Chander Kashyape21185b2011-05-24 20:02:56 +000023#define CONFIG_SYS_SDRAM_BASE 0x40000000
Chander Kashyape21185b2011-05-24 20:02:56 +000024
Chander Kashyape21185b2011-05-24 20:02:56 +000025/* Handling Sleep Mode*/
26#define S5P_CHECK_SLEEP 0x00000BAD
27#define S5P_CHECK_DIDLE 0xBAD00000
Rajeshwari Shinde643be9c2013-07-04 12:29:17 +053028#define S5P_CHECK_LPA 0xABAD0000
Chander Kashyape21185b2011-05-24 20:02:56 +000029
Chander Kashyape21185b2011-05-24 20:02:56 +000030/* select serial console configuration */
Chander Kashyape21185b2011-05-24 20:02:56 +000031#define CONFIG_SERIAL1 1 /* use SERIAL 1 */
Chander Kashyap393cb362011-12-06 23:34:12 +000032#define EXYNOS4_DEFAULT_UART_OFFSET 0x010000
Chander Kashyape21185b2011-05-24 20:02:56 +000033
Chander Kashyape21185b2011-05-24 20:02:56 +000034/* allow to overwrite serial and ethaddr */
35#define CONFIG_ENV_OVERWRITE
36
Chander Kashyap5187d8d2011-09-20 21:25:03 +000037/* MMC SPL */
Rajeshwari Shinde643be9c2013-07-04 12:29:17 +053038#define CONFIG_SKIP_LOWLEVEL_INIT
Chander Kashyap9b3ab1c2011-09-20 21:25:04 +000039#define COPY_BL2_FNPTR_ADDR 0x00002488
Chander Kashyape21185b2011-05-24 20:02:56 +000040
Inderpal Singh8a000612013-04-04 23:09:21 +000041#define CONFIG_SPL_TEXT_BASE 0x02021410
42
Chander Kashyape21185b2011-05-24 20:02:56 +000043#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000"
44
45/* Miscellaneous configurable options */
Chander Kashyape21185b2011-05-24 20:02:56 +000046#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
Chander Kashyape21185b2011-05-24 20:02:56 +000047/* memtest works on */
48#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
49#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
50#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
51
Chander Kashyape21185b2011-05-24 20:02:56 +000052/* SMDKV310 has 4 bank of DRAM */
Chander Kashyape21185b2011-05-24 20:02:56 +000053#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
54#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
55#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
56#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
57#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
58#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
59#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
60#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
61#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
62
63/* FLASH and environment organization */
Chander Kashyape21185b2011-05-24 20:02:56 +000064
Chander Kashyape21185b2011-05-24 20:02:56 +000065#define CONFIG_CLK_1000_400_200
66
67/* MIU (Memory Interleaving Unit) */
68#define CONFIG_MIU_2BIT_INTERLEAVED
69
Chander Kashyape21185b2011-05-24 20:02:56 +000070#define CONFIG_SYS_MMC_ENV_DEV 0
71#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
72#define RESERVE_BLOCK_SIZE (512)
73#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
74#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE)
Chander Kashyape21185b2011-05-24 20:02:56 +000075
Rajeshwari Shinde643be9c2013-07-04 12:29:17 +053076#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
77
78#define CONFIG_SYS_INIT_SP_ADDR 0x02040000
Chander Kashyape21185b2011-05-24 20:02:56 +000079
Bin Menga1875592016-02-05 19:30:11 -080080/* U-Boot copy size from boot Media to DRAM.*/
Chander Kashyape21185b2011-05-24 20:02:56 +000081#define COPY_BL2_SIZE 0x80000
82#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
83#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)
84
85/* Ethernet Controllor Driver */
86#ifdef CONFIG_CMD_NET
Chander Kashyape21185b2011-05-24 20:02:56 +000087#define CONFIG_ENV_SROM_BANK 1
88#endif /*CONFIG_CMD_NET*/
Thomas Abraham07407d92011-06-03 22:52:17 +000089
Chander Kashyape21185b2011-05-24 20:02:56 +000090#endif /* __CONFIG_H */