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Jon Loeliger5c9efb32006-04-27 10:15:16 -05001/*
Kumar Gala1b77ca82011-01-04 17:45:13 -06002 * Copyright 2006, 2010-2011 Freescale Semiconductor.
Jon Loeliger5c9efb32006-04-27 10:15:16 -05003 *
Jon Loeligerdebb7352006-04-26 17:58:56 -05004 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
Jon Loeligerdebb7352006-04-26 17:58:56 -05007 */
8
9/*
Jon Loeliger5c9efb32006-04-27 10:15:16 -050010 * MPC8641HPCN board configuration file
Jon Loeligerdebb7352006-04-26 17:58:56 -050011 *
12 * Make sure you change the MAC address and other network params first,
Joe Hershberger92ac5202015-05-04 14:55:14 -050013 * search for CONFIG_SERVERIP, etc. in this file.
Jon Loeligerdebb7352006-04-26 17:58:56 -050014 */
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
19/* High Level Configuration Options */
Kumar Gala7649a592009-03-31 23:02:38 -050020#define CONFIG_MP 1 /* support multiple processors */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020021#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
Becky Bruced591a802009-02-03 18:10:54 -060022#define CONFIG_ADDR_MAP 1 /* Use addr map */
Jon Loeligerdebb7352006-04-26 17:58:56 -050023
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024/*
25 * default CCSRBAR is at 0xff700000
26 * assume U-Boot is less than 0.5MB
27 */
28#define CONFIG_SYS_TEXT_BASE 0xeff00000
29
Jon Loeligerdebb7352006-04-26 17:58:56 -050030#ifdef RUN_DIAG
Becky Bruce6bf98b12008-11-05 14:55:33 -060031#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
Jon Loeligerdebb7352006-04-26 17:58:56 -050032#endif
Jon Loeliger5c9efb32006-04-27 10:15:16 -050033
Becky Bruceaf5d1002008-10-31 17:14:14 -050034/*
Becky Bruce1266df82008-11-03 15:44:01 -060035 * virtual address to be used for temporary mappings. There
36 * should be 128k free at this VA.
37 */
38#define CONFIG_SYS_SCRATCH_VA 0xe0000000
39
Kumar Gala1b77ca82011-01-04 17:45:13 -060040#define CONFIG_SYS_SRIO
41#define CONFIG_SRIO1 /* SRIO port 1 */
Becky Bruceaf5d1002008-10-31 17:14:14 -050042
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040043#define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */
44#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */
Ed Swarthout63cec582007-08-02 14:09:49 -050045#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Kumar Gala8ba93f62008-10-21 18:06:15 -050046#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Jon Loeliger5c9efb32006-04-27 10:15:16 -050047
Wolfgang Denk53677ef2008-05-20 16:00:29 +020048#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeligerdebb7352006-04-26 17:58:56 -050049#define CONFIG_ENV_OVERWRITE
Jon Loeliger5c9efb32006-04-27 10:15:16 -050050
Peter Tyser4bbfd3e2010-10-07 22:32:48 -050051#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
Becky Bruce31d82672008-05-08 19:02:12 -050052#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
Becky Bruced591a802009-02-03 18:10:54 -060053#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */
Jon Loeligerdebb7352006-04-26 17:58:56 -050054
Wolfgang Denk53677ef2008-05-20 16:00:29 +020055#define CONFIG_ALTIVEC 1
Jon Loeligerdebb7352006-04-26 17:58:56 -050056
Jon Loeliger5c9efb32006-04-27 10:15:16 -050057/*
Jon Loeligerdebb7352006-04-26 17:58:56 -050058 * L2CR setup -- make sure this is right for your board!
59 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_L2
Jon Loeligerdebb7352006-04-26 17:58:56 -050061#define L2_INIT 0
62#define L2_ENABLE (L2CR_L2E)
63
64#ifndef CONFIG_SYS_CLK_FREQ
Ed Swarthout63cec582007-08-02 14:09:49 -050065#ifndef __ASSEMBLY__
66extern unsigned long get_board_sys_clk(unsigned long dummy);
67#endif
Wolfgang Denk53677ef2008-05-20 16:00:29 +020068#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
Jon Loeligerdebb7352006-04-26 17:58:56 -050069#endif
70
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
72#define CONFIG_SYS_MEMTEST_END 0x00400000
Jon Loeligerdebb7352006-04-26 17:58:56 -050073
Jon Loeligerdebb7352006-04-26 17:58:56 -050074/*
Becky Bruce3111d322008-11-06 17:37:35 -060075 * With the exception of PCI Memory and Rapid IO, most devices will simply
76 * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA
77 * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0.
78 */
79#ifdef CONFIG_PHYS_64BIT
Becky Bruce1605cc92011-10-03 19:10:51 -050080#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f
Becky Bruce3111d322008-11-06 17:37:35 -060081#else
Becky Bruce1605cc92011-10-03 19:10:51 -050082#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -060083#endif
84
85/*
Jon Loeligerdebb7352006-04-26 17:58:56 -050086 * Base addresses -- Note these are effective addresses where the
87 * actual resources get mapped (not physical addresses)
88 */
Becky Brucec759a012008-11-06 17:36:04 -060089#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Jon Loeligerdebb7352006-04-26 17:58:56 -050091
Becky Bruce3111d322008-11-06 17:37:35 -060092/* Physical addresses */
93#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Becky Bruce1605cc92011-10-03 19:10:51 -050094#define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH
95#define CONFIG_SYS_CCSRBAR_PHYS \
96 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
97 CONFIG_SYS_CCSRBAR_PHYS_HIGH)
Becky Bruce3111d322008-11-06 17:37:35 -060098
york076bff82010-07-02 22:25:52 +000099#define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */
100
Jon Loeligerdebb7352006-04-26 17:58:56 -0500101/*
102 * DDR Setup
103 */
Kumar Gala6a8e5692008-08-26 15:01:35 -0500104#undef CONFIG_FSL_DDR_INTERACTIVE
105#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
106#define CONFIG_DDR_SPD
107
108#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
109#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
112#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Becky Bruce1266df82008-11-03 15:44:01 -0600113#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
Jin Zhengxiongfcb28e72006-07-13 10:35:10 -0500114#define CONFIG_VERY_BIG_RAM
Jon Loeligerdebb7352006-04-26 17:58:56 -0500115
Kumar Gala6a8e5692008-08-26 15:01:35 -0500116#define CONFIG_DIMM_SLOTS_PER_CTLR 2
117#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500118
Kumar Gala6a8e5692008-08-26 15:01:35 -0500119/*
120 * I2C addresses of SPD EEPROMs
121 */
122#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
123#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */
124#define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */
125#define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500126
Kumar Gala6a8e5692008-08-26 15:01:35 -0500127/*
128 * These are used when DDR doesn't use SPD.
129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
131#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
132#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
133#define CONFIG_SYS_DDR_TIMING_3 0x00000000
134#define CONFIG_SYS_DDR_TIMING_0 0x00260802
135#define CONFIG_SYS_DDR_TIMING_1 0x39357322
136#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
137#define CONFIG_SYS_DDR_MODE_1 0x00480432
138#define CONFIG_SYS_DDR_MODE_2 0x00000000
139#define CONFIG_SYS_DDR_INTERVAL 0x06090100
140#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
141#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
142#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
143#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
144#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */
145#define CONFIG_SYS_DDR_CONTROL2 0x04400000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500146
Jon Loeligerad8f8682008-01-15 13:42:41 -0600147#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_I2C_EEPROM_NXID
Jean-Christophe PLAGNIOL-VILLARD32628c52008-08-30 23:54:58 +0200149#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
151#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500152
Becky Brucec759a012008-11-06 17:36:04 -0600153#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */
Becky Bruce1605cc92011-10-03 19:10:51 -0500154#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE
155#define CONFIG_SYS_FLASH_BASE_PHYS \
156 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
157 CONFIG_SYS_PHYS_ADDR_HIGH)
Becky Bruce3111d322008-11-06 17:37:35 -0600158
Becky Bruceb81b7732009-02-02 16:34:52 -0600159#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Jon Loeligerdebb7352006-04-26 17:58:56 -0500160
Becky Bruce3111d322008-11-06 17:37:35 -0600161#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
162 | 0x00001001) /* port size 16bit */
163#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500164
Becky Bruce3111d322008-11-06 17:37:35 -0600165#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
166 | 0x00001001) /* port size 16bit */
167#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500168
Becky Bruce3111d322008-11-06 17:37:35 -0600169#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
170 | 0x00000801) /* port size 8bit */
171#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500172
Becky Brucec759a012008-11-06 17:36:04 -0600173/*
174 * The LBC_BASE is the base of the region that contains the PIXIS and the CF.
175 * The PIXIS and CF by themselves aren't large enough to take up the 128k
176 * required for the smallest BAT mapping, so there's a 64k hole.
177 */
178#define CONFIG_SYS_LBC_BASE 0xffde0000
Becky Bruce1605cc92011-10-03 19:10:51 -0500179#define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500180
Kim Phillips7608d752007-08-21 17:00:17 -0500181#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Becky Brucec759a012008-11-06 17:36:04 -0600182#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
Becky Bruce1605cc92011-10-03 19:10:51 -0500183#define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000)
184#define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \
185 CONFIG_SYS_PHYS_ADDR_HIGH)
Becky Brucec759a012008-11-06 17:36:04 -0600186#define PIXIS_SIZE 0x00008000 /* 32k */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500187#define PIXIS_ID 0x0 /* Board ID at offset 0 */
188#define PIXIS_VER 0x1 /* Board version at offset 1 */
189#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
190#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
191#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */
192#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
193#define PIXIS_VCTL 0x10 /* VELA Control Register */
194#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
195#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
196#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Gala9af9c6b2009-07-15 13:45:00 -0500197#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
198#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500199#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
200#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
201#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
202#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
Jon Loeligerdebb7352006-04-26 17:58:56 -0500204
Becky Bruceb5431562008-10-31 17:13:49 -0500205/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */
Becky Brucec759a012008-11-06 17:36:04 -0600206#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
Becky Bruce3111d322008-11-06 17:37:35 -0600207#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
Becky Bruceb5431562008-10-31 17:13:49 -0500208
Becky Bruce170deac2008-11-05 14:55:32 -0600209#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#undef CONFIG_SYS_FLASH_CHECKSUM
213#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
214#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200215#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Becky Brucebf9a8c32008-11-05 14:55:35 -0600216#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500217
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200218#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_FLASH_CFI
220#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeligerdebb7352006-04-26 17:58:56 -0500221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
223#define CONFIG_SYS_RAMBOOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500224#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#undef CONFIG_SYS_RAMBOOT
Jon Loeligerdebb7352006-04-26 17:58:56 -0500226#endif
227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#if defined(CONFIG_SYS_RAMBOOT)
Jin Zhengxiong-R64188fa7db9c2006-06-27 18:11:54 +0800229#undef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_SDRAM_SIZE 256
Jon Loeligerdebb7352006-04-26 17:58:56 -0500231#endif
232
233#undef CONFIG_CLOCKS_IN_MHZ
234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_INIT_RAM_LOCK 1
236#ifndef CONFIG_SYS_INIT_RAM_LOCK
237#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500238#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500240#endif
Wolfgang Denk553f0982010-10-26 13:32:32 +0200241#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500242
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200243#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeligerdebb7352006-04-26 17:58:56 -0500245
Scott Wood221fbd22015-04-15 16:13:48 -0500246#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500248
249/* Serial Port */
250#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_NS16550_SERIAL
252#define CONFIG_SYS_NS16550_REG_SIZE 1
253#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeligerdebb7352006-04-26 17:58:56 -0500256 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
259#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500260
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500261/*
Jon Loeliger586d1d52006-05-19 13:22:44 -0500262 * I2C
263 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200264#define CONFIG_SYS_I2C
265#define CONFIG_SYS_I2C_FSL
266#define CONFIG_SYS_FSL_I2C_SPEED 400000
267#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
268#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100
269#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jon Loeligerdebb7352006-04-26 17:58:56 -0500270
Jon Loeliger586d1d52006-05-19 13:22:44 -0500271/*
272 * RapidIO MMU
273 */
Kumar Gala1b77ca82011-01-04 17:45:13 -0600274#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */
Becky Bruce3111d322008-11-06 17:37:35 -0600275#ifdef CONFIG_PHYS_64BIT
Becky Bruce1605cc92011-10-03 19:10:51 -0500276#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000
277#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c
Becky Bruce3111d322008-11-06 17:37:35 -0600278#else
Becky Bruce1605cc92011-10-03 19:10:51 -0500279#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE
280#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -0600281#endif
Becky Bruce1605cc92011-10-03 19:10:51 -0500282#define CONFIG_SYS_SRIO1_MEM_PHYS \
283 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
284 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH)
Kumar Gala1b77ca82011-01-04 17:45:13 -0600285#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500286
287/*
288 * General PCI
289 * Addresses are mapped 1-1.
290 */
Becky Bruce49f46f32009-02-03 18:10:53 -0600291
Kumar Gala64e55d52010-12-17 10:47:36 -0600292#define CONFIG_SYS_PCIE1_NAME "ULI"
Kumar Gala46f3e382010-07-09 00:02:34 -0500293#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
Becky Bruce3111d322008-11-06 17:37:35 -0600294#ifdef CONFIG_PHYS_64BIT
Kumar Gala46f3e382010-07-09 00:02:34 -0500295#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
Becky Bruce1605cc92011-10-03 19:10:51 -0500296#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000
297#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c
Becky Bruce3111d322008-11-06 17:37:35 -0600298#else
Kumar Gala46f3e382010-07-09 00:02:34 -0500299#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT
Becky Bruce1605cc92011-10-03 19:10:51 -0500300#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT
301#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000
Becky Bruce3111d322008-11-06 17:37:35 -0600302#endif
Becky Bruce1605cc92011-10-03 19:10:51 -0500303#define CONFIG_SYS_PCIE1_MEM_PHYS \
304 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
305 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH)
Kumar Gala46f3e382010-07-09 00:02:34 -0500306#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
307#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
308#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
Becky Bruce1605cc92011-10-03 19:10:51 -0500309#define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT
310#define CONFIG_SYS_PCIE1_IO_PHYS \
311 PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
312 CONFIG_SYS_PHYS_ADDR_HIGH)
Kumar Gala46f3e382010-07-09 00:02:34 -0500313#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500314
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600315#ifdef CONFIG_PHYS_64BIT
316/*
Kumar Gala46f3e382010-07-09 00:02:34 -0500317 * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT.
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600318 * This will increase the amount of PCI address space available for
319 * for mapping RAM.
320 */
Kumar Gala46f3e382010-07-09 00:02:34 -0500321#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600322#else
Kumar Gala46f3e382010-07-09 00:02:34 -0500323#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \
324 + CONFIG_SYS_PCIE1_MEM_SIZE)
Becky Bruce4c78d4a2009-02-03 18:10:56 -0600325#endif
Kumar Gala46f3e382010-07-09 00:02:34 -0500326#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \
327 + CONFIG_SYS_PCIE1_MEM_SIZE)
Becky Bruce1605cc92011-10-03 19:10:51 -0500328#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \
329 + CONFIG_SYS_PCIE1_MEM_SIZE)
330#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH
Kumar Gala46f3e382010-07-09 00:02:34 -0500331#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \
332 + CONFIG_SYS_PCIE1_MEM_SIZE)
333#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
334#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
335#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \
336 + CONFIG_SYS_PCIE1_IO_SIZE)
Becky Bruce1605cc92011-10-03 19:10:51 -0500337#define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \
338 + CONFIG_SYS_PCIE1_IO_SIZE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500339#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \
340 + CONFIG_SYS_PCIE1_IO_SIZE)
341#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE
Jon Loeligerdebb7352006-04-26 17:58:56 -0500342
Jon Loeligerdebb7352006-04-26 17:58:56 -0500343#if defined(CONFIG_PCI)
344
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200345#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500346
Jon Loeligerdebb7352006-04-26 17:58:56 -0500347#undef CONFIG_EEPRO100
348#undef CONFIG_TULIP
349
Zhang Weia81d1c02007-06-06 10:08:14 +0200350/************************************************************
351 * USB support
352 ************************************************************/
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200353#define CONFIG_PCI_OHCI 1
Zhang Weia81d1c02007-06-06 10:08:14 +0200354#define CONFIG_USB_OHCI_NEW 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_USB_EVENT_POLL 1
356#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
357#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
358#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Zhang Weia81d1c02007-06-06 10:08:14 +0200359
Jason Jin0f460a12007-07-13 12:14:58 +0800360/*PCIE video card used*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500361#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
Jason Jin0f460a12007-07-13 12:14:58 +0800362
363/*PCI video card used*/
Kumar Gala46f3e382010-07-09 00:02:34 -0500364/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/
Jason Jin0f460a12007-07-13 12:14:58 +0800365
366/* video */
Jason Jin0f460a12007-07-13 12:14:58 +0800367
368#if defined(CONFIG_VIDEO)
369#define CONFIG_BIOSEMU
Jason Jin0f460a12007-07-13 12:14:58 +0800370#define CONFIG_ATI_RADEON_FB
371#define CONFIG_VIDEO_LOGO
Kumar Gala46f3e382010-07-09 00:02:34 -0500372#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT
Jason Jin0f460a12007-07-13 12:14:58 +0800373#endif
374
Jon Loeligerdebb7352006-04-26 17:58:56 -0500375#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500376
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800377#define CONFIG_SCSI_AHCI
378
379#ifdef CONFIG_SCSI_AHCI
Rob Herring344ca0b2013-08-24 10:10:54 -0500380#define CONFIG_LIBATA
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800381#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
383#define CONFIG_SYS_SCSI_MAX_LUN 1
384#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
385#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jin Zhengxiongdabf9ef2006-08-23 19:15:12 +0800386#endif
387
Jon Loeligerdebb7352006-04-26 17:58:56 -0500388#endif /* CONFIG_PCI */
389
Jon Loeligerdebb7352006-04-26 17:58:56 -0500390#if defined(CONFIG_TSEC_ENET)
391
Jon Loeligerdebb7352006-04-26 17:58:56 -0500392#define CONFIG_MII 1 /* MII PHY management */
393
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200394#define CONFIG_TSEC1 1
395#define CONFIG_TSEC1_NAME "eTSEC1"
396#define CONFIG_TSEC2 1
397#define CONFIG_TSEC2_NAME "eTSEC2"
398#define CONFIG_TSEC3 1
399#define CONFIG_TSEC3_NAME "eTSEC3"
400#define CONFIG_TSEC4 1
401#define CONFIG_TSEC4_NAME "eTSEC4"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500402
Jon Loeligerdebb7352006-04-26 17:58:56 -0500403#define TSEC1_PHY_ADDR 0
404#define TSEC2_PHY_ADDR 1
405#define TSEC3_PHY_ADDR 2
406#define TSEC4_PHY_ADDR 3
407#define TSEC1_PHYIDX 0
408#define TSEC2_PHYIDX 0
409#define TSEC3_PHYIDX 0
410#define TSEC4_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500411#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
412#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
413#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
414#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500415
416#define CONFIG_ETHPRIME "eTSEC1"
417
418#endif /* CONFIG_TSEC_ENET */
419
Becky Bruce3111d322008-11-06 17:37:35 -0600420#ifdef CONFIG_PHYS_64BIT
Becky Bruce3111d322008-11-06 17:37:35 -0600421#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
422#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
423
Becky Bruce1605cc92011-10-03 19:10:51 -0500424/* Put physical address into the BAT format */
425#define BAT_PHYS_ADDR(low, high) \
426 (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high))
427/* Convert high/low pairs to actual 64-bit value */
428#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32))
429#else
430/* 32-bit systems just ignore the "high" bits */
431#define BAT_PHYS_ADDR(low, high) (low)
432#define PAIRED_PHYS_TO_PHYS(low, high) (low)
433#endif
434
Jon Loeliger586d1d52006-05-19 13:22:44 -0500435/*
Becky Brucec759a012008-11-06 17:36:04 -0600436 * BAT0 DDR
Jon Loeligerdebb7352006-04-26 17:58:56 -0500437 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
Timur Tabi9ff32d82010-03-29 12:51:07 -0500439#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500440
Jon Loeliger586d1d52006-05-19 13:22:44 -0500441/*
Becky Brucec759a012008-11-06 17:36:04 -0600442 * BAT1 LBC (PIXIS/CF)
Becky Bruceaf5d1002008-10-31 17:14:14 -0500443 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500444#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
445 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600446 | BATL_PP_RW | BATL_CACHEINHIBIT | \
447 BATL_GUARDEDSTORAGE)
Becky Brucec759a012008-11-06 17:36:04 -0600448#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
449 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500450#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \
451 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600452 | BATL_PP_RW | BATL_MEMCOHERENCE)
Becky Brucec759a012008-11-06 17:36:04 -0600453#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
Becky Bruceaf5d1002008-10-31 17:14:14 -0500454
455/* if CONFIG_PCI:
Kumar Gala46f3e382010-07-09 00:02:34 -0500456 * BAT2 PCIE1 and PCIE1 MEM
Becky Bruceaf5d1002008-10-31 17:14:14 -0500457 * if CONFIG_RIO
Becky Brucec759a012008-11-06 17:36:04 -0600458 * BAT2 Rapidio Memory
Jon Loeligerdebb7352006-04-26 17:58:56 -0500459 */
Becky Bruceaf5d1002008-10-31 17:14:14 -0500460#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000461#define CONFIG_PCI_INDIRECT_BRIDGE
Becky Bruce1605cc92011-10-03 19:10:51 -0500462#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
463 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600464 | BATL_PP_RW | BATL_CACHEINHIBIT \
465 | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500466#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \
Becky Bruceaf5d1002008-10-31 17:14:14 -0500467 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500468#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \
469 CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600470 | BATL_PP_RW | BATL_CACHEINHIBIT)
Becky Bruceaf5d1002008-10-31 17:14:14 -0500471#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
472#else /* CONFIG_RIO */
Becky Bruce1605cc92011-10-03 19:10:51 -0500473#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
474 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600475 | BATL_PP_RW | BATL_CACHEINHIBIT | \
476 BATL_GUARDEDSTORAGE)
Kumar Gala1b77ca82011-01-04 17:45:13 -0600477#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \
Becky Bruce3111d322008-11-06 17:37:35 -0600478 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500479#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \
480 CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600481 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
Becky Bruceaf5d1002008-10-31 17:14:14 -0500483#endif
Jon Loeligerdebb7352006-04-26 17:58:56 -0500484
Jon Loeliger586d1d52006-05-19 13:22:44 -0500485/*
Becky Brucec759a012008-11-06 17:36:04 -0600486 * BAT3 CCSR Space
Jon Loeligerdebb7352006-04-26 17:58:56 -0500487 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500488#define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
489 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600490 | BATL_PP_RW | BATL_CACHEINHIBIT \
491 | BATL_GUARDEDSTORAGE)
Becky Brucec759a012008-11-06 17:36:04 -0600492#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
493 | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500494#define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \
495 CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600496 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500498
Becky Bruce3111d322008-11-06 17:37:35 -0600499#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
500#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
501 | BATL_PP_RW | BATL_CACHEINHIBIT \
502 | BATL_GUARDEDSTORAGE)
503#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
504 | BATU_BL_1M | BATU_VS | BATU_VP)
505#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
506 | BATL_PP_RW | BATL_CACHEINHIBIT)
507#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
508#endif
509
Jon Loeliger586d1d52006-05-19 13:22:44 -0500510/*
Kumar Gala46f3e382010-07-09 00:02:34 -0500511 * BAT4 PCIE1_IO and PCIE2_IO
Jon Loeligerdebb7352006-04-26 17:58:56 -0500512 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500513#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
514 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600515 | BATL_PP_RW | BATL_CACHEINHIBIT \
516 | BATL_GUARDEDSTORAGE)
Kumar Gala46f3e382010-07-09 00:02:34 -0500517#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \
Becky Brucec759a012008-11-06 17:36:04 -0600518 | BATU_VS | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500519#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \
520 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600521 | BATL_PP_RW | BATL_CACHEINHIBIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200522#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500523
Jon Loeliger586d1d52006-05-19 13:22:44 -0500524/*
Becky Brucec759a012008-11-06 17:36:04 -0600525 * BAT5 Init RAM for stack in the CPU DCache (no backing memory)
Jon Loeligerdebb7352006-04-26 17:58:56 -0500526 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
528#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
529#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
530#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500531
Jon Loeliger586d1d52006-05-19 13:22:44 -0500532/*
Becky Brucec759a012008-11-06 17:36:04 -0600533 * BAT6 FLASH
Jon Loeligerdebb7352006-04-26 17:58:56 -0500534 */
Becky Bruce1605cc92011-10-03 19:10:51 -0500535#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
536 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600537 | BATL_PP_RW | BATL_CACHEINHIBIT \
538 | BATL_GUARDEDSTORAGE)
Becky Bruce170deac2008-11-05 14:55:32 -0600539#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
540 | BATU_VP)
Becky Bruce1605cc92011-10-03 19:10:51 -0500541#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \
542 CONFIG_SYS_PHYS_ADDR_HIGH) \
Becky Bruce3111d322008-11-06 17:37:35 -0600543 | BATL_PP_RW | BATL_MEMCOHERENCE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
Jon Loeligerdebb7352006-04-26 17:58:56 -0500545
Becky Brucebf9a8c32008-11-05 14:55:35 -0600546/* Map the last 1M of flash where we're running from reset */
547#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
548 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200549#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
Becky Brucebf9a8c32008-11-05 14:55:35 -0600550#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
551 | BATL_MEMCOHERENCE)
552#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
553
Becky Brucec759a012008-11-06 17:36:04 -0600554/*
555 * BAT7 FREE - used later for tmp mappings
556 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557#define CONFIG_SYS_DBAT7L 0x00000000
558#define CONFIG_SYS_DBAT7U 0x00000000
559#define CONFIG_SYS_IBAT7L 0x00000000
560#define CONFIG_SYS_IBAT7U 0x00000000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500561
Jon Loeligerdebb7352006-04-26 17:58:56 -0500562/*
563 * Environment
564 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200565#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200566 #define CONFIG_ENV_IS_IN_FLASH 1
Scott Wood221fbd22015-04-15 16:13:48 -0500567 #define CONFIG_ENV_ADDR \
568 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200569 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500570#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200571 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200572 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500573#endif
Becky Bruce0f2d6602008-11-05 14:55:31 -0600574#define CONFIG_ENV_SIZE 0x2000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500575
576#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200577#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500578
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500579/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500580 * BOOTP options
581 */
582#define CONFIG_BOOTP_BOOTFILESIZE
583#define CONFIG_BOOTP_BOOTPATH
584#define CONFIG_BOOTP_GATEWAY
585#define CONFIG_BOOTP_HOSTNAME
586
Jon Loeliger659e2f62007-07-10 09:10:49 -0500587/*
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500588 * Command line configuration.
589 */
Becky Bruce4f93f8b2008-01-23 16:31:06 -0600590#define CONFIG_CMD_REGINFO
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500591
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500592#if defined(CONFIG_PCI)
593 #define CONFIG_CMD_PCI
Simon Glassc649e3c2016-05-01 11:36:02 -0600594 #define CONFIG_SCSI
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500595#endif
596
Jon Loeligerdebb7352006-04-26 17:58:56 -0500597#undef CONFIG_WATCHDOG /* watchdog disabled */
598
599/*
600 * Miscellaneous configurable options
601 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200602#define CONFIG_SYS_LONGHELP /* undef to save memory */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200603#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200604#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500605
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500606#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500608#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200609 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500610#endif
611
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200612#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
613#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
614#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500615
616/*
617 * For booting Linux, the board info and command line data
618 * have to be in the first 8 MB of memory, since this is
619 * the maximum mapped by the Linux kernel during initialization.
620 */
Scott Woode1efe432016-07-19 17:51:55 -0500621#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
622#define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500623
Jon Loeliger2f9c19e2007-06-11 19:03:44 -0500624#if defined(CONFIG_CMD_KGDB)
625 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500626#endif
627
Jon Loeligerdebb7352006-04-26 17:58:56 -0500628/*
629 * Environment Configuration
630 */
631
Andy Fleming10327dc2007-08-16 16:35:02 -0500632#define CONFIG_HAS_ETH0 1
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500633#define CONFIG_HAS_ETH1 1
634#define CONFIG_HAS_ETH2 1
635#define CONFIG_HAS_ETH3 1
Jon Loeligerdebb7352006-04-26 17:58:56 -0500636
Jon Loeliger18b6c8c2006-05-09 08:23:49 -0500637#define CONFIG_IPADDR 192.168.1.100
Jon Loeligerdebb7352006-04-26 17:58:56 -0500638
639#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000640#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000641#define CONFIG_BOOTFILE "uImage"
Ed Swarthout32922cd2007-06-05 12:30:52 -0500642#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500643
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500644#define CONFIG_SERVERIP 192.168.1.1
Jon Loeliger18b6c8c2006-05-09 08:23:49 -0500645#define CONFIG_GATEWAYIP 192.168.1.1
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500646#define CONFIG_NETMASK 255.255.255.0
Jon Loeligerdebb7352006-04-26 17:58:56 -0500647
Jon Loeliger5c9efb32006-04-27 10:15:16 -0500648/* default location for tftp and bootm */
Scott Woode1efe432016-07-19 17:51:55 -0500649#define CONFIG_LOADADDR 0x10000000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500650
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200651#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Jon Loeligerdebb7352006-04-26 17:58:56 -0500652
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200653#define CONFIG_EXTRA_ENV_SETTINGS \
654 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200655 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200656 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200657 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
658 " +$filesize; " \
659 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
660 " +$filesize; " \
661 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
662 " $filesize; " \
663 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
664 " +$filesize; " \
665 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
666 " $filesize\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200667 "consoledev=ttyS0\0" \
Scott Woode1efe432016-07-19 17:51:55 -0500668 "ramdiskaddr=0x18000000\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200669 "ramdiskfile=your.ramdisk.u-boot\0" \
Scott Woode1efe432016-07-19 17:51:55 -0500670 "fdtaddr=0x17c00000\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200671 "fdtfile=mpc8641_hpcn.dtb\0" \
Becky Bruce3111d322008-11-06 17:37:35 -0600672 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
673 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200674 "maxcpus=2"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500675
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200676#define CONFIG_NFSBOOTCOMMAND \
677 "setenv bootargs root=/dev/nfs rw " \
678 "nfsroot=$serverip:$rootpath " \
679 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
680 "console=$consoledev,$baudrate $othbootargs;" \
681 "tftp $loadaddr $bootfile;" \
682 "tftp $fdtaddr $fdtfile;" \
683 "bootm $loadaddr - $fdtaddr"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500684
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200685#define CONFIG_RAMBOOTCOMMAND \
686 "setenv bootargs root=/dev/ram rw " \
687 "console=$consoledev,$baudrate $othbootargs;" \
688 "tftp $ramdiskaddr $ramdiskfile;" \
689 "tftp $loadaddr $bootfile;" \
690 "tftp $fdtaddr $fdtfile;" \
691 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeligerdebb7352006-04-26 17:58:56 -0500692
693#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
694
695#endif /* __CONFIG_H */