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Stelian Pop39cf4802008-05-09 21:57:18 +02001/*
2 * Driver for AT91/AT32 LCD Controller
3 *
4 * Copyright (C) 2007 Atmel Corporation
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
Stelian Pop39cf4802008-05-09 21:57:18 +02007 */
8
9#include <common.h>
10#include <asm/io.h>
Stelian Pop39cf4802008-05-09 21:57:18 +020011#include <asm/arch/gpio.h>
12#include <asm/arch/clk.h>
13#include <lcd.h>
Nikita Kiryanov0b29a892015-02-03 13:32:27 +020014#include <bmp_layout.h>
Stelian Pop39cf4802008-05-09 21:57:18 +020015#include <atmel_lcdc.h>
16
Stelian Pop39cf4802008-05-09 21:57:18 +020017/* configurable parameters */
18#define ATMEL_LCDC_CVAL_DEFAULT 0xc8
19#define ATMEL_LCDC_DMA_BURST_LEN 8
Mark Jackson6bbced62009-06-29 15:59:10 +010020#ifndef ATMEL_LCDC_GUARD_TIME
21#define ATMEL_LCDC_GUARD_TIME 1
22#endif
Stelian Pop39cf4802008-05-09 21:57:18 +020023
Bo Shenc6941e12015-01-16 10:55:46 +080024#if defined(CONFIG_AT91SAM9263)
Stelian Pop39cf4802008-05-09 21:57:18 +020025#define ATMEL_LCDC_FIFO_SIZE 2048
26#else
27#define ATMEL_LCDC_FIFO_SIZE 512
28#endif
29
30#define lcdc_readl(mmio, reg) __raw_readl((mmio)+(reg))
31#define lcdc_writel(mmio, reg, val) __raw_writel((val), (mmio)+(reg))
32
Nikita Kiryanov38b55082015-02-03 13:32:21 +020033ushort *configuration_get_cmap(void)
34{
35 return (ushort *)(panel_info.mmio + ATMEL_LCDC_LUT(0));
36}
37
Nikita Kiryanovb3d12e92015-02-03 13:32:22 +020038#if defined(CONFIG_BMP_16BPP) && defined(CONFIG_ATMEL_LCD_BGR555)
39void fb_put_word(uchar **fb, uchar **from)
40{
41 *(*fb)++ = (((*from)[0] & 0x1f) << 2) | ((*from)[1] & 0x03);
42 *(*fb)++ = ((*from)[0] & 0xe0) | (((*from)[1] & 0x7c) >> 2);
43 *from += 2;
44}
45#endif
46
Nikita Kiryanova02e9482015-02-03 13:32:24 +020047#ifdef CONFIG_LCD_LOGO
48#include <bmp_logo.h>
49void lcd_logo_set_cmap(void)
50{
51 int i;
52 uint lut_entry;
53 ushort colreg;
54 uint *cmap = (uint *)configuration_get_cmap();
55
56 for (i = 0; i < BMP_LOGO_COLORS; ++i) {
57 colreg = bmp_logo_palette[i];
58#ifdef CONFIG_ATMEL_LCD_BGR555
59 lut_entry = ((colreg & 0x000F) << 11) |
60 ((colreg & 0x00F0) << 2) |
61 ((colreg & 0x0F00) >> 7);
62#else
63 lut_entry = ((colreg & 0x000F) << 1) |
64 ((colreg & 0x00F0) << 3) |
65 ((colreg & 0x0F00) << 4);
66#endif
67 *(cmap + BMP_LOGO_OFFSET) = lut_entry;
68 cmap++;
69 }
70}
71#endif
72
Stelian Pop39cf4802008-05-09 21:57:18 +020073void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
74{
75#if defined(CONFIG_ATMEL_LCD_BGR555)
76 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
77 (red >> 3) | ((green & 0xf8) << 2) | ((blue & 0xf8) << 7));
78#else
79 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LUT(regno),
80 (blue >> 3) | ((green & 0xfc) << 3) | ((red & 0xf8) << 8));
81#endif
82}
83
Simon Glass1c3dbe52015-05-13 07:02:27 -060084void lcd_set_cmap(struct bmp_image *bmp, unsigned colors)
Nikita Kiryanov0b29a892015-02-03 13:32:27 +020085{
86 int i;
87
88 for (i = 0; i < colors; ++i) {
Simon Glass1c3dbe52015-05-13 07:02:27 -060089 struct bmp_color_table_entry cte = bmp->color_table[i];
Nikita Kiryanov0b29a892015-02-03 13:32:27 +020090 lcd_setcolreg(i, cte.red, cte.green, cte.blue);
91 }
92}
93
Stelian Pop39cf4802008-05-09 21:57:18 +020094void lcd_ctrl_init(void *lcdbase)
95{
96 unsigned long value;
97
98 /* Turn off the LCD controller and the DMA controller */
99 lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
Mark Jackson6bbced62009-06-29 15:59:10 +0100100 ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET);
Stelian Pop39cf4802008-05-09 21:57:18 +0200101
102 /* Wait for the LCDC core to become idle */
103 while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY)
104 udelay(10);
105
106 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, 0);
107
108 /* Reset LCDC DMA */
109 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMARST);
110
111 /* ...set frame size and burst length = 8 words (?) */
112 value = (panel_info.vl_col * panel_info.vl_row *
113 NBITS(panel_info.vl_bpix)) / 32;
114 value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);
115 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMAFRMCFG, value);
116
117 /* Set pixel clock */
118 value = get_lcdc_clk_rate(0) / panel_info.vl_clk;
119 if (get_lcdc_clk_rate(0) % panel_info.vl_clk)
120 value++;
121 value = (value / 2) - 1;
122
123 if (!value) {
124 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS);
125 } else
126 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON1,
127 value << ATMEL_LCDC_CLKVAL_OFFSET);
128
129 /* Initialize control register 2 */
Stefan Roesef2302d42008-08-06 14:05:38 +0200130#ifdef CONFIG_AVR32
131 value = ATMEL_LCDC_MEMOR_BIG | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
132#else
Stelian Pop39cf4802008-05-09 21:57:18 +0200133 value = ATMEL_LCDC_MEMOR_LITTLE | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE;
Stefan Roesef2302d42008-08-06 14:05:38 +0200134#endif
Stelian Pop39cf4802008-05-09 21:57:18 +0200135 if (panel_info.vl_tft)
136 value |= ATMEL_LCDC_DISTYPE_TFT;
137
Haavard Skinnemoen70dbc542008-09-01 16:21:19 +0200138 value |= panel_info.vl_sync;
Stelian Pop39cf4802008-05-09 21:57:18 +0200139 value |= (panel_info.vl_bpix << 5);
140 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value);
141
142 /* Vertical timing */
143 value = (panel_info.vl_vsync_len - 1) << ATMEL_LCDC_VPW_OFFSET;
144 value |= panel_info.vl_upper_margin << ATMEL_LCDC_VBP_OFFSET;
145 value |= panel_info.vl_lower_margin;
146 lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM1, value);
147
148 /* Horizontal timing */
149 value = (panel_info.vl_right_margin - 1) << ATMEL_LCDC_HFP_OFFSET;
150 value |= (panel_info.vl_hsync_len - 1) << ATMEL_LCDC_HPW_OFFSET;
151 value |= (panel_info.vl_left_margin - 1);
152 lcdc_writel(panel_info.mmio, ATMEL_LCDC_TIM2, value);
153
154 /* Display size */
155 value = (panel_info.vl_col - 1) << ATMEL_LCDC_HOZVAL_OFFSET;
156 value |= panel_info.vl_row - 1;
157 lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDFRMCFG, value);
158
159 /* FIFO Threshold: Use formula from data sheet */
160 value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);
161 lcdc_writel(panel_info.mmio, ATMEL_LCDC_FIFO, value);
162
163 /* Toggle LCD_MODE every frame */
164 lcdc_writel(panel_info.mmio, ATMEL_LCDC_MVAL, 0);
165
166 /* Disable all interrupts */
167 lcdc_writel(panel_info.mmio, ATMEL_LCDC_IDR, ~0UL);
168
169 /* Set contrast */
170 value = ATMEL_LCDC_PS_DIV8 |
Stelian Pop39cf4802008-05-09 21:57:18 +0200171 ATMEL_LCDC_ENA_PWMENABLE;
Alexander Steincdfcedb2010-07-20 08:55:40 +0200172 if (!panel_info.vl_cont_pol_low)
173 value |= ATMEL_LCDC_POL_POSITIVE;
Stelian Pop39cf4802008-05-09 21:57:18 +0200174 lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_CTR, value);
175 lcdc_writel(panel_info.mmio, ATMEL_LCDC_CONTRAST_VAL, ATMEL_LCDC_CVAL_DEFAULT);
176
177 /* Set framebuffer DMA base address and pixel offset */
178 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMABADDR1, (u_long)lcdbase);
179
180 lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN);
181 lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON,
Mark Jackson6bbced62009-06-29 15:59:10 +0100182 (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR);
Stelian Pop39cf4802008-05-09 21:57:18 +0200183}
184
185ulong calc_fbsize(void)
186{
187 return ((panel_info.vl_col * panel_info.vl_row *
188 NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
189}