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wdenk0f8c9762002-08-19 11:57:05 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk0f8c9762002-08-19 11:57:05 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#undef CFG_RAMBOOT
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
39#define CONFIG_PM826 1 /* ...on a PM8260 module */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050040#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk0f8c9762002-08-19 11:57:05 +000041
wdenkaacf9a42003-01-17 16:27:01 +000042#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */
43
wdenk0f8c9762002-08-19 11:57:05 +000044#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
45
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010046#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenk0f8c9762002-08-19 11:57:05 +000047
48#undef CONFIG_BOOTARGS
49#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020050 "bootp; " \
51 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
52 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk0f8c9762002-08-19 11:57:05 +000053 "bootm"
54
55/* enable I2C and select the hardware/software driver */
56#undef CONFIG_HARD_I2C
57#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
58# define CFG_I2C_SPEED 50000
59# define CFG_I2C_SLAVE 0xFE
60/*
61 * Software (bit-bang) I2C driver configuration
62 */
63#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
64#define I2C_ACTIVE (iop->pdir |= 0x00010000)
65#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
66#define I2C_READ ((iop->pdat & 0x00010000) != 0)
67#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
68 else iop->pdat &= ~0x00010000
69#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
70 else iop->pdat &= ~0x00020000
71#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
72
73
74#define CONFIG_RTC_PCF8563
75#define CFG_I2C_RTC_ADDR 0x51
76
77/*
78 * select serial console configuration
79 *
80 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
81 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
82 * for SCC).
83 *
84 * if CONFIG_CONS_NONE is defined, then the serial console routines must
85 * defined elsewhere (for example, on the cogent platform, there are serial
86 * ports on the motherboard which are used for the serial console - see
87 * cogent/cma101/serial.[ch]).
88 */
89#define CONFIG_CONS_ON_SMC /* define if console on SMC */
90#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
91#undef CONFIG_CONS_NONE /* define if console on something else*/
92#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
93
94/*
95 * select ethernet configuration
96 *
wdenkaacf9a42003-01-17 16:27:01 +000097 * if CONFIG_ETHER_ON_SCC is selected, then
98 * - CONFIG_ETHER_INDEX must be set to the channel number (1-4)
99 * - CONFIG_NET_MULTI must not be defined
100 *
101 * if CONFIG_ETHER_ON_FCC is selected, then
102 * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected
103 * - CONFIG_NET_MULTI must be defined
wdenk0f8c9762002-08-19 11:57:05 +0000104 *
105 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500106 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk0f8c9762002-08-19 11:57:05 +0000107 */
wdenkaacf9a42003-01-17 16:27:01 +0000108#define CONFIG_NET_MULTI
wdenk0f8c9762002-08-19 11:57:05 +0000109#undef CONFIG_ETHER_NONE /* define if ether on something else */
wdenk0f8c9762002-08-19 11:57:05 +0000110
wdenkaacf9a42003-01-17 16:27:01 +0000111#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
112#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */
113
114#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
wdenk0f8c9762002-08-19 11:57:05 +0000115/*
116 * - Rx-CLK is CLK11
117 * - Tx-CLK is CLK10
wdenkaacf9a42003-01-17 16:27:01 +0000118 */
119#define CONFIG_ETHER_ON_FCC1
120# define CFG_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
121#ifndef CONFIG_DB_CR826_J30x_ON
122# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10)
123#else
124# define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
125#endif
126/*
127 * - Rx-CLK is CLK15
128 * - Tx-CLK is CLK14
129 */
130#define CONFIG_ETHER_ON_FCC2
131# define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
132# define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
133/*
wdenk0f8c9762002-08-19 11:57:05 +0000134 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
135 * - Enable Full Duplex in FSMR
136 */
wdenk0f8c9762002-08-19 11:57:05 +0000137# define CFG_CPMFCR_RAMTYPE 0
138# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
139
wdenk0f8c9762002-08-19 11:57:05 +0000140/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
141#define CONFIG_8260_CLKIN 64000000 /* in Hz */
142
143#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
144#define CONFIG_BAUDRATE 230400
145#else
146#define CONFIG_BAUDRATE 9600
147#endif
148
149#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
150#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
151
152#undef CONFIG_WATCHDOG /* watchdog disabled */
153
Jon Loeliger18225e82007-07-09 21:31:24 -0500154/*
155 * BOOTP options
156 */
157#define CONFIG_BOOTP_SUBNETMASK
158#define CONFIG_BOOTP_GATEWAY
159#define CONFIG_BOOTP_HOSTNAME
160#define CONFIG_BOOTP_BOOTPATH
161#define CONFIG_BOOTP_BOOTFILESIZE
wdenk0f8c9762002-08-19 11:57:05 +0000162
wdenk0f8c9762002-08-19 11:57:05 +0000163
Jon Loeligeracf02692007-07-08 14:49:44 -0500164/*
165 * Command line configuration.
166 */
167#include <config_cmd_default.h>
168
169#define CONFIG_CMD_BEDBUG
170#define CONFIG_CMD_DATE
171#define CONFIG_CMD_DHCP
172#define CONFIG_CMD_DOC
173#define CONFIG_CMD_EEPROM
174#define CONFIG_CMD_I2C
175#define CONFIG_CMD_NFS
176#define CONFIG_CMD_SNTP
177
178#ifdef CONFIG_PCI
179#define CONFIG_CMD_PCI
180#endif
181
wdenk0f8c9762002-08-19 11:57:05 +0000182
Jean-Christophe PLAGNIOL-VILLARDcc4a0ce2008-08-13 01:40:43 +0200183#define CONFIG_NAND_LEGACY
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100184
wdenk0f8c9762002-08-19 11:57:05 +0000185/*
186 * Disk-On-Chip configuration
187 */
188
189#define CFG_DOC_SHORT_TIMEOUT
190#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
191
192#define CFG_DOC_SUPPORT_2000
193#define CFG_DOC_SUPPORT_MILLENNIUM
194
195/*
196 * Miscellaneous configurable options
197 */
198#define CFG_LONGHELP /* undef to save memory */
199#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligeracf02692007-07-08 14:49:44 -0500200#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000201#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
202#else
203#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
204#endif
205#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
206#define CFG_MAXARGS 16 /* max number of command args */
207#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
208
209#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
210#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
211
212#define CFG_LOAD_ADDR 0x100000 /* default load address */
213
214#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
215
216#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
217
wdenkac6dbb82003-03-26 11:42:53 +0000218#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
wdenk0f8c9762002-08-19 11:57:05 +0000219
220/*
221 * For booting Linux, the board info and command line data
222 * have to be in the first 8 MB of memory, since this is
223 * the maximum mapped by the Linux kernel during initialization.
224 */
225#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
226
227/*-----------------------------------------------------------------------
228 * Flash and Boot ROM mapping
229 */
wdenkefa329c2004-03-23 20:18:25 +0000230#ifdef CONFIG_FLASH_32MB
231#define CFG_FLASH0_BASE 0x40000000
232#define CFG_FLASH0_SIZE 0x02000000
233#else
234#define CFG_FLASH0_BASE 0xFF000000
235#define CFG_FLASH0_SIZE 0x00800000
236#endif
wdenk3bac3512003-03-12 10:41:04 +0000237#define CFG_BOOTROM_BASE 0xFF800000
wdenk0f8c9762002-08-19 11:57:05 +0000238#define CFG_BOOTROM_SIZE 0x00080000
wdenk3bac3512003-03-12 10:41:04 +0000239#define CFG_DOC_BASE 0xFF800000
wdenk0f8c9762002-08-19 11:57:05 +0000240#define CFG_DOC_SIZE 0x00100000
241
wdenk0f8c9762002-08-19 11:57:05 +0000242/* Flash bank size (for preliminary settings)
243 */
244#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
245
246/*-----------------------------------------------------------------------
247 * FLASH organization
248 */
249#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
wdenkefa329c2004-03-23 20:18:25 +0000250#ifdef CONFIG_FLASH_32MB
251#define CFG_MAX_FLASH_SECT 135 /* max num of sects on one chip */
252#else
wdenk0f8c9762002-08-19 11:57:05 +0000253#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
wdenkefa329c2004-03-23 20:18:25 +0000254#endif
wdenk0f8c9762002-08-19 11:57:05 +0000255#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
256#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
257
258#if 0
259/* Start port with environment in flash; switch to EEPROM later */
260#define CFG_ENV_IS_IN_FLASH 1
261#define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000)
262#define CFG_ENV_SIZE 0x40000
263#define CFG_ENV_SECT_SIZE 0x40000
264#else
265/* Final version: environment in EEPROM */
266#define CFG_ENV_IS_IN_EEPROM 1
267#define CFG_I2C_EEPROM_ADDR 0x58
268#define CFG_I2C_EEPROM_ADDR_LEN 1
269#define CFG_EEPROM_PAGE_WRITE_BITS 4
270#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk3bac3512003-03-12 10:41:04 +0000271#define CFG_ENV_OFFSET 512
272#define CFG_ENV_SIZE (2048 - 512)
wdenk0f8c9762002-08-19 11:57:05 +0000273#endif
274
275/*-----------------------------------------------------------------------
276 * Hard Reset Configuration Words
277 *
278 * if you change bits in the HRCW, you must also change the CFG_*
279 * defines for the various registers affected by the HRCW e.g. changing
280 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
281 */
282#if defined(CONFIG_BOOT_ROM)
283#define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
284#else
285#define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS)
286#endif
287
288/* no slaves so just fill with zeros */
289#define CFG_HRCW_SLAVE1 0
290#define CFG_HRCW_SLAVE2 0
291#define CFG_HRCW_SLAVE3 0
292#define CFG_HRCW_SLAVE4 0
293#define CFG_HRCW_SLAVE5 0
294#define CFG_HRCW_SLAVE6 0
295#define CFG_HRCW_SLAVE7 0
296
297/*-----------------------------------------------------------------------
298 * Internal Memory Mapped Register
299 */
300#define CFG_IMMR 0xF0000000
301
302/*-----------------------------------------------------------------------
303 * Definitions for initial stack pointer and data area (in DPRAM)
304 */
305#define CFG_INIT_RAM_ADDR CFG_IMMR
306#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
307#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
308#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
309#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
310
311/*-----------------------------------------------------------------------
312 * Start addresses for the final memory configuration
313 * (Set up by the startup code)
314 * Please note that CFG_SDRAM_BASE _must_ start at 0
315 *
316 * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM
317 * is mapped at SDRAM_BASE2_PRELIM.
318 */
319#define CFG_SDRAM_BASE 0x00000000
320#define CFG_FLASH_BASE CFG_FLASH0_BASE
321#define CFG_MONITOR_BASE TEXT_BASE
322#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
323#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
324
325#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
326# define CFG_RAMBOOT
327#endif
328
wdenk10f67012003-03-25 18:06:06 +0000329#ifdef CONFIG_PCI
wdenk4d75a502003-03-25 16:50:56 +0000330#define CONFIG_PCI_PNP
331#define CONFIG_EEPRO100
stroese53cf9432003-06-05 15:39:44 +0000332#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk10f67012003-03-25 18:06:06 +0000333#endif
wdenk4d75a502003-03-25 16:50:56 +0000334
wdenk0f8c9762002-08-19 11:57:05 +0000335/*
336 * Internal Definitions
337 *
338 * Boot Flags
339 */
340#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
341#define BOOTFLAG_WARM 0x02 /* Software reboot */
342
343
344/*-----------------------------------------------------------------------
345 * Cache Configuration
346 */
347#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeligeracf02692007-07-08 14:49:44 -0500348#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000349# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
350#endif
351
352/*-----------------------------------------------------------------------
353 * HIDx - Hardware Implementation-dependent Registers 2-11
354 *-----------------------------------------------------------------------
355 * HID0 also contains cache control - initially enable both caches and
356 * invalidate contents, then the final state leaves only the instruction
357 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
358 * but Soft reset does not.
359 *
360 * HID1 has only read-only information - nothing to set.
361 */
362#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
wdenk8bde7f72003-06-27 21:31:46 +0000363 HID0_IFEM|HID0_ABE)
wdenk0f8c9762002-08-19 11:57:05 +0000364#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
365#define CFG_HID2 0
366
367/*-----------------------------------------------------------------------
368 * RMR - Reset Mode Register 5-5
369 *-----------------------------------------------------------------------
370 * turn on Checkstop Reset Enable
371 */
372#define CFG_RMR RMR_CSRE
373
374/*-----------------------------------------------------------------------
375 * BCR - Bus Configuration 4-25
376 *-----------------------------------------------------------------------
377 */
378
379#define BCR_APD01 0x10000000
380#define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
381
382/*-----------------------------------------------------------------------
383 * SIUMCR - SIU Module Configuration 4-31
384 *-----------------------------------------------------------------------
385 */
386#if 0
387#define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01)
388#else
389#define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
390#endif
391
392
393/*-----------------------------------------------------------------------
394 * SYPCR - System Protection Control 4-35
395 * SYPCR can only be written once after reset!
396 *-----------------------------------------------------------------------
397 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
398 */
399#if defined(CONFIG_WATCHDOG)
400#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000401 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
wdenk0f8c9762002-08-19 11:57:05 +0000402#else
403#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000404 SYPCR_SWRI|SYPCR_SWP)
wdenk0f8c9762002-08-19 11:57:05 +0000405#endif /* CONFIG_WATCHDOG */
406
407/*-----------------------------------------------------------------------
408 * TMCNTSC - Time Counter Status and Control 4-40
409 *-----------------------------------------------------------------------
410 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
411 * and enable Time Counter
412 */
413#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
414
415/*-----------------------------------------------------------------------
416 * PISCR - Periodic Interrupt Status and Control 4-42
417 *-----------------------------------------------------------------------
418 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
419 * Periodic timer
420 */
421#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
422
423/*-----------------------------------------------------------------------
424 * SCCR - System Clock Control 9-8
425 *-----------------------------------------------------------------------
426 */
wdenk7152b1d2003-09-05 23:19:14 +0000427#define CFG_SCCR (SCCR_DFBRG00)
wdenk0f8c9762002-08-19 11:57:05 +0000428
429/*-----------------------------------------------------------------------
430 * RCCR - RISC Controller Configuration 13-7
431 *-----------------------------------------------------------------------
432 */
433#define CFG_RCCR 0
434
435/*
436 * Init Memory Controller:
437 *
438 * Bank Bus Machine PortSz Device
439 * ---- --- ------- ------ ------
440 * 0 60x GPCM 64 bit FLASH
441 * 1 60x SDRAM 64 bit SDRAM
wdenk0f8c9762002-08-19 11:57:05 +0000442 *
443 */
444
445 /* Initialize SDRAM on local bus
446 */
447#define CFG_INIT_LOCAL_SDRAM
448
449
450/* Minimum mask to separate preliminary
451 * address ranges for CS[0:2]
452 */
453#define CFG_MIN_AM_MASK 0xC0000000
454
wdenkefa329c2004-03-23 20:18:25 +0000455/*
456 * we use the same values for 32 MB and 128 MB SDRAM
457 * refresh rate = 7.73 uS (64 MHz Bus Clock)
458 */
459#define CFG_MPTPR 0x2000
460#define CFG_PSRT 0x0E
wdenk0f8c9762002-08-19 11:57:05 +0000461
462#define CFG_MRS_OFFS 0x00000000
463
464
465#if defined(CONFIG_BOOT_ROM)
466/*
467 * Bank 0 - Boot ROM (8 bit wide)
468 */
469#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
470 BRx_PS_8 |\
471 BRx_MS_GPCM_P |\
472 BRx_V)
473
474#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
475 ORxG_CSNT |\
476 ORxG_ACS_DIV1 |\
477 ORxG_SCY_3_CLK |\
478 ORxG_EHTR |\
479 ORxG_TRLX)
480
481/*
482 * Bank 1 - Flash (64 bit wide)
483 */
484#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
485 BRx_PS_64 |\
486 BRx_MS_GPCM_P |\
487 BRx_V)
488
489#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
490 ORxG_CSNT |\
491 ORxG_ACS_DIV1 |\
492 ORxG_SCY_3_CLK |\
493 ORxG_EHTR |\
494 ORxG_TRLX)
495
496#else /* ! CONFIG_BOOT_ROM */
497
498/*
499 * Bank 0 - Flash (64 bit wide)
500 */
501#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000502 BRx_PS_64 |\
503 BRx_MS_GPCM_P |\
504 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000505
506#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000507 ORxG_CSNT |\
508 ORxG_ACS_DIV1 |\
509 ORxG_SCY_3_CLK |\
510 ORxG_EHTR |\
511 ORxG_TRLX)
wdenk0f8c9762002-08-19 11:57:05 +0000512
513/*
514 * Bank 1 - Disk-On-Chip
515 */
516#define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
517 BRx_PS_8 |\
518 BRx_MS_GPCM_P |\
519 BRx_V)
520
521#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
522 ORxG_CSNT |\
523 ORxG_ACS_DIV1 |\
524 ORxG_SCY_3_CLK |\
525 ORxG_EHTR |\
526 ORxG_TRLX)
527
528#endif /* CONFIG_BOOT_ROM */
529
530/* Bank 2 - SDRAM
531 */
wdenkefa329c2004-03-23 20:18:25 +0000532
wdenk0f8c9762002-08-19 11:57:05 +0000533#ifndef CFG_RAMBOOT
534#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000535 BRx_PS_64 |\
536 BRx_MS_SDRAM_P |\
537 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000538
539 /* SDRAM initialization values for 8-column chips
540 */
541#define CFG_OR2_8COL (CFG_MIN_AM_MASK |\
wdenk8bde7f72003-06-27 21:31:46 +0000542 ORxS_BPD_4 |\
543 ORxS_ROWST_PBI0_A9 |\
544 ORxS_NUMR_12)
wdenk0f8c9762002-08-19 11:57:05 +0000545
546#define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
wdenk8bde7f72003-06-27 21:31:46 +0000547 PSDMR_BSMA_A14_A16 |\
548 PSDMR_SDA10_PBI0_A10 |\
549 PSDMR_RFRC_7_CLK |\
550 PSDMR_PRETOACT_2W |\
551 PSDMR_ACTTORW_1W |\
552 PSDMR_LDOTOPRE_1C |\
553 PSDMR_WRC_1C |\
554 PSDMR_CL_2)
wdenk0f8c9762002-08-19 11:57:05 +0000555
556 /* SDRAM initialization values for 9-column chips
557 */
558#define CFG_OR2_9COL (CFG_MIN_AM_MASK |\
wdenk8bde7f72003-06-27 21:31:46 +0000559 ORxS_BPD_4 |\
560 ORxS_ROWST_PBI0_A7 |\
561 ORxS_NUMR_13)
wdenk0f8c9762002-08-19 11:57:05 +0000562
563#define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
wdenk8bde7f72003-06-27 21:31:46 +0000564 PSDMR_BSMA_A13_A15 |\
565 PSDMR_SDA10_PBI0_A9 |\
566 PSDMR_RFRC_7_CLK |\
567 PSDMR_PRETOACT_2W |\
568 PSDMR_ACTTORW_1W |\
569 PSDMR_LDOTOPRE_1C |\
570 PSDMR_WRC_1C |\
571 PSDMR_CL_2)
wdenk0f8c9762002-08-19 11:57:05 +0000572
573#define CFG_OR2_PRELIM CFG_OR2_9COL
574#define CFG_PSDMR CFG_PSDMR_9COL
575
576#endif /* CFG_RAMBOOT */
577
578#endif /* __CONFIG_H */