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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d574c19b89549964b2cc30e3e542109cfc22466b / . / drivers / ddr / fsl / Kconfig
blob: 1b73df82debc1dc47658dce9616537b68c5b8dc8 [file] [log] [blame]
York Sund26e34c2016-12-28 08:43:40 -0800[diff] [blame]1config SYS_FSL_DDR
2 bool
3 help
4 Select Freescale General DDR driver, shared between most Freescale
5 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
6 based Layerscape SoCs (such as ls2080a).
7
8config SYS_FSL_MMDC
9 bool
10 help
11 Select Freescale Multi Mode DDR controller (MMDC).
12
13config SYS_FSL_DDR_BE
14 bool
15 help
16 Access DDR registers in big-endian
17
18config SYS_FSL_DDR_LE
19 bool
20 help
21 Access DDR registers in little-endian
22
Rajesh Bhagat32413122019-02-01 05:22:01 +0000[diff] [blame]23config FSL_DDR_BIST
24 bool
25
26config FSL_DDR_INTERACTIVE
27 bool
28
29config FSL_DDR_SYNC_REFRESH
30 bool
31
32config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
33 bool
34
York Sund26e34c2016-12-28 08:43:40 -0800[diff] [blame]35menu "Freescale DDR controllers"
36 depends on SYS_FSL_DDR
37
York Sun51370d52016-12-28 08:43:45 -0800[diff] [blame]38config SYS_NUM_DDR_CTLRS
York Sun66e399b2016-12-28 08:43:44 -0800[diff] [blame]39 int "Maximum DDR controllers"
40 default 3 if ARCH_LS2080A || \
41 ARCH_T4240
42 default 2 if ARCH_B4860 || \
43 ARCH_BSC9132 || \
44 ARCH_MPC8572 || \
45 ARCH_MPC8641 || \
46 ARCH_P4080 || \
47 ARCH_P5020 || \
48 ARCH_P5040 || \
Priyanka Jain4909b892018-10-29 09:17:09 +0000[diff] [blame]49 ARCH_LX2160A || \
York Sun66e399b2016-12-28 08:43:44 -0800[diff] [blame]50 ARCH_T4160
51 default 1
52
York Sund26e34c2016-12-28 08:43:40 -0800[diff] [blame]53config SYS_FSL_DDR_VER
54 int
55 default 50 if SYS_FSL_DDR_VER_50
56 default 47 if SYS_FSL_DDR_VER_47
57 default 46 if SYS_FSL_DDR_VER_46
58 default 44 if SYS_FSL_DDR_VER_44
59
60config SYS_FSL_DDR_VER_50
61 bool
62
63config SYS_FSL_DDR_VER_47
64 bool
65
66config SYS_FSL_DDR_VER_46
67 bool
68
69config SYS_FSL_DDR_VER_44
70 bool
71
72config SYS_FSL_DDRC_GEN1
73 bool
74 help
75 Enable Freescale DDR controller.
76
77config SYS_FSL_DDRC_GEN2
78 bool
79 depends on !MPC86xx
80 help
81 Enable Freescale DDR2 controller.
82
83config SYS_FSL_DDRC_86XX_GEN2
84 bool
85 depends on MPC86xx
86 help
87 Enable Freescale DDR2 controller for MPC86xx SoCs.
88
89config SYS_FSL_DDRC_GEN3
90 bool
91 depends on PPC
92 help
93 Enable Freescale DDR3 controller for PowerPC SoCs.
94
95config SYS_FSL_DDRC_ARM_GEN3
96 bool
97 depends on ARM
98 help
99 Enable Freescale DDR3 controller for ARM SoCs.
100
101config SYS_FSL_DDRC_GEN4
102 bool
103 help
104 Enable Freescale DDR4 controller.
105
106config SYS_FSL_HAS_DDR4
107 bool
108
109config SYS_FSL_HAS_DDR3
110 bool
111
112config SYS_FSL_HAS_DDR2
113 bool
114
115config SYS_FSL_HAS_DDR1
116 bool
117
118choice
119 prompt "DDR technology"
120 default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4
121 default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3
122 default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2
123 default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1
124
125config SYS_FSL_DDR4
126 bool "Freescale DDR4 controller"
127 depends on SYS_FSL_HAS_DDR4
128 select SYS_FSL_DDRC_GEN4
129
130config SYS_FSL_DDR3
131 bool "Freescale DDR3 controller"
132 depends on SYS_FSL_HAS_DDR3
133 select SYS_FSL_DDRC_GEN3 if PPC
134 select SYS_FSL_DDRC_ARM_GEN3 if ARM
135
136config SYS_FSL_DDR2
137 bool "Freescale DDR2 controller"
138 depends on SYS_FSL_HAS_DDR2
139 select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3)
140 select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx
141
142config SYS_FSL_DDR1
143 bool "Freescale DDR1 controller"
144 depends on SYS_FSL_HAS_DDR1
145 select SYS_FSL_DDRC_GEN1
146
147endchoice
148
149endmenu
York Sunba1b6fb2016-12-28 08:43:41 -0800[diff] [blame]150
151config SYS_FSL_ERRATUM_A008378
152 bool
153
154config SYS_FSL_ERRATUM_A008511
155 bool
156
157config SYS_FSL_ERRATUM_A009663
158 bool
159
160config SYS_FSL_ERRATUM_A009801
161 bool
162
163config SYS_FSL_ERRATUM_A009803
164 bool
165
166config SYS_FSL_ERRATUM_A009942
167 bool
168
169config SYS_FSL_ERRATUM_A010165
170 bool
York Sun63659ff2016-12-28 08:43:43 -0800[diff] [blame]171
172config SYS_FSL_ERRATUM_NMG_DDR120
173 bool
174
175config SYS_FSL_ERRATUM_DDR_115
176 bool
177
178config SYS_FSL_ERRATUM_DDR111_DDR134
179 bool
180
181config SYS_FSL_ERRATUM_DDR_A003
182 bool
183
184config SYS_FSL_ERRATUM_DDR_A003474
185 bool