Blame - arch/arm/mach-zynqmp/Kconfig - platform/external/u-boot

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Siva Durga Prasad Paladugu	0b54a9d	2015-06-10 15:50:57 +0530	[diff] [blame]	1	if ARCH_ZYNQMP
				2
Michal Simek	84c7204	2015-01-15 10:01:51 +0100	[diff] [blame]	3	config SYS_BOARD
Liam Beguin	1814194	2021-10-20 11:25:18 -0400	[diff] [blame]	4	string "Board name"
Michal Simek	84c7204	2015-01-15 10:01:51 +0100	[diff] [blame]	5	default "zynqmp"
				6
				7	config SYS_VENDOR
Mike Looijmans	ef4cab9	2017-01-03 09:47:52 +0100	[diff] [blame]	8	string "Vendor name"
Michal Simek	84c7204	2015-01-15 10:01:51 +0100	[diff] [blame]	9	default "xilinx"
				10
				11	config SYS_SOC
				12	default "zynqmp"
				13
Siva Durga Prasad Paladugu	e042d36	2017-07-13 19:01:11 +0530	[diff] [blame]	14	config SYS_MEM_RSVD_FOR_MMU
				15	bool "Reserve memory for MMU Table"
				16	help
				17	If defined this option is used to setup different space for
				18	MMU table than the one which will be allocated during
				19	relocation.
				20
Mike Looijmans	3b64608	2016-09-20 11:37:24 +0200	[diff] [blame]	21	config BOOT_INIT_FILE
				22	string "boot.bin init register filename"
Michal Simek	9cf9da7	2016-12-16 13:00:26 +0100	[diff] [blame]	23	depends on SPL
Mike Looijmans	3b64608	2016-09-20 11:37:24 +0200	[diff] [blame]	24	default ""
				25	help
				26	Add register writes to boot.bin format (max 256 pairs).
				27	Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
				28
Michal Simek	c85a6b7	2016-10-21 12:58:17 +0200	[diff] [blame]	29	config PMUFW_INIT_FILE
				30	string "PMU firmware"
				31	depends on SPL
				32	default ""
				33	help
				34	Include external PMUFW (Platform Management Unit FirmWare) to
				35	a Xilinx bootable image (boot.bin).
				36
Luca Ceresoli	c28a9cf	2019-05-21 18:06:43 +0200	[diff] [blame]	37	config ZYNQMP_SPL_PM_CFG_OBJ_FILE
				38	string "PMU firmware configuration object to load at runtime by SPL"
				39	depends on SPL
				40	help
				41	Path to a binary PMU firmware configuration object to be linked
				42	into U-Boot SPL and loaded at runtime into the PMU firmware.
				43
				44	The ZynqMP Power Management Unit (PMU) needs a configuration
				45	object for most SoC peripherals to work. To have it loaded by
				46	U-Boot SPL set here the file name (absolute path or relative to
				47	the top source tree) of your configuration, which must be a
				48	binary blob. It will be linked in the SPL binary and loaded
				49	into the PMU firmware by U-Boot SPL during board
				50	initialization.
				51
				52	Leave this option empty if your PMU firmware has a hard-coded
				53	configuration object or you are loading it by any other means.
				54
Siva Durga Prasad Paladugu	3b644a3	2018-01-12 15:35:46 +0530	[diff] [blame]	55	config ZYNQMP_NO_DDR
				56	bool "Disable DDR MMU mapping"
				57	help
				58	This option configures MMU with no DDR to avoid speculative
				59	access to DDR memory where DDR is not present.
				60
Jorge Ramirez-Ortiz	01c7714	2021-06-13 20:55:53 +0200	[diff] [blame]	61	config SPL_ZYNQMP_DRAM_ECC_INIT
				62	bool "Initialize DRAM ECC"
				63	depends on SPL
				64	help
				65	This option initializes all memory to 0xdeadbeef. Must be set if your
				66	memory is of ECC type.
				67
				68	config SPL_ZYNQMP_DRAM_BANK1_BASE
				69	depends on SPL_ZYNQMP_DRAM_ECC_INIT
				70	hex "DRAM Bank1 address"
Michal Simek	a156b6c	2023-10-26 08:34:31 +0200	[diff] [blame]	71	default 0x00000000
				72	help
				73	Start address of DRAM ECC bank1
Jorge Ramirez-Ortiz	01c7714	2021-06-13 20:55:53 +0200	[diff] [blame]	74
				75	config SPL_ZYNQMP_DRAM_BANK1_LEN
				76	depends on SPL_ZYNQMP_DRAM_ECC_INIT
				77	hex "DRAM Bank1 size"
Michal Simek	a156b6c	2023-10-26 08:34:31 +0200	[diff] [blame]	78	default 0x80000000
				79	help
				80	Size in bytes of the DRAM ECC bank1
Jorge Ramirez-Ortiz	01c7714	2021-06-13 20:55:53 +0200	[diff] [blame]	81
				82	config SPL_ZYNQMP_DRAM_BANK2_BASE
				83	depends on SPL_ZYNQMP_DRAM_ECC_INIT
				84	hex "DRAM Bank2 address"
Michal Simek	a156b6c	2023-10-26 08:34:31 +0200	[diff] [blame]	85	default 0x800000000
				86	help
				87	Start address of DRAM ECC bank2
Jorge Ramirez-Ortiz	01c7714	2021-06-13 20:55:53 +0200	[diff] [blame]	88
				89	config SPL_ZYNQMP_DRAM_BANK2_LEN
				90	depends on SPL_ZYNQMP_DRAM_ECC_INIT
				91	hex "DRAM Bank2 size"
Michal Simek	a156b6c	2023-10-26 08:34:31 +0200	[diff] [blame]	92	default 0x0
				93	help
				94	Size in bytes of the DRAM ECC bank2. A null size takes no action.
Jorge Ramirez-Ortiz	01c7714	2021-06-13 20:55:53 +0200	[diff] [blame]	95
Simon Glass	04e3890	2016-07-05 17:10:13 -0600	[diff] [blame]	96	config SYS_MALLOC_F_LEN
				97	default 0x600
				98
Siva Durga Prasad Paladugu	189bec4	2017-07-13 19:01:10 +0530	[diff] [blame]	99	config DEFINE_TCM_OCM_MMAP
				100	bool "Define TCM and OCM memory in MMU Table"
Siva Durga Prasad Paladugu	8940148	2017-08-01 16:24:50 +0530	[diff] [blame]	101	default y if MP
Siva Durga Prasad Paladugu	189bec4	2017-07-13 19:01:10 +0530	[diff] [blame]	102	help
				103	This option if enabled defines the TCM and OCM memory and its
				104	memory attributes in MMU table entry.
				105
Michal Simek	fd1b635	2017-07-12 13:21:27 +0200	[diff] [blame]	106	config ZYNQMP_PSU_INIT_ENABLED
				107	bool "Include psu_init"
Michal Simek	83d2941	2022-02-17 14:28:40 +0100	[diff] [blame]	108	select BOARD_EARLY_INIT_F
Michal Simek	fd1b635	2017-07-12 13:21:27 +0200	[diff] [blame]	109	help
Michal Simek	74673ca	2022-12-02 09:18:06 +0100	[diff] [blame]	110	Include psu_init to full u-boot.
				111
				112	config SPL_ZYNQMP_PSU_INIT_ENABLED
				113	bool "Include psu_init in SPL"
Michal Simek	425b851	2024-03-12 16:51:21 +0100	[diff] [blame]	114	depends on SPL
				115	default y
Michal Simek	74673ca	2022-12-02 09:18:06 +0100	[diff] [blame]	116	select BOARD_EARLY_INIT_F
				117	help
				118	Include psu_init by default in SPL.
Michal Simek	fd1b635	2017-07-12 13:21:27 +0200	[diff] [blame]	119
Michal Simek	7f491d7	2016-08-30 16:17:27 +0200	[diff] [blame]	120	config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
				121	bool "Overwrite SPL bootmode"
				122	depends on SPL
				123	help
				124	Overwrite bootmode selected via boot mode pins to tell SPL what should
				125	be the next boot device.
				126
Jorge Ramirez-Ortiz	398a74a	2021-10-13 15:48:00 +0200	[diff] [blame]	127	config SPL_ZYNQMP_RESTORE_JTAG
				128	bool "Restore JTAG"
				129	depends on SPL
				130	help
				131	Booting SPL in secure mode causes the CSU to disable the JTAG interface
				132	even if no eFuses were burnt. This option restores the interface if
				133	possible.
				134
Vipul Kumar	5dc5a53	2018-02-28 15:53:28 +0530	[diff] [blame]	135	config ZYNQ_SDHCI_MAX_FREQ
				136	default 200000000
				137
Michal Simek	7f491d7	2016-08-30 16:17:27 +0200	[diff] [blame]	138	config SPL_ZYNQMP_ALT_BOOTMODE
				139	hex
				140	default 0x0 if JTAG_MODE
				141	default 0x1 if QSPI_MODE_24BIT
				142	default 0x2 if QSPI_MODE_32BIT
				143	default 0x3 if SD_MODE
				144	default 0x4 if NAND_MODE
				145	default 0x5 if SD_MODE1
				146	default 0x6 if EMMC_MODE
				147	default 0x7 if USB_MODE
Michal Simek	2661081	2016-10-26 09:24:32 +0200	[diff] [blame]	148	default 0xa if SW_USBHOST_MODE
				149	default 0xb if SW_SATA_MODE
Michal Simek	011f0c4	2017-02-15 09:41:53 +0100	[diff] [blame]	150	default 0xe if SD1_LSHFT_MODE
Michal Simek	7f491d7	2016-08-30 16:17:27 +0200	[diff] [blame]	151
				152	choice
				153	prompt "Boot mode"
Michal Simek	e367240	2016-08-30 16:17:27 +0200	[diff] [blame]	154	depends on SPL_ZYNQMP_ALT_BOOTMODE_ENABLED
Ulf Magnusson	e7563c2	2018-01-30 14:02:01 +0100	[diff] [blame]	155	default JTAG_MODE
Michal Simek	7f491d7	2016-08-30 16:17:27 +0200	[diff] [blame]	156
				157	config JTAG_MODE
				158	bool "JTAG_MODE"
				159
				160	config QSPI_MODE_24BIT
				161	bool "QSPI_MODE_24BIT"
				162
				163	config QSPI_MODE_32BIT
				164	bool "QSPI_MODE_32BIT"
				165
				166	config SD_MODE
				167	bool "SD_MODE"
				168
				169	config SD_MODE1
				170	bool "SD_MODE1"
				171
				172	config NAND_MODE
				173	bool "NAND_MODE"
				174
				175	config EMMC_MODE
				176	bool "EMMC_MODE"
				177
				178	config USB_MODE
				179	bool "USB"
				180
Michal Simek	2661081	2016-10-26 09:24:32 +0200	[diff] [blame]	181	config SW_USBHOST_MODE
				182	bool "SW USBHOST_MODE"
				183
				184	config SW_SATA_MODE
				185	bool "SW SATA_MODE"
				186
Michal Simek	011f0c4	2017-02-15 09:41:53 +0100	[diff] [blame]	187	config SD1_LSHFT_MODE
				188	bool "SD1_LSHFT_MODE"
				189
Michal Simek	7f491d7	2016-08-30 16:17:27 +0200	[diff] [blame]	190	endchoice
Simon Glass	04e3890	2016-07-05 17:10:13 -0600	[diff] [blame]	191
Charlie Johnston	7abd435	2024-04-10 12:50:08 -0700	[diff] [blame]	192	config CMD_ZYNQMP
				193	bool "Enable ZynqMP specific commands"
				194	depends on ZYNQMP_FIRMWARE
				195	default y
				196	help
				197	Enable ZynqMP specific commands like "zynqmp secure"
				198	which is used for zynqmp secure image verification.
				199	The secure image is a xilinx specific BOOT.BIN with
				200	either authentication or encryption or both encryption
				201	and authentication feature enabled while generating
				202	BOOT.BIN using Xilinx bootgen tool.
				203
Michal Simek	6ba36c0	2020-08-27 15:34:11 +0200	[diff] [blame]	204	source "board/xilinx/Kconfig"
Michal Simek	6ba36c0	2020-08-27 15:34:11 +0200	[diff] [blame]	205
Michal Simek	84c7204	2015-01-15 10:01:51 +0100	[diff] [blame]	206	endif