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wdenkc6097192002-11-03 00:24:07 +00001/*
Stefan Roesedbbd1252007-10-05 17:10:59 +02002 * (C) Copyright 2000-2007
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
wdenkc6097192002-11-03 00:24:07 +000025 * CPU specific code
26 *
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
29 *
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
32 */
33
34#include <common.h>
35#include <watchdog.h>
36#include <command.h>
37#include <asm/cache.h>
38#include <ppc4xx.h>
Ben Warren25a85902008-10-27 23:53:17 -070039#include <netdev.h>
wdenkc6097192002-11-03 00:24:07 +000040
Wolfgang Denkd87080b2006-03-31 18:32:53 +020041DECLARE_GLOBAL_DATA_PTR;
Wolfgang Denkd87080b2006-03-31 18:32:53 +020042
Stefan Roesef3443862006-10-07 11:30:52 +020043void board_reset(void);
Stefan Roesef3443862006-10-07 11:30:52 +020044
Adam Grahamc9c11d72008-10-08 10:13:19 -070045/*
46 * To provide an interface to detect CPU number for boards that support
47 * more then one CPU, we implement the "weak" default functions here.
48 *
49 * Returns CPU number
50 */
51int __get_cpu_num(void)
52{
53 return NA_OR_UNKNOWN_CPU;
54}
55int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
56
Stefan Roese20b3c4b2009-07-06 11:44:33 +020057#if defined(CONFIG_PCI)
Stefan Roese887e2ec2006-09-07 11:51:23 +020058#if defined(CONFIG_405GP) || \
59 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
60 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010061
62#define PCI_ASYNC
63
Stefan Roesec7f69c32007-11-09 12:18:54 +010064static int pci_async_enabled(void)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010065{
66#if defined(CONFIG_405GP)
Stefan Roesed1c3b272009-09-09 16:25:29 +020067 return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010068#endif
69
Stefan Roese887e2ec2006-09-07 11:51:23 +020070#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese2801b2d2008-03-11 15:05:50 +010071 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
72 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010073 unsigned long val;
74
Stefan Roesed1c3b272009-09-09 16:25:29 +020075 mfsdr(SDR0_SDSTP1, val);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010076 return (val & SDR0_SDSTP1_PAME_MASK);
77#endif
78}
79#endif
Stefan Roese20b3c4b2009-07-06 11:44:33 +020080#endif /* CONFIG_PCI */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010081
Stefan Roesedbbd1252007-10-05 17:10:59 +020082#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
83 !defined(CONFIG_405) && !defined(CONFIG_405EX)
Stefan Roesea760b022009-11-12 16:41:09 +010084int pci_arbiter_enabled(void)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010085{
86#if defined(CONFIG_405GP)
Stefan Roesed1c3b272009-09-09 16:25:29 +020087 return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010088#endif
89
90#if defined(CONFIG_405EP)
Stefan Roesed1c3b272009-09-09 16:25:29 +020091 return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010092#endif
93
94#if defined(CONFIG_440GP)
Stefan Roesed1c3b272009-09-09 16:25:29 +020095 return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010096#endif
97
Stefan Roese7372ca62007-02-02 12:44:22 +010098#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010099 unsigned long val;
100
Stefan Roesed1c3b272009-09-09 16:25:29 +0200101 mfsdr(SDR0_XCR, val);
Stefan Roese7372ca62007-02-02 12:44:22 +0100102 return (val & 0x80000000);
103#endif
104#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese2801b2d2008-03-11 15:05:50 +0100105 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
106 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roese7372ca62007-02-02 12:44:22 +0100107 unsigned long val;
108
Stefan Roesed1c3b272009-09-09 16:25:29 +0200109 mfsdr(SDR0_PCI0, val);
Stefan Roese7372ca62007-02-02 12:44:22 +0100110 return (val & 0x80000000);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100111#endif
112}
113#endif
114
Stefan Roesec7f69c32007-11-09 12:18:54 +0100115#if defined(CONFIG_405EP)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100116#define I2C_BOOTROM
117
Stefan Roesec7f69c32007-11-09 12:18:54 +0100118static int i2c_bootrom_enabled(void)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100119{
120#if defined(CONFIG_405EP)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200121 return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200122#else
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100123 unsigned long val;
124
Stefan Roesed1c3b272009-09-09 16:25:29 +0200125 mfsdr(SDR0_SDCS0, val);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100126 return (val & SDR0_SDCS_SDD);
127#endif
128}
Stefan Roese90e6f412007-04-18 12:05:59 +0200129#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200130
131#if defined(CONFIG_440GX)
132#define SDR0_PINSTP_SHIFT 29
133static char *bootstrap_str[] = {
134 "EBC (16 bits)",
135 "EBC (8 bits)",
136 "EBC (32 bits)",
137 "EBC (8 bits)",
138 "PCI",
139 "I2C (Addr 0x54)",
140 "Reserved",
141 "I2C (Addr 0x50)",
142};
BenoƮt Monine3cbe1f2007-06-04 08:36:05 +0200143static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
Stefan Roese887e2ec2006-09-07 11:51:23 +0200144#endif
145
146#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
147#define SDR0_PINSTP_SHIFT 30
148static char *bootstrap_str[] = {
149 "EBC (8 bits)",
150 "PCI",
151 "I2C (Addr 0x54)",
152 "I2C (Addr 0x50)",
153};
BenoƮt Monine3cbe1f2007-06-04 08:36:05 +0200154static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
Stefan Roese887e2ec2006-09-07 11:51:23 +0200155#endif
156
157#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
158#define SDR0_PINSTP_SHIFT 29
159static char *bootstrap_str[] = {
160 "EBC (8 bits)",
161 "PCI",
162 "NAND (8 bits)",
163 "EBC (16 bits)",
164 "EBC (16 bits)",
165 "I2C (Addr 0x54)",
166 "PCI",
167 "I2C (Addr 0x52)",
168};
BenoƮt Monine3cbe1f2007-06-04 08:36:05 +0200169static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
Stefan Roese887e2ec2006-09-07 11:51:23 +0200170#endif
171
172#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
173#define SDR0_PINSTP_SHIFT 29
174static char *bootstrap_str[] = {
175 "EBC (8 bits)",
176 "EBC (16 bits)",
177 "EBC (16 bits)",
178 "NAND (8 bits)",
179 "PCI",
180 "I2C (Addr 0x54)",
181 "PCI",
182 "I2C (Addr 0x52)",
183};
BenoƮt Monine3cbe1f2007-06-04 08:36:05 +0200184static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
Stefan Roese887e2ec2006-09-07 11:51:23 +0200185#endif
186
Stefan Roese2801b2d2008-03-11 15:05:50 +0100187#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
188#define SDR0_PINSTP_SHIFT 29
189static char *bootstrap_str[] = {
190 "EBC (8 bits)",
191 "EBC (16 bits)",
192 "PCI",
193 "PCI",
194 "EBC (16 bits)",
195 "NAND (8 bits)",
196 "I2C (Addr 0x54)", /* A8 */
197 "I2C (Addr 0x52)", /* A4 */
198};
199static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
200#endif
201
Feng Kan7d307932008-07-08 22:47:31 -0700202#if defined(CONFIG_460SX)
203#define SDR0_PINSTP_SHIFT 29
204static char *bootstrap_str[] = {
205 "EBC (8 bits)",
206 "EBC (16 bits)",
207 "EBC (32 bits)",
208 "NAND (8 bits)",
209 "I2C (Addr 0x54)", /* A8 */
210 "I2C (Addr 0x52)", /* A4 */
211};
212static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
213#endif
214
Stefan Roese90e6f412007-04-18 12:05:59 +0200215#if defined(CONFIG_405EZ)
216#define SDR0_PINSTP_SHIFT 28
217static char *bootstrap_str[] = {
218 "EBC (8 bits)",
219 "SPI (fast)",
220 "NAND (512 page, 4 addr cycle)",
221 "I2C (Addr 0x50)",
222 "EBC (32 bits)",
223 "I2C (Addr 0x50)",
224 "NAND (2K page, 5 addr cycle)",
225 "I2C (Addr 0x50)",
226 "EBC (16 bits)",
227 "Reserved",
228 "NAND (2K page, 4 addr cycle)",
229 "I2C (Addr 0x50)",
230 "NAND (512 page, 3 addr cycle)",
231 "I2C (Addr 0x50)",
232 "SPI (slow)",
233 "I2C (Addr 0x50)",
234};
BenoƮt Monine3cbe1f2007-06-04 08:36:05 +0200235static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
236 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
Stefan Roese90e6f412007-04-18 12:05:59 +0200237#endif
238
Stefan Roesedbbd1252007-10-05 17:10:59 +0200239#if defined(CONFIG_405EX)
240#define SDR0_PINSTP_SHIFT 29
241static char *bootstrap_str[] = {
242 "EBC (8 bits)",
243 "EBC (16 bits)",
244 "EBC (16 bits)",
245 "NAND (8 bits)",
246 "NAND (8 bits)",
247 "I2C (Addr 0x54)",
248 "EBC (8 bits)",
249 "I2C (Addr 0x52)",
250};
251static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
252#endif
253
Stefan Roese887e2ec2006-09-07 11:51:23 +0200254#if defined(SDR0_PINSTP_SHIFT)
255static int bootstrap_option(void)
256{
257 unsigned long val;
258
Stefan Roesed1c3b272009-09-09 16:25:29 +0200259 mfsdr(SDR0_PINSTP, val);
Stefan Roese90e6f412007-04-18 12:05:59 +0200260 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200261}
262#endif /* SDR0_PINSTP_SHIFT */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100263
Stefan Roese3d9569b2005-11-27 19:36:26 +0100264
265#if defined(CONFIG_440)
Stefan Roesec7f69c32007-11-09 12:18:54 +0100266static int do_chip_reset (unsigned long sys0, unsigned long sys1)
267{
Stefan Roesed1c3b272009-09-09 16:25:29 +0200268 /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
Stefan Roesec7f69c32007-11-09 12:18:54 +0100269 * reset.
270 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200271 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */
272 mtdcr (CPC0_SYS0, sys0);
273 mtdcr (CPC0_SYS1, sys1);
274 mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200275 mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
Stefan Roesec7f69c32007-11-09 12:18:54 +0100276
277 return 1;
278}
Stefan Roese3d9569b2005-11-27 19:36:26 +0100279#endif
280
wdenkc6097192002-11-03 00:24:07 +0000281
282int checkcpu (void)
283{
Stefan Roese3d9569b2005-11-27 19:36:26 +0100284#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100285 uint pvr = get_pvr();
wdenkc6097192002-11-03 00:24:07 +0000286 ulong clock = gd->cpu_clk;
287 char buf[32];
Stefan Roese89bcc482009-07-29 08:45:27 +0200288#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
289 u32 reg;
290#endif
wdenkc6097192002-11-03 00:24:07 +0000291
Stefan Roese3d9569b2005-11-27 19:36:26 +0100292#if !defined(CONFIG_IOP480)
Wolfgang Denkba999c52006-10-20 17:54:33 +0200293 char addstr[64] = "";
Stefan Roese3d9569b2005-11-27 19:36:26 +0100294 sys_info_t sys_info;
Adam Grahamc9c11d72008-10-08 10:13:19 -0700295 int cpu_num;
wdenkc6097192002-11-03 00:24:07 +0000296
Adam Grahamc9c11d72008-10-08 10:13:19 -0700297 cpu_num = get_cpu_num();
298 if (cpu_num >= 0)
299 printf("CPU%d: ", cpu_num);
300 else
301 puts("CPU: ");
wdenkc6097192002-11-03 00:24:07 +0000302
303 get_sys_info(&sys_info);
304
Ricardo Ribalda Delgadod865fd02008-07-17 11:44:12 +0200305#if defined(CONFIG_XILINX_440)
306 puts("IBM PowerPC 4");
307#else
Stefan Roese3d9569b2005-11-27 19:36:26 +0100308 puts("AMCC PowerPC 4");
Ricardo Ribalda Delgadod865fd02008-07-17 11:44:12 +0200309#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100310
Stefan Roesee01bd212007-03-21 13:38:59 +0100311#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200312 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
313 defined(CONFIG_405EX)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100314 puts("05");
wdenkc6097192002-11-03 00:24:07 +0000315#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100316#if defined(CONFIG_440)
Stefan Roese2801b2d2008-03-11 15:05:50 +0100317#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
318 puts("60");
319#else
Stefan Roese3d9569b2005-11-27 19:36:26 +0100320 puts("40");
wdenkc6097192002-11-03 00:24:07 +0000321#endif
Stefan Roese2801b2d2008-03-11 15:05:50 +0100322#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100323
wdenkc6097192002-11-03 00:24:07 +0000324 switch (pvr) {
325 case PVR_405GP_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100326 puts("GP Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000327 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100328
wdenkc6097192002-11-03 00:24:07 +0000329 case PVR_405GP_RC:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100330 puts("GP Rev. C");
wdenkc6097192002-11-03 00:24:07 +0000331 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100332
wdenkc6097192002-11-03 00:24:07 +0000333 case PVR_405GP_RD:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100334 puts("GP Rev. D");
wdenkc6097192002-11-03 00:24:07 +0000335 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100336
wdenk42dfe7a2004-03-14 22:25:36 +0000337#ifdef CONFIG_405GP
Stefan Roese3d9569b2005-11-27 19:36:26 +0100338 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
339 puts("GP Rev. E");
wdenkc6097192002-11-03 00:24:07 +0000340 break;
341#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100342
wdenkc6097192002-11-03 00:24:07 +0000343 case PVR_405CR_RA:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100344 puts("CR Rev. A");
wdenkc6097192002-11-03 00:24:07 +0000345 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100346
wdenkc6097192002-11-03 00:24:07 +0000347 case PVR_405CR_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100348 puts("CR Rev. B");
349 break;
350
351#ifdef CONFIG_405CR
352 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
353 puts("CR Rev. C");
354 break;
355#endif
356
357 case PVR_405GPR_RB:
358 puts("GPr Rev. B");
359 break;
360
stroeseb867d702003-05-23 11:18:02 +0000361 case PVR_405EP_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100362 puts("EP Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000363 break;
wdenkc6097192002-11-03 00:24:07 +0000364
Stefan Roesee01bd212007-03-21 13:38:59 +0100365 case PVR_405EZ_RA:
366 puts("EZ Rev. A");
367 break;
368
Stefan Roesedbbd1252007-10-05 17:10:59 +0200369 case PVR_405EX1_RA:
370 puts("EX Rev. A");
371 strcpy(addstr, "Security support");
372 break;
373
Stefan Roesedbbd1252007-10-05 17:10:59 +0200374 case PVR_405EXR2_RA:
375 puts("EXr Rev. A");
376 strcpy(addstr, "No Security support");
377 break;
378
Stefan Roese70fab192008-05-13 20:22:01 +0200379 case PVR_405EX1_RC:
380 puts("EX Rev. C");
381 strcpy(addstr, "Security support");
382 break;
383
384 case PVR_405EX2_RC:
385 puts("EX Rev. C");
386 strcpy(addstr, "No Security support");
387 break;
388
389 case PVR_405EXR1_RC:
390 puts("EXr Rev. C");
391 strcpy(addstr, "Security support");
392 break;
393
394 case PVR_405EXR2_RC:
395 puts("EXr Rev. C");
396 strcpy(addstr, "No Security support");
397 break;
398
Stefan Roese56f14812009-10-06 07:21:08 +0200399 case PVR_405EX1_RD:
400 puts("EX Rev. D");
401 strcpy(addstr, "Security support");
402 break;
403
404 case PVR_405EX2_RD:
405 puts("EX Rev. D");
406 strcpy(addstr, "No Security support");
407 break;
408
409 case PVR_405EXR1_RD:
410 puts("EXr Rev. D");
411 strcpy(addstr, "Security support");
412 break;
413
414 case PVR_405EXR2_RD:
415 puts("EXr Rev. D");
416 strcpy(addstr, "No Security support");
417 break;
418
wdenkc6097192002-11-03 00:24:07 +0000419#if defined(CONFIG_440)
wdenk8bde7f72003-06-27 21:31:46 +0000420 case PVR_440GP_RB:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200421 puts("GP Rev. B");
wdenk4d816772003-09-03 14:03:26 +0000422 /* See errata 1.12: CHIP_4 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200423 if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
424 (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
wdenk4d816772003-09-03 14:03:26 +0000425 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
426 "Resetting chip ...\n");
427 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200428 do_chip_reset ( mfdcr(CPC0_STRP0),
429 mfdcr(CPC0_STRP1) );
wdenk4d816772003-09-03 14:03:26 +0000430 }
wdenkc6097192002-11-03 00:24:07 +0000431 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100432
wdenk8bde7f72003-06-27 21:31:46 +0000433 case PVR_440GP_RC:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200434 puts("GP Rev. C");
wdenkba56f622004-02-06 23:19:44 +0000435 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100436
wdenkba56f622004-02-06 23:19:44 +0000437 case PVR_440GX_RA:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200438 puts("GX Rev. A");
wdenkba56f622004-02-06 23:19:44 +0000439 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100440
wdenkba56f622004-02-06 23:19:44 +0000441 case PVR_440GX_RB:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200442 puts("GX Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000443 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100444
stroese0a7c5392005-04-07 05:33:41 +0000445 case PVR_440GX_RC:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200446 puts("GX Rev. C");
stroese0a7c5392005-04-07 05:33:41 +0000447 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100448
Stefan Roese57275b62005-11-01 10:08:03 +0100449 case PVR_440GX_RF:
450 puts("GX Rev. F");
451 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100452
Stefan Roesec157d8e2005-08-01 16:41:48 +0200453 case PVR_440EP_RA:
454 puts("EP Rev. A");
455 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100456
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200457#ifdef CONFIG_440EP
458 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200459 puts("EP Rev. B");
460 break;
Stefan Roese512f8d52006-05-10 14:10:41 +0200461
462 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
463 puts("EP Rev. C");
464 break;
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200465#endif /* CONFIG_440EP */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100466
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200467#ifdef CONFIG_440GR
468 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
469 puts("GR Rev. A");
470 break;
Stefan Roese512f8d52006-05-10 14:10:41 +0200471
Stefan Roese5770a1e2006-05-18 19:21:53 +0200472 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
Stefan Roese512f8d52006-05-10 14:10:41 +0200473 puts("GR Rev. B");
474 break;
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200475#endif /* CONFIG_440GR */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100476#endif /* CONFIG_440 */
477
Stefan Roese2902fad2007-01-31 16:56:10 +0100478#ifdef CONFIG_440EPX
479 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200480 puts("EPx Rev. A");
481 strcpy(addstr, "Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200482 break;
483
Stefan Roese2902fad2007-01-31 16:56:10 +0100484 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200485 puts("EPx Rev. A");
486 strcpy(addstr, "No Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200487 break;
Stefan Roese2902fad2007-01-31 16:56:10 +0100488#endif /* CONFIG_440EPX */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200489
Stefan Roese2902fad2007-01-31 16:56:10 +0100490#ifdef CONFIG_440GRX
491 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200492 puts("GRx Rev. A");
493 strcpy(addstr, "Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200494 break;
495
Stefan Roese2902fad2007-01-31 16:56:10 +0100496 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200497 puts("GRx Rev. A");
498 strcpy(addstr, "No Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200499 break;
Stefan Roese2902fad2007-01-31 16:56:10 +0100500#endif /* CONFIG_440GRX */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200501
Stefan Roese95981772007-01-13 08:01:03 +0100502 case PVR_440SP_6_RAB:
503 puts("SP Rev. A/B");
504 strcpy(addstr, "RAID 6 support");
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100505 break;
506
Stefan Roese95981772007-01-13 08:01:03 +0100507 case PVR_440SP_RAB:
508 puts("SP Rev. A/B");
509 strcpy(addstr, "No RAID 6 support");
510 break;
511
512 case PVR_440SP_6_RC:
513 puts("SP Rev. C");
514 strcpy(addstr, "RAID 6 support");
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100515 break;
516
Stefan Roesee732fae2006-11-28 16:09:24 +0100517 case PVR_440SP_RC:
518 puts("SP Rev. C");
Stefan Roese95981772007-01-13 08:01:03 +0100519 strcpy(addstr, "No RAID 6 support");
520 break;
521
522 case PVR_440SPe_6_RA:
523 puts("SPe Rev. A");
524 strcpy(addstr, "RAID 6 support");
Stefan Roesee732fae2006-11-28 16:09:24 +0100525 break;
526
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200527 case PVR_440SPe_RA:
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200528 puts("SPe Rev. A");
Stefan Roese95981772007-01-13 08:01:03 +0100529 strcpy(addstr, "No RAID 6 support");
530 break;
531
532 case PVR_440SPe_6_RB:
533 puts("SPe Rev. B");
534 strcpy(addstr, "RAID 6 support");
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200535 break;
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200536
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200537 case PVR_440SPe_RB:
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200538 puts("SPe Rev. B");
Stefan Roese95981772007-01-13 08:01:03 +0100539 strcpy(addstr, "No RAID 6 support");
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200540 break;
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200541
Stefan Roese89bcc482009-07-29 08:45:27 +0200542#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roese2801b2d2008-03-11 15:05:50 +0100543 case PVR_460EX_RA:
544 puts("EX Rev. A");
545 strcpy(addstr, "No Security/Kasumi support");
546 break;
547
548 case PVR_460EX_SE_RA:
549 puts("EX Rev. A");
550 strcpy(addstr, "Security/Kasumi support");
551 break;
552
Stefan Roese89bcc482009-07-29 08:45:27 +0200553 case PVR_460EX_RB:
554 puts("EX Rev. B");
555 mfsdr(SDR0_ECID3, reg);
556 if (reg & 0x00100000)
557 strcpy(addstr, "No Security/Kasumi support");
558 else
559 strcpy(addstr, "Security/Kasumi support");
560 break;
561
Stefan Roese2801b2d2008-03-11 15:05:50 +0100562 case PVR_460GT_RA:
563 puts("GT Rev. A");
564 strcpy(addstr, "No Security/Kasumi support");
565 break;
566
567 case PVR_460GT_SE_RA:
568 puts("GT Rev. A");
569 strcpy(addstr, "Security/Kasumi support");
570 break;
571
Stefan Roese89bcc482009-07-29 08:45:27 +0200572 case PVR_460GT_RB:
573 puts("GT Rev. B");
574 mfsdr(SDR0_ECID3, reg);
575 if (reg & 0x00100000)
576 strcpy(addstr, "No Security/Kasumi support");
577 else
578 strcpy(addstr, "Security/Kasumi support");
579 break;
580#endif
581
Feng Kan7d307932008-07-08 22:47:31 -0700582 case PVR_460SX_RA:
583 puts("SX Rev. A");
584 strcpy(addstr, "Security support");
585 break;
586
587 case PVR_460SX_RA_V1:
588 puts("SX Rev. A");
589 strcpy(addstr, "No Security support");
590 break;
591
592 case PVR_460GX_RA:
593 puts("GX Rev. A");
594 strcpy(addstr, "Security support");
595 break;
596
597 case PVR_460GX_RA_V1:
598 puts("GX Rev. A");
599 strcpy(addstr, "No Security support");
600 break;
601
Ricardo Ribalda Delgadod865fd02008-07-17 11:44:12 +0200602 case PVR_VIRTEX5:
603 puts("x5 VIRTEX5");
604 break;
605
wdenk8bde7f72003-06-27 21:31:46 +0000606 default:
Stefan Roese17f50f222005-08-04 17:09:16 +0200607 printf (" UNKNOWN (PVR=%08x)", pvr);
wdenkc6097192002-11-03 00:24:07 +0000608 break;
609 }
Stefan Roese3d9569b2005-11-27 19:36:26 +0100610
Stefan Roese08c6a262009-10-19 14:44:11 +0200611 printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
612 strmhz(buf, clock),
Stefan Roesee01bd212007-03-21 13:38:59 +0100613 sys_info.freqPLB / 1000000,
614 get_OPB_freq() / 1000000,
Stefan Roesedbbd1252007-10-05 17:10:59 +0200615 sys_info.freqEBC / 1000000);
Stefan Roese08c6a262009-10-19 14:44:11 +0200616#if defined(CONFIG_PCI) && \
617 (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
618 defined(CONFIG_440GR) || defined(CONFIG_440GRX))
619 printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
620#endif
621 printf(")\n");
Stefan Roese3d9569b2005-11-27 19:36:26 +0100622
Stefan Roeseedf0b542006-10-18 15:59:35 +0200623 if (addstr[0] != 0)
624 printf(" %s\n", addstr);
625
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100626#if defined(I2C_BOOTROM)
627 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
Stefan Roese90e6f412007-04-18 12:05:59 +0200628#endif /* I2C_BOOTROM */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200629#if defined(SDR0_PINSTP_SHIFT)
BenoƮt Monine3cbe1f2007-06-04 08:36:05 +0200630 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
Stefan Roesecf940982009-04-15 10:50:48 +0200631 printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
632#ifdef CONFIG_NAND_U_BOOT
633 puts(", booting from NAND");
634#endif /* CONFIG_NAND_U_BOOT */
635 putc('\n');
Wolfgang Denkba999c52006-10-20 17:54:33 +0200636#endif /* SDR0_PINSTP_SHIFT */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100637
Stefan Roesedbbd1252007-10-05 17:10:59 +0200638#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100639 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
Stefan Roese3d9569b2005-11-27 19:36:26 +0100640#endif
641
Stefan Roese1bbae2b2009-05-27 10:34:32 +0200642#if defined(CONFIG_PCI) && defined(PCI_ASYNC)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100643 if (pci_async_enabled()) {
Stefan Roese3d9569b2005-11-27 19:36:26 +0100644 printf (", PCI async ext clock used");
645 } else {
646 printf (", PCI sync clock at %lu MHz",
647 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
648 }
649#endif
650
Stefan Roesedbbd1252007-10-05 17:10:59 +0200651#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100652 putc('\n');
653#endif
654
Stefan Roesedbbd1252007-10-05 17:10:59 +0200655#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100656 printf (" 16 kB I-Cache 16 kB D-Cache");
657#elif defined(CONFIG_440)
658 printf (" 32 kB I-Cache 32 kB D-Cache");
659#else
660 printf (" 16 kB I-Cache %d kB D-Cache",
661 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
662#endif
663#endif /* !defined(CONFIG_IOP480) */
664
665#if defined(CONFIG_IOP480)
666 printf ("PLX IOP480 (PVR=%08x)", pvr);
667 printf (" at %s MHz:", strmhz(buf, clock));
668 printf (" %u kB I-Cache", 4);
669 printf (" %u kB D-Cache", 2);
670#endif
671
672#endif /* !defined(CONFIG_405) */
673
674 putc ('\n');
wdenkc6097192002-11-03 00:24:07 +0000675
676 return 0;
677}
678
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200679int ppc440spe_revB() {
680 unsigned int pvr;
681
682 pvr = get_pvr();
Stefan Roese5a5c5692007-01-15 09:46:29 +0100683 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200684 return 1;
685 else
686 return 0;
687}
wdenkc6097192002-11-03 00:24:07 +0000688
689/* ------------------------------------------------------------------------- */
690
wdenk8bde7f72003-06-27 21:31:46 +0000691int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
wdenkc6097192002-11-03 00:24:07 +0000692{
Stefan Roese1f94d162006-11-27 14:48:41 +0100693#if defined(CONFIG_BOARD_RESET)
694 board_reset();
Stefan Roese1729b922006-11-27 14:52:04 +0100695#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200696#if defined(CONFIG_SYS_4xx_RESET_TYPE)
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200697 mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
Stefan Roesec157d8e2005-08-01 16:41:48 +0200698#else
wdenk8bde7f72003-06-27 21:31:46 +0000699 /*
700 * Initiate system reset in debug control register DBCR
701 */
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200702 mtspr(SPRN_DBCR0, 0x30000000);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200703#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
Stefan Roesef3443862006-10-07 11:30:52 +0200704#endif /* defined(CONFIG_BOARD_RESET) */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200705
wdenkc6097192002-11-03 00:24:07 +0000706 return 1;
707}
708
wdenkc6097192002-11-03 00:24:07 +0000709
710/*
711 * Get timebase clock frequency
712 */
713unsigned long get_tbclk (void)
714{
Stefan Roese3d9569b2005-11-27 19:36:26 +0100715#if !defined(CONFIG_IOP480)
wdenkc6097192002-11-03 00:24:07 +0000716 sys_info_t sys_info;
717
718 get_sys_info(&sys_info);
719 return (sys_info.freqProcessor);
wdenkc6097192002-11-03 00:24:07 +0000720#else
Stefan Roese3d9569b2005-11-27 19:36:26 +0100721 return (66000000);
wdenkc6097192002-11-03 00:24:07 +0000722#endif
723
724}
725
726
727#if defined(CONFIG_WATCHDOG)
Stefan Roesec7f69c32007-11-09 12:18:54 +0100728void watchdog_reset(void)
wdenkc6097192002-11-03 00:24:07 +0000729{
730 int re_enable = disable_interrupts();
731 reset_4xx_watchdog();
732 if (re_enable) enable_interrupts();
733}
734
Stefan Roesec7f69c32007-11-09 12:18:54 +0100735void reset_4xx_watchdog(void)
wdenkc6097192002-11-03 00:24:07 +0000736{
737 /*
738 * Clear TSR(WIS) bit
739 */
Matthias Fuchs58ea1422009-07-22 17:27:56 +0200740 mtspr(SPRN_TSR, 0x40000000);
wdenkc6097192002-11-03 00:24:07 +0000741}
742#endif /* CONFIG_WATCHDOG */
Ben Warren25a85902008-10-27 23:53:17 -0700743
744/*
745 * Initializes on-chip ethernet controllers.
746 * to override, implement board_eth_init()
747 */
748int cpu_eth_init(bd_t *bis)
749{
750#if defined(CONFIG_PPC4xx_EMAC)
751 ppc_4xx_eth_initialize(bis);
752#endif
753 return 0;
754}