wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 1 | /* |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame^] | 2 | * (C) Copyright 2000-2007 |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 25 | * CPU specific code |
| 26 | * |
| 27 | * written or collected and sometimes rewritten by |
| 28 | * Magnus Damm <damm@bitsmart.com> |
| 29 | * |
| 30 | * minor modifications by |
| 31 | * Wolfgang Denk <wd@denx.de> |
| 32 | */ |
| 33 | |
| 34 | #include <common.h> |
| 35 | #include <watchdog.h> |
| 36 | #include <command.h> |
| 37 | #include <asm/cache.h> |
| 38 | #include <ppc4xx.h> |
| 39 | |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 40 | #if !defined(CONFIG_405) |
| 41 | DECLARE_GLOBAL_DATA_PTR; |
| 42 | #endif |
| 43 | |
Stefan Roese | f344386 | 2006-10-07 11:30:52 +0200 | [diff] [blame] | 44 | #if defined(CONFIG_BOARD_RESET) |
| 45 | void board_reset(void); |
| 46 | #endif |
| 47 | |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 48 | #if defined(CONFIG_405GP) || \ |
| 49 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
| 50 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 51 | |
| 52 | #define PCI_ASYNC |
| 53 | |
| 54 | int pci_async_enabled(void) |
| 55 | { |
| 56 | #if defined(CONFIG_405GP) |
| 57 | return (mfdcr(strap) & PSR_PCI_ASYNC_EN); |
| 58 | #endif |
| 59 | |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 60 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
| 61 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 62 | unsigned long val; |
| 63 | |
Wolfgang Denk | 7481266 | 2005-12-12 16:06:05 +0100 | [diff] [blame] | 64 | mfsdr(sdr_sdstp1, val); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 65 | return (val & SDR0_SDSTP1_PAME_MASK); |
| 66 | #endif |
| 67 | } |
| 68 | #endif |
| 69 | |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame^] | 70 | #if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \ |
| 71 | !defined(CONFIG_405) && !defined(CONFIG_405EX) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 72 | int pci_arbiter_enabled(void) |
| 73 | { |
| 74 | #if defined(CONFIG_405GP) |
| 75 | return (mfdcr(strap) & PSR_PCI_ARBIT_EN); |
| 76 | #endif |
| 77 | |
| 78 | #if defined(CONFIG_405EP) |
| 79 | return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN); |
| 80 | #endif |
| 81 | |
| 82 | #if defined(CONFIG_440GP) |
| 83 | return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); |
| 84 | #endif |
| 85 | |
Stefan Roese | 7372ca6 | 2007-02-02 12:44:22 +0100 | [diff] [blame] | 86 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 87 | unsigned long val; |
| 88 | |
Stefan Roese | 7372ca6 | 2007-02-02 12:44:22 +0100 | [diff] [blame] | 89 | mfsdr(sdr_xcr, val); |
| 90 | return (val & 0x80000000); |
| 91 | #endif |
| 92 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
| 93 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
| 94 | unsigned long val; |
| 95 | |
| 96 | mfsdr(sdr_pci0, val); |
| 97 | return (val & 0x80000000); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 98 | #endif |
| 99 | } |
| 100 | #endif |
| 101 | |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 102 | #if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \ |
| 103 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ |
| 104 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame^] | 105 | defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ |
| 106 | defined(CONFIG_405EX) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 107 | |
| 108 | #define I2C_BOOTROM |
| 109 | |
| 110 | int i2c_bootrom_enabled(void) |
| 111 | { |
| 112 | #if defined(CONFIG_405EP) |
| 113 | return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 114 | #else |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 115 | unsigned long val; |
| 116 | |
| 117 | mfsdr(sdr_sdcs, val); |
| 118 | return (val & SDR0_SDCS_SDD); |
| 119 | #endif |
| 120 | } |
Stefan Roese | 90e6f41 | 2007-04-18 12:05:59 +0200 | [diff] [blame] | 121 | #endif |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 122 | |
| 123 | #if defined(CONFIG_440GX) |
| 124 | #define SDR0_PINSTP_SHIFT 29 |
| 125 | static char *bootstrap_str[] = { |
| 126 | "EBC (16 bits)", |
| 127 | "EBC (8 bits)", |
| 128 | "EBC (32 bits)", |
| 129 | "EBC (8 bits)", |
| 130 | "PCI", |
| 131 | "I2C (Addr 0x54)", |
| 132 | "Reserved", |
| 133 | "I2C (Addr 0x50)", |
| 134 | }; |
Benoît Monin | e3cbe1f | 2007-06-04 08:36:05 +0200 | [diff] [blame] | 135 | static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' }; |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 136 | #endif |
| 137 | |
| 138 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
| 139 | #define SDR0_PINSTP_SHIFT 30 |
| 140 | static char *bootstrap_str[] = { |
| 141 | "EBC (8 bits)", |
| 142 | "PCI", |
| 143 | "I2C (Addr 0x54)", |
| 144 | "I2C (Addr 0x50)", |
| 145 | }; |
Benoît Monin | e3cbe1f | 2007-06-04 08:36:05 +0200 | [diff] [blame] | 146 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D'}; |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 147 | #endif |
| 148 | |
| 149 | #if defined(CONFIG_440EP) || defined(CONFIG_440GR) |
| 150 | #define SDR0_PINSTP_SHIFT 29 |
| 151 | static char *bootstrap_str[] = { |
| 152 | "EBC (8 bits)", |
| 153 | "PCI", |
| 154 | "NAND (8 bits)", |
| 155 | "EBC (16 bits)", |
| 156 | "EBC (16 bits)", |
| 157 | "I2C (Addr 0x54)", |
| 158 | "PCI", |
| 159 | "I2C (Addr 0x52)", |
| 160 | }; |
Benoît Monin | e3cbe1f | 2007-06-04 08:36:05 +0200 | [diff] [blame] | 161 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 162 | #endif |
| 163 | |
| 164 | #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) |
| 165 | #define SDR0_PINSTP_SHIFT 29 |
| 166 | static char *bootstrap_str[] = { |
| 167 | "EBC (8 bits)", |
| 168 | "EBC (16 bits)", |
| 169 | "EBC (16 bits)", |
| 170 | "NAND (8 bits)", |
| 171 | "PCI", |
| 172 | "I2C (Addr 0x54)", |
| 173 | "PCI", |
| 174 | "I2C (Addr 0x52)", |
| 175 | }; |
Benoît Monin | e3cbe1f | 2007-06-04 08:36:05 +0200 | [diff] [blame] | 176 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 177 | #endif |
| 178 | |
Stefan Roese | 90e6f41 | 2007-04-18 12:05:59 +0200 | [diff] [blame] | 179 | #if defined(CONFIG_405EZ) |
| 180 | #define SDR0_PINSTP_SHIFT 28 |
| 181 | static char *bootstrap_str[] = { |
| 182 | "EBC (8 bits)", |
| 183 | "SPI (fast)", |
| 184 | "NAND (512 page, 4 addr cycle)", |
| 185 | "I2C (Addr 0x50)", |
| 186 | "EBC (32 bits)", |
| 187 | "I2C (Addr 0x50)", |
| 188 | "NAND (2K page, 5 addr cycle)", |
| 189 | "I2C (Addr 0x50)", |
| 190 | "EBC (16 bits)", |
| 191 | "Reserved", |
| 192 | "NAND (2K page, 4 addr cycle)", |
| 193 | "I2C (Addr 0x50)", |
| 194 | "NAND (512 page, 3 addr cycle)", |
| 195 | "I2C (Addr 0x50)", |
| 196 | "SPI (slow)", |
| 197 | "I2C (Addr 0x50)", |
| 198 | }; |
Benoît Monin | e3cbe1f | 2007-06-04 08:36:05 +0200 | [diff] [blame] | 199 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \ |
| 200 | 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' }; |
Stefan Roese | 90e6f41 | 2007-04-18 12:05:59 +0200 | [diff] [blame] | 201 | #endif |
| 202 | |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame^] | 203 | #if defined(CONFIG_405EX) |
| 204 | #define SDR0_PINSTP_SHIFT 29 |
| 205 | static char *bootstrap_str[] = { |
| 206 | "EBC (8 bits)", |
| 207 | "EBC (16 bits)", |
| 208 | "EBC (16 bits)", |
| 209 | "NAND (8 bits)", |
| 210 | "NAND (8 bits)", |
| 211 | "I2C (Addr 0x54)", |
| 212 | "EBC (8 bits)", |
| 213 | "I2C (Addr 0x52)", |
| 214 | }; |
| 215 | static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' }; |
| 216 | #endif |
| 217 | |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 218 | #if defined(SDR0_PINSTP_SHIFT) |
| 219 | static int bootstrap_option(void) |
| 220 | { |
| 221 | unsigned long val; |
| 222 | |
Stefan Roese | 90e6f41 | 2007-04-18 12:05:59 +0200 | [diff] [blame] | 223 | mfsdr(SDR_PINSTP, val); |
| 224 | return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 225 | } |
| 226 | #endif /* SDR0_PINSTP_SHIFT */ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 227 | |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 228 | |
| 229 | #if defined(CONFIG_440) |
| 230 | static int do_chip_reset(unsigned long sys0, unsigned long sys1); |
| 231 | #endif |
| 232 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 233 | |
| 234 | int checkcpu (void) |
| 235 | { |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 236 | #if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */ |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 237 | uint pvr = get_pvr(); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 238 | ulong clock = gd->cpu_clk; |
| 239 | char buf[32]; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 240 | |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 241 | #if !defined(CONFIG_IOP480) |
Wolfgang Denk | ba999c5 | 2006-10-20 17:54:33 +0200 | [diff] [blame] | 242 | char addstr[64] = ""; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 243 | sys_info_t sys_info; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 244 | |
| 245 | puts ("CPU: "); |
| 246 | |
| 247 | get_sys_info(&sys_info); |
| 248 | |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 249 | puts("AMCC PowerPC 4"); |
| 250 | |
Stefan Roese | e01bd21 | 2007-03-21 13:38:59 +0100 | [diff] [blame] | 251 | #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame^] | 252 | defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ |
| 253 | defined(CONFIG_405EX) |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 254 | puts("05"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 255 | #endif |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 256 | #if defined(CONFIG_440) |
| 257 | puts("40"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 258 | #endif |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 259 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 260 | switch (pvr) { |
| 261 | case PVR_405GP_RB: |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 262 | puts("GP Rev. B"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 263 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 264 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 265 | case PVR_405GP_RC: |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 266 | puts("GP Rev. C"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 267 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 268 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 269 | case PVR_405GP_RD: |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 270 | puts("GP Rev. D"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 271 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 272 | |
wdenk | 42dfe7a | 2004-03-14 22:25:36 +0000 | [diff] [blame] | 273 | #ifdef CONFIG_405GP |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 274 | case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */ |
| 275 | puts("GP Rev. E"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 276 | break; |
| 277 | #endif |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 278 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 279 | case PVR_405CR_RA: |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 280 | puts("CR Rev. A"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 281 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 282 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 283 | case PVR_405CR_RB: |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 284 | puts("CR Rev. B"); |
| 285 | break; |
| 286 | |
| 287 | #ifdef CONFIG_405CR |
| 288 | case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */ |
| 289 | puts("CR Rev. C"); |
| 290 | break; |
| 291 | #endif |
| 292 | |
| 293 | case PVR_405GPR_RB: |
| 294 | puts("GPr Rev. B"); |
| 295 | break; |
| 296 | |
stroese | b867d70 | 2003-05-23 11:18:02 +0000 | [diff] [blame] | 297 | case PVR_405EP_RB: |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 298 | puts("EP Rev. B"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 299 | break; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 300 | |
Stefan Roese | e01bd21 | 2007-03-21 13:38:59 +0100 | [diff] [blame] | 301 | case PVR_405EZ_RA: |
| 302 | puts("EZ Rev. A"); |
| 303 | break; |
| 304 | |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame^] | 305 | case PVR_405EX1_RA: |
| 306 | puts("EX Rev. A"); |
| 307 | strcpy(addstr, "Security support"); |
| 308 | break; |
| 309 | |
| 310 | case PVR_405EX2_RA: |
| 311 | puts("EX Rev. A"); |
| 312 | strcpy(addstr, "No Security support"); |
| 313 | break; |
| 314 | |
| 315 | case PVR_405EXR1_RA: |
| 316 | puts("EXr Rev. A"); |
| 317 | strcpy(addstr, "Security support"); |
| 318 | break; |
| 319 | |
| 320 | case PVR_405EXR2_RA: |
| 321 | puts("EXr Rev. A"); |
| 322 | strcpy(addstr, "No Security support"); |
| 323 | break; |
| 324 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 325 | #if defined(CONFIG_440) |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 326 | case PVR_440GP_RB: |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 327 | puts("GP Rev. B"); |
wdenk | 4d81677 | 2003-09-03 14:03:26 +0000 | [diff] [blame] | 328 | /* See errata 1.12: CHIP_4 */ |
| 329 | if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) || |
| 330 | (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){ |
| 331 | puts ( "\n\t CPC0_SYSx DCRs corrupted. " |
| 332 | "Resetting chip ...\n"); |
| 333 | udelay( 1000 * 1000 ); /* Give time for serial buf to clear */ |
| 334 | do_chip_reset ( mfdcr(cpc0_strp0), |
| 335 | mfdcr(cpc0_strp1) ); |
| 336 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 337 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 338 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 339 | case PVR_440GP_RC: |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 340 | puts("GP Rev. C"); |
wdenk | ba56f62 | 2004-02-06 23:19:44 +0000 | [diff] [blame] | 341 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 342 | |
wdenk | ba56f62 | 2004-02-06 23:19:44 +0000 | [diff] [blame] | 343 | case PVR_440GX_RA: |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 344 | puts("GX Rev. A"); |
wdenk | ba56f62 | 2004-02-06 23:19:44 +0000 | [diff] [blame] | 345 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 346 | |
wdenk | ba56f62 | 2004-02-06 23:19:44 +0000 | [diff] [blame] | 347 | case PVR_440GX_RB: |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 348 | puts("GX Rev. B"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 349 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 350 | |
stroese | 0a7c539 | 2005-04-07 05:33:41 +0000 | [diff] [blame] | 351 | case PVR_440GX_RC: |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 352 | puts("GX Rev. C"); |
stroese | 0a7c539 | 2005-04-07 05:33:41 +0000 | [diff] [blame] | 353 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 354 | |
Stefan Roese | 57275b6 | 2005-11-01 10:08:03 +0100 | [diff] [blame] | 355 | case PVR_440GX_RF: |
| 356 | puts("GX Rev. F"); |
| 357 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 358 | |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 359 | case PVR_440EP_RA: |
| 360 | puts("EP Rev. A"); |
| 361 | break; |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 362 | |
Stefan Roese | 9a8d82f | 2005-10-04 15:00:30 +0200 | [diff] [blame] | 363 | #ifdef CONFIG_440EP |
| 364 | case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 365 | puts("EP Rev. B"); |
| 366 | break; |
Stefan Roese | 512f8d5 | 2006-05-10 14:10:41 +0200 | [diff] [blame] | 367 | |
| 368 | case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */ |
| 369 | puts("EP Rev. C"); |
| 370 | break; |
Stefan Roese | 9a8d82f | 2005-10-04 15:00:30 +0200 | [diff] [blame] | 371 | #endif /* CONFIG_440EP */ |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 372 | |
Stefan Roese | 9a8d82f | 2005-10-04 15:00:30 +0200 | [diff] [blame] | 373 | #ifdef CONFIG_440GR |
| 374 | case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */ |
| 375 | puts("GR Rev. A"); |
| 376 | break; |
Stefan Roese | 512f8d5 | 2006-05-10 14:10:41 +0200 | [diff] [blame] | 377 | |
Stefan Roese | 5770a1e | 2006-05-18 19:21:53 +0200 | [diff] [blame] | 378 | case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */ |
Stefan Roese | 512f8d5 | 2006-05-10 14:10:41 +0200 | [diff] [blame] | 379 | puts("GR Rev. B"); |
| 380 | break; |
Stefan Roese | 9a8d82f | 2005-10-04 15:00:30 +0200 | [diff] [blame] | 381 | #endif /* CONFIG_440GR */ |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 382 | #endif /* CONFIG_440 */ |
| 383 | |
Stefan Roese | 2902fad | 2007-01-31 16:56:10 +0100 | [diff] [blame] | 384 | #ifdef CONFIG_440EPX |
| 385 | case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ |
Stefan Roese | edf0b54 | 2006-10-18 15:59:35 +0200 | [diff] [blame] | 386 | puts("EPx Rev. A"); |
| 387 | strcpy(addstr, "Security/Kasumi support"); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 388 | break; |
| 389 | |
Stefan Roese | 2902fad | 2007-01-31 16:56:10 +0100 | [diff] [blame] | 390 | case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ |
Stefan Roese | edf0b54 | 2006-10-18 15:59:35 +0200 | [diff] [blame] | 391 | puts("EPx Rev. A"); |
| 392 | strcpy(addstr, "No Security/Kasumi support"); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 393 | break; |
Stefan Roese | 2902fad | 2007-01-31 16:56:10 +0100 | [diff] [blame] | 394 | #endif /* CONFIG_440EPX */ |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 395 | |
Stefan Roese | 2902fad | 2007-01-31 16:56:10 +0100 | [diff] [blame] | 396 | #ifdef CONFIG_440GRX |
| 397 | case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ |
Stefan Roese | edf0b54 | 2006-10-18 15:59:35 +0200 | [diff] [blame] | 398 | puts("GRx Rev. A"); |
| 399 | strcpy(addstr, "Security/Kasumi support"); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 400 | break; |
| 401 | |
Stefan Roese | 2902fad | 2007-01-31 16:56:10 +0100 | [diff] [blame] | 402 | case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ |
Stefan Roese | edf0b54 | 2006-10-18 15:59:35 +0200 | [diff] [blame] | 403 | puts("GRx Rev. A"); |
| 404 | strcpy(addstr, "No Security/Kasumi support"); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 405 | break; |
Stefan Roese | 2902fad | 2007-01-31 16:56:10 +0100 | [diff] [blame] | 406 | #endif /* CONFIG_440GRX */ |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 407 | |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 408 | case PVR_440SP_6_RAB: |
| 409 | puts("SP Rev. A/B"); |
| 410 | strcpy(addstr, "RAID 6 support"); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 411 | break; |
| 412 | |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 413 | case PVR_440SP_RAB: |
| 414 | puts("SP Rev. A/B"); |
| 415 | strcpy(addstr, "No RAID 6 support"); |
| 416 | break; |
| 417 | |
| 418 | case PVR_440SP_6_RC: |
| 419 | puts("SP Rev. C"); |
| 420 | strcpy(addstr, "RAID 6 support"); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 421 | break; |
| 422 | |
Stefan Roese | e732fae | 2006-11-28 16:09:24 +0100 | [diff] [blame] | 423 | case PVR_440SP_RC: |
| 424 | puts("SP Rev. C"); |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 425 | strcpy(addstr, "No RAID 6 support"); |
| 426 | break; |
| 427 | |
| 428 | case PVR_440SPe_6_RA: |
| 429 | puts("SPe Rev. A"); |
| 430 | strcpy(addstr, "RAID 6 support"); |
Stefan Roese | e732fae | 2006-11-28 16:09:24 +0100 | [diff] [blame] | 431 | break; |
| 432 | |
Marian Balakowicz | 6c5879f | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 433 | case PVR_440SPe_RA: |
Marian Balakowicz | fe84b48 | 2006-07-03 23:42:36 +0200 | [diff] [blame] | 434 | puts("SPe Rev. A"); |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 435 | strcpy(addstr, "No RAID 6 support"); |
| 436 | break; |
| 437 | |
| 438 | case PVR_440SPe_6_RB: |
| 439 | puts("SPe Rev. B"); |
| 440 | strcpy(addstr, "RAID 6 support"); |
Marian Balakowicz | 6c5879f | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 441 | break; |
Marian Balakowicz | fe84b48 | 2006-07-03 23:42:36 +0200 | [diff] [blame] | 442 | |
Marian Balakowicz | 6c5879f | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 443 | case PVR_440SPe_RB: |
Marian Balakowicz | fe84b48 | 2006-07-03 23:42:36 +0200 | [diff] [blame] | 444 | puts("SPe Rev. B"); |
Stefan Roese | 9598177 | 2007-01-13 08:01:03 +0100 | [diff] [blame] | 445 | strcpy(addstr, "No RAID 6 support"); |
Marian Balakowicz | 6c5879f | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 446 | break; |
Marian Balakowicz | fe84b48 | 2006-07-03 23:42:36 +0200 | [diff] [blame] | 447 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 448 | default: |
Stefan Roese | 17f50f22 | 2005-08-04 17:09:16 +0200 | [diff] [blame] | 449 | printf (" UNKNOWN (PVR=%08x)", pvr); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 450 | break; |
| 451 | } |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 452 | |
| 453 | printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), |
Stefan Roese | e01bd21 | 2007-03-21 13:38:59 +0100 | [diff] [blame] | 454 | sys_info.freqPLB / 1000000, |
| 455 | get_OPB_freq() / 1000000, |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame^] | 456 | sys_info.freqEBC / 1000000); |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 457 | |
Stefan Roese | edf0b54 | 2006-10-18 15:59:35 +0200 | [diff] [blame] | 458 | if (addstr[0] != 0) |
| 459 | printf(" %s\n", addstr); |
| 460 | |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 461 | #if defined(I2C_BOOTROM) |
| 462 | printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis"); |
Stefan Roese | 90e6f41 | 2007-04-18 12:05:59 +0200 | [diff] [blame] | 463 | #endif /* I2C_BOOTROM */ |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 464 | #if defined(SDR0_PINSTP_SHIFT) |
Benoît Monin | e3cbe1f | 2007-06-04 08:36:05 +0200 | [diff] [blame] | 465 | printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]); |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 466 | printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); |
Wolfgang Denk | ba999c5 | 2006-10-20 17:54:33 +0200 | [diff] [blame] | 467 | #endif /* SDR0_PINSTP_SHIFT */ |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 468 | |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame^] | 469 | #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 470 | printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis"); |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 471 | #endif |
| 472 | |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 473 | #if defined(PCI_ASYNC) |
| 474 | if (pci_async_enabled()) { |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 475 | printf (", PCI async ext clock used"); |
| 476 | } else { |
| 477 | printf (", PCI sync clock at %lu MHz", |
| 478 | sys_info.freqPLB / sys_info.pllPciDiv / 1000000); |
| 479 | } |
| 480 | #endif |
| 481 | |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame^] | 482 | #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 483 | putc('\n'); |
| 484 | #endif |
| 485 | |
Stefan Roese | dbbd125 | 2007-10-05 17:10:59 +0200 | [diff] [blame^] | 486 | #if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 487 | printf (" 16 kB I-Cache 16 kB D-Cache"); |
| 488 | #elif defined(CONFIG_440) |
| 489 | printf (" 32 kB I-Cache 32 kB D-Cache"); |
| 490 | #else |
| 491 | printf (" 16 kB I-Cache %d kB D-Cache", |
| 492 | ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8); |
| 493 | #endif |
| 494 | #endif /* !defined(CONFIG_IOP480) */ |
| 495 | |
| 496 | #if defined(CONFIG_IOP480) |
| 497 | printf ("PLX IOP480 (PVR=%08x)", pvr); |
| 498 | printf (" at %s MHz:", strmhz(buf, clock)); |
| 499 | printf (" %u kB I-Cache", 4); |
| 500 | printf (" %u kB D-Cache", 2); |
| 501 | #endif |
| 502 | |
| 503 | #endif /* !defined(CONFIG_405) */ |
| 504 | |
| 505 | putc ('\n'); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 506 | |
| 507 | return 0; |
| 508 | } |
| 509 | |
Rafal Jaworowski | 692519b | 2006-08-10 12:43:17 +0200 | [diff] [blame] | 510 | #if defined (CONFIG_440SPE) |
| 511 | int ppc440spe_revB() { |
| 512 | unsigned int pvr; |
| 513 | |
| 514 | pvr = get_pvr(); |
Stefan Roese | 5a5c569 | 2007-01-15 09:46:29 +0100 | [diff] [blame] | 515 | if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB)) |
Rafal Jaworowski | 692519b | 2006-08-10 12:43:17 +0200 | [diff] [blame] | 516 | return 1; |
| 517 | else |
| 518 | return 0; |
| 519 | } |
| 520 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 521 | |
| 522 | /* ------------------------------------------------------------------------- */ |
| 523 | |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 524 | int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 525 | { |
Stefan Roese | 1f94d16 | 2006-11-27 14:48:41 +0100 | [diff] [blame] | 526 | #if defined(CONFIG_BOARD_RESET) |
| 527 | board_reset(); |
Stefan Roese | 1729b92 | 2006-11-27 14:52:04 +0100 | [diff] [blame] | 528 | #else |
Stefan Roese | 1c2ce22 | 2006-11-27 14:12:17 +0100 | [diff] [blame] | 529 | #if defined(CFG_4xx_RESET_TYPE) |
| 530 | mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28); |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 531 | #else |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 532 | /* |
| 533 | * Initiate system reset in debug control register DBCR |
| 534 | */ |
Stefan Roese | f344386 | 2006-10-07 11:30:52 +0200 | [diff] [blame] | 535 | mtspr(dbcr0, 0x30000000); |
Stefan Roese | 1729b92 | 2006-11-27 14:52:04 +0100 | [diff] [blame] | 536 | #endif /* defined(CFG_4xx_RESET_TYPE) */ |
Stefan Roese | f344386 | 2006-10-07 11:30:52 +0200 | [diff] [blame] | 537 | #endif /* defined(CONFIG_BOARD_RESET) */ |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 538 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 539 | return 1; |
| 540 | } |
| 541 | |
| 542 | #if defined(CONFIG_440) |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 543 | static int do_chip_reset (unsigned long sys0, unsigned long sys1) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 544 | { |
wdenk | 4d81677 | 2003-09-03 14:03:26 +0000 | [diff] [blame] | 545 | /* Changes to cpc0_sys0 and cpc0_sys1 require chip |
| 546 | * reset. |
| 547 | */ |
| 548 | mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ |
| 549 | mtdcr (cpc0_sys0, sys0); |
| 550 | mtdcr (cpc0_sys1, sys1); |
| 551 | mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ |
| 552 | mtspr (dbcr0, 0x20000000); /* Reset the chip */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 553 | |
wdenk | 4d81677 | 2003-09-03 14:03:26 +0000 | [diff] [blame] | 554 | return 1; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 555 | } |
| 556 | #endif |
| 557 | |
| 558 | |
| 559 | /* |
| 560 | * Get timebase clock frequency |
| 561 | */ |
| 562 | unsigned long get_tbclk (void) |
| 563 | { |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 564 | #if !defined(CONFIG_IOP480) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 565 | sys_info_t sys_info; |
| 566 | |
| 567 | get_sys_info(&sys_info); |
| 568 | return (sys_info.freqProcessor); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 569 | #else |
Stefan Roese | 3d9569b | 2005-11-27 19:36:26 +0100 | [diff] [blame] | 570 | return (66000000); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 571 | #endif |
| 572 | |
| 573 | } |
| 574 | |
| 575 | |
| 576 | #if defined(CONFIG_WATCHDOG) |
| 577 | void |
| 578 | watchdog_reset(void) |
| 579 | { |
| 580 | int re_enable = disable_interrupts(); |
| 581 | reset_4xx_watchdog(); |
| 582 | if (re_enable) enable_interrupts(); |
| 583 | } |
| 584 | |
| 585 | void |
| 586 | reset_4xx_watchdog(void) |
| 587 | { |
| 588 | /* |
| 589 | * Clear TSR(WIS) bit |
| 590 | */ |
| 591 | mtspr(tsr, 0x40000000); |
| 592 | } |
| 593 | #endif /* CONFIG_WATCHDOG */ |