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wdenkc6097192002-11-03 00:24:07 +00001/*
Stefan Roesedbbd1252007-10-05 17:10:59 +02002 * (C) Copyright 2000-2007
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
wdenkc6097192002-11-03 00:24:07 +000025 * CPU specific code
26 *
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
29 *
30 * minor modifications by
31 * Wolfgang Denk <wd@denx.de>
32 */
33
34#include <common.h>
35#include <watchdog.h>
36#include <command.h>
37#include <asm/cache.h>
38#include <ppc4xx.h>
39
Wolfgang Denkd87080b2006-03-31 18:32:53 +020040#if !defined(CONFIG_405)
41DECLARE_GLOBAL_DATA_PTR;
42#endif
43
Stefan Roesef3443862006-10-07 11:30:52 +020044#if defined(CONFIG_BOARD_RESET)
45void board_reset(void);
46#endif
47
Stefan Roese887e2ec2006-09-07 11:51:23 +020048#if defined(CONFIG_405GP) || \
49 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
50 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010051
52#define PCI_ASYNC
53
54int pci_async_enabled(void)
55{
56#if defined(CONFIG_405GP)
57 return (mfdcr(strap) & PSR_PCI_ASYNC_EN);
58#endif
59
Stefan Roese887e2ec2006-09-07 11:51:23 +020060#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
61 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010062 unsigned long val;
63
Wolfgang Denk74812662005-12-12 16:06:05 +010064 mfsdr(sdr_sdstp1, val);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010065 return (val & SDR0_SDSTP1_PAME_MASK);
66#endif
67}
68#endif
69
Stefan Roesedbbd1252007-10-05 17:10:59 +020070#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
71 !defined(CONFIG_405) && !defined(CONFIG_405EX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010072int pci_arbiter_enabled(void)
73{
74#if defined(CONFIG_405GP)
75 return (mfdcr(strap) & PSR_PCI_ARBIT_EN);
76#endif
77
78#if defined(CONFIG_405EP)
79 return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN);
80#endif
81
82#if defined(CONFIG_440GP)
83 return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
84#endif
85
Stefan Roese7372ca62007-02-02 12:44:22 +010086#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010087 unsigned long val;
88
Stefan Roese7372ca62007-02-02 12:44:22 +010089 mfsdr(sdr_xcr, val);
90 return (val & 0x80000000);
91#endif
92#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
93 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
94 unsigned long val;
95
96 mfsdr(sdr_pci0, val);
97 return (val & 0x80000000);
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010098#endif
99}
100#endif
101
Stefan Roese887e2ec2006-09-07 11:51:23 +0200102#if defined(CONFIG_405EP) || defined(CONFIG_440GX) || \
103 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
104 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200105 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
106 defined(CONFIG_405EX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100107
108#define I2C_BOOTROM
109
110int i2c_bootrom_enabled(void)
111{
112#if defined(CONFIG_405EP)
113 return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200114#else
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100115 unsigned long val;
116
117 mfsdr(sdr_sdcs, val);
118 return (val & SDR0_SDCS_SDD);
119#endif
120}
Stefan Roese90e6f412007-04-18 12:05:59 +0200121#endif
Stefan Roese887e2ec2006-09-07 11:51:23 +0200122
123#if defined(CONFIG_440GX)
124#define SDR0_PINSTP_SHIFT 29
125static char *bootstrap_str[] = {
126 "EBC (16 bits)",
127 "EBC (8 bits)",
128 "EBC (32 bits)",
129 "EBC (8 bits)",
130 "PCI",
131 "I2C (Addr 0x54)",
132 "Reserved",
133 "I2C (Addr 0x50)",
134};
Benoît Monine3cbe1f2007-06-04 08:36:05 +0200135static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
Stefan Roese887e2ec2006-09-07 11:51:23 +0200136#endif
137
138#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
139#define SDR0_PINSTP_SHIFT 30
140static char *bootstrap_str[] = {
141 "EBC (8 bits)",
142 "PCI",
143 "I2C (Addr 0x54)",
144 "I2C (Addr 0x50)",
145};
Benoît Monine3cbe1f2007-06-04 08:36:05 +0200146static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
Stefan Roese887e2ec2006-09-07 11:51:23 +0200147#endif
148
149#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
150#define SDR0_PINSTP_SHIFT 29
151static char *bootstrap_str[] = {
152 "EBC (8 bits)",
153 "PCI",
154 "NAND (8 bits)",
155 "EBC (16 bits)",
156 "EBC (16 bits)",
157 "I2C (Addr 0x54)",
158 "PCI",
159 "I2C (Addr 0x52)",
160};
Benoît Monine3cbe1f2007-06-04 08:36:05 +0200161static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
Stefan Roese887e2ec2006-09-07 11:51:23 +0200162#endif
163
164#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
165#define SDR0_PINSTP_SHIFT 29
166static char *bootstrap_str[] = {
167 "EBC (8 bits)",
168 "EBC (16 bits)",
169 "EBC (16 bits)",
170 "NAND (8 bits)",
171 "PCI",
172 "I2C (Addr 0x54)",
173 "PCI",
174 "I2C (Addr 0x52)",
175};
Benoît Monine3cbe1f2007-06-04 08:36:05 +0200176static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
Stefan Roese887e2ec2006-09-07 11:51:23 +0200177#endif
178
Stefan Roese90e6f412007-04-18 12:05:59 +0200179#if defined(CONFIG_405EZ)
180#define SDR0_PINSTP_SHIFT 28
181static char *bootstrap_str[] = {
182 "EBC (8 bits)",
183 "SPI (fast)",
184 "NAND (512 page, 4 addr cycle)",
185 "I2C (Addr 0x50)",
186 "EBC (32 bits)",
187 "I2C (Addr 0x50)",
188 "NAND (2K page, 5 addr cycle)",
189 "I2C (Addr 0x50)",
190 "EBC (16 bits)",
191 "Reserved",
192 "NAND (2K page, 4 addr cycle)",
193 "I2C (Addr 0x50)",
194 "NAND (512 page, 3 addr cycle)",
195 "I2C (Addr 0x50)",
196 "SPI (slow)",
197 "I2C (Addr 0x50)",
198};
Benoît Monine3cbe1f2007-06-04 08:36:05 +0200199static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
200 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
Stefan Roese90e6f412007-04-18 12:05:59 +0200201#endif
202
Stefan Roesedbbd1252007-10-05 17:10:59 +0200203#if defined(CONFIG_405EX)
204#define SDR0_PINSTP_SHIFT 29
205static char *bootstrap_str[] = {
206 "EBC (8 bits)",
207 "EBC (16 bits)",
208 "EBC (16 bits)",
209 "NAND (8 bits)",
210 "NAND (8 bits)",
211 "I2C (Addr 0x54)",
212 "EBC (8 bits)",
213 "I2C (Addr 0x52)",
214};
215static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
216#endif
217
Stefan Roese887e2ec2006-09-07 11:51:23 +0200218#if defined(SDR0_PINSTP_SHIFT)
219static int bootstrap_option(void)
220{
221 unsigned long val;
222
Stefan Roese90e6f412007-04-18 12:05:59 +0200223 mfsdr(SDR_PINSTP, val);
224 return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200225}
226#endif /* SDR0_PINSTP_SHIFT */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100227
Stefan Roese3d9569b2005-11-27 19:36:26 +0100228
229#if defined(CONFIG_440)
230static int do_chip_reset(unsigned long sys0, unsigned long sys1);
231#endif
232
wdenkc6097192002-11-03 00:24:07 +0000233
234int checkcpu (void)
235{
Stefan Roese3d9569b2005-11-27 19:36:26 +0100236#if !defined(CONFIG_405) /* not used on Xilinx 405 FPGA implementations */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100237 uint pvr = get_pvr();
wdenkc6097192002-11-03 00:24:07 +0000238 ulong clock = gd->cpu_clk;
239 char buf[32];
wdenkc6097192002-11-03 00:24:07 +0000240
Stefan Roese3d9569b2005-11-27 19:36:26 +0100241#if !defined(CONFIG_IOP480)
Wolfgang Denkba999c52006-10-20 17:54:33 +0200242 char addstr[64] = "";
Stefan Roese3d9569b2005-11-27 19:36:26 +0100243 sys_info_t sys_info;
wdenkc6097192002-11-03 00:24:07 +0000244
245 puts ("CPU: ");
246
247 get_sys_info(&sys_info);
248
Stefan Roese3d9569b2005-11-27 19:36:26 +0100249 puts("AMCC PowerPC 4");
250
Stefan Roesee01bd212007-03-21 13:38:59 +0100251#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200252 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
253 defined(CONFIG_405EX)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100254 puts("05");
wdenkc6097192002-11-03 00:24:07 +0000255#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100256#if defined(CONFIG_440)
257 puts("40");
wdenkc6097192002-11-03 00:24:07 +0000258#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100259
wdenkc6097192002-11-03 00:24:07 +0000260 switch (pvr) {
261 case PVR_405GP_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100262 puts("GP Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000263 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100264
wdenkc6097192002-11-03 00:24:07 +0000265 case PVR_405GP_RC:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100266 puts("GP Rev. C");
wdenkc6097192002-11-03 00:24:07 +0000267 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100268
wdenkc6097192002-11-03 00:24:07 +0000269 case PVR_405GP_RD:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100270 puts("GP Rev. D");
wdenkc6097192002-11-03 00:24:07 +0000271 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100272
wdenk42dfe7a2004-03-14 22:25:36 +0000273#ifdef CONFIG_405GP
Stefan Roese3d9569b2005-11-27 19:36:26 +0100274 case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
275 puts("GP Rev. E");
wdenkc6097192002-11-03 00:24:07 +0000276 break;
277#endif
Stefan Roese3d9569b2005-11-27 19:36:26 +0100278
wdenkc6097192002-11-03 00:24:07 +0000279 case PVR_405CR_RA:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100280 puts("CR Rev. A");
wdenkc6097192002-11-03 00:24:07 +0000281 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100282
wdenkc6097192002-11-03 00:24:07 +0000283 case PVR_405CR_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100284 puts("CR Rev. B");
285 break;
286
287#ifdef CONFIG_405CR
288 case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
289 puts("CR Rev. C");
290 break;
291#endif
292
293 case PVR_405GPR_RB:
294 puts("GPr Rev. B");
295 break;
296
stroeseb867d702003-05-23 11:18:02 +0000297 case PVR_405EP_RB:
Stefan Roese3d9569b2005-11-27 19:36:26 +0100298 puts("EP Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000299 break;
wdenkc6097192002-11-03 00:24:07 +0000300
Stefan Roesee01bd212007-03-21 13:38:59 +0100301 case PVR_405EZ_RA:
302 puts("EZ Rev. A");
303 break;
304
Stefan Roesedbbd1252007-10-05 17:10:59 +0200305 case PVR_405EX1_RA:
306 puts("EX Rev. A");
307 strcpy(addstr, "Security support");
308 break;
309
310 case PVR_405EX2_RA:
311 puts("EX Rev. A");
312 strcpy(addstr, "No Security support");
313 break;
314
315 case PVR_405EXR1_RA:
316 puts("EXr Rev. A");
317 strcpy(addstr, "Security support");
318 break;
319
320 case PVR_405EXR2_RA:
321 puts("EXr Rev. A");
322 strcpy(addstr, "No Security support");
323 break;
324
wdenkc6097192002-11-03 00:24:07 +0000325#if defined(CONFIG_440)
wdenk8bde7f72003-06-27 21:31:46 +0000326 case PVR_440GP_RB:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200327 puts("GP Rev. B");
wdenk4d816772003-09-03 14:03:26 +0000328 /* See errata 1.12: CHIP_4 */
329 if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) ||
330 (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){
331 puts ( "\n\t CPC0_SYSx DCRs corrupted. "
332 "Resetting chip ...\n");
333 udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
334 do_chip_reset ( mfdcr(cpc0_strp0),
335 mfdcr(cpc0_strp1) );
336 }
wdenkc6097192002-11-03 00:24:07 +0000337 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100338
wdenk8bde7f72003-06-27 21:31:46 +0000339 case PVR_440GP_RC:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200340 puts("GP Rev. C");
wdenkba56f622004-02-06 23:19:44 +0000341 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100342
wdenkba56f622004-02-06 23:19:44 +0000343 case PVR_440GX_RA:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200344 puts("GX Rev. A");
wdenkba56f622004-02-06 23:19:44 +0000345 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100346
wdenkba56f622004-02-06 23:19:44 +0000347 case PVR_440GX_RB:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200348 puts("GX Rev. B");
wdenkc6097192002-11-03 00:24:07 +0000349 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100350
stroese0a7c5392005-04-07 05:33:41 +0000351 case PVR_440GX_RC:
Stefan Roesec157d8e2005-08-01 16:41:48 +0200352 puts("GX Rev. C");
stroese0a7c5392005-04-07 05:33:41 +0000353 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100354
Stefan Roese57275b62005-11-01 10:08:03 +0100355 case PVR_440GX_RF:
356 puts("GX Rev. F");
357 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100358
Stefan Roesec157d8e2005-08-01 16:41:48 +0200359 case PVR_440EP_RA:
360 puts("EP Rev. A");
361 break;
Stefan Roese3d9569b2005-11-27 19:36:26 +0100362
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200363#ifdef CONFIG_440EP
364 case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200365 puts("EP Rev. B");
366 break;
Stefan Roese512f8d52006-05-10 14:10:41 +0200367
368 case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
369 puts("EP Rev. C");
370 break;
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200371#endif /* CONFIG_440EP */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100372
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200373#ifdef CONFIG_440GR
374 case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
375 puts("GR Rev. A");
376 break;
Stefan Roese512f8d52006-05-10 14:10:41 +0200377
Stefan Roese5770a1e2006-05-18 19:21:53 +0200378 case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
Stefan Roese512f8d52006-05-10 14:10:41 +0200379 puts("GR Rev. B");
380 break;
Stefan Roese9a8d82f2005-10-04 15:00:30 +0200381#endif /* CONFIG_440GR */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100382#endif /* CONFIG_440 */
383
Stefan Roese2902fad2007-01-31 16:56:10 +0100384#ifdef CONFIG_440EPX
385 case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200386 puts("EPx Rev. A");
387 strcpy(addstr, "Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200388 break;
389
Stefan Roese2902fad2007-01-31 16:56:10 +0100390 case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200391 puts("EPx Rev. A");
392 strcpy(addstr, "No Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200393 break;
Stefan Roese2902fad2007-01-31 16:56:10 +0100394#endif /* CONFIG_440EPX */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200395
Stefan Roese2902fad2007-01-31 16:56:10 +0100396#ifdef CONFIG_440GRX
397 case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200398 puts("GRx Rev. A");
399 strcpy(addstr, "Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200400 break;
401
Stefan Roese2902fad2007-01-31 16:56:10 +0100402 case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
Stefan Roeseedf0b542006-10-18 15:59:35 +0200403 puts("GRx Rev. A");
404 strcpy(addstr, "No Security/Kasumi support");
Stefan Roese887e2ec2006-09-07 11:51:23 +0200405 break;
Stefan Roese2902fad2007-01-31 16:56:10 +0100406#endif /* CONFIG_440GRX */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200407
Stefan Roese95981772007-01-13 08:01:03 +0100408 case PVR_440SP_6_RAB:
409 puts("SP Rev. A/B");
410 strcpy(addstr, "RAID 6 support");
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100411 break;
412
Stefan Roese95981772007-01-13 08:01:03 +0100413 case PVR_440SP_RAB:
414 puts("SP Rev. A/B");
415 strcpy(addstr, "No RAID 6 support");
416 break;
417
418 case PVR_440SP_6_RC:
419 puts("SP Rev. C");
420 strcpy(addstr, "RAID 6 support");
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100421 break;
422
Stefan Roesee732fae2006-11-28 16:09:24 +0100423 case PVR_440SP_RC:
424 puts("SP Rev. C");
Stefan Roese95981772007-01-13 08:01:03 +0100425 strcpy(addstr, "No RAID 6 support");
426 break;
427
428 case PVR_440SPe_6_RA:
429 puts("SPe Rev. A");
430 strcpy(addstr, "RAID 6 support");
Stefan Roesee732fae2006-11-28 16:09:24 +0100431 break;
432
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200433 case PVR_440SPe_RA:
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200434 puts("SPe Rev. A");
Stefan Roese95981772007-01-13 08:01:03 +0100435 strcpy(addstr, "No RAID 6 support");
436 break;
437
438 case PVR_440SPe_6_RB:
439 puts("SPe Rev. B");
440 strcpy(addstr, "RAID 6 support");
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200441 break;
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200442
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200443 case PVR_440SPe_RB:
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200444 puts("SPe Rev. B");
Stefan Roese95981772007-01-13 08:01:03 +0100445 strcpy(addstr, "No RAID 6 support");
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200446 break;
Marian Balakowiczfe84b482006-07-03 23:42:36 +0200447
wdenk8bde7f72003-06-27 21:31:46 +0000448 default:
Stefan Roese17f50f222005-08-04 17:09:16 +0200449 printf (" UNKNOWN (PVR=%08x)", pvr);
wdenkc6097192002-11-03 00:24:07 +0000450 break;
451 }
Stefan Roese3d9569b2005-11-27 19:36:26 +0100452
453 printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
Stefan Roesee01bd212007-03-21 13:38:59 +0100454 sys_info.freqPLB / 1000000,
455 get_OPB_freq() / 1000000,
Stefan Roesedbbd1252007-10-05 17:10:59 +0200456 sys_info.freqEBC / 1000000);
Stefan Roese3d9569b2005-11-27 19:36:26 +0100457
Stefan Roeseedf0b542006-10-18 15:59:35 +0200458 if (addstr[0] != 0)
459 printf(" %s\n", addstr);
460
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100461#if defined(I2C_BOOTROM)
462 printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
Stefan Roese90e6f412007-04-18 12:05:59 +0200463#endif /* I2C_BOOTROM */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200464#if defined(SDR0_PINSTP_SHIFT)
Benoît Monine3cbe1f2007-06-04 08:36:05 +0200465 printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
Stefan Roese887e2ec2006-09-07 11:51:23 +0200466 printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
Wolfgang Denkba999c52006-10-20 17:54:33 +0200467#endif /* SDR0_PINSTP_SHIFT */
Stefan Roese3d9569b2005-11-27 19:36:26 +0100468
Stefan Roesedbbd1252007-10-05 17:10:59 +0200469#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100470 printf (" Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
Stefan Roese3d9569b2005-11-27 19:36:26 +0100471#endif
472
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100473#if defined(PCI_ASYNC)
474 if (pci_async_enabled()) {
Stefan Roese3d9569b2005-11-27 19:36:26 +0100475 printf (", PCI async ext clock used");
476 } else {
477 printf (", PCI sync clock at %lu MHz",
478 sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
479 }
480#endif
481
Stefan Roesedbbd1252007-10-05 17:10:59 +0200482#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100483 putc('\n');
484#endif
485
Stefan Roesedbbd1252007-10-05 17:10:59 +0200486#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100487 printf (" 16 kB I-Cache 16 kB D-Cache");
488#elif defined(CONFIG_440)
489 printf (" 32 kB I-Cache 32 kB D-Cache");
490#else
491 printf (" 16 kB I-Cache %d kB D-Cache",
492 ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
493#endif
494#endif /* !defined(CONFIG_IOP480) */
495
496#if defined(CONFIG_IOP480)
497 printf ("PLX IOP480 (PVR=%08x)", pvr);
498 printf (" at %s MHz:", strmhz(buf, clock));
499 printf (" %u kB I-Cache", 4);
500 printf (" %u kB D-Cache", 2);
501#endif
502
503#endif /* !defined(CONFIG_405) */
504
505 putc ('\n');
wdenkc6097192002-11-03 00:24:07 +0000506
507 return 0;
508}
509
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200510#if defined (CONFIG_440SPE)
511int ppc440spe_revB() {
512 unsigned int pvr;
513
514 pvr = get_pvr();
Stefan Roese5a5c5692007-01-15 09:46:29 +0100515 if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
Rafal Jaworowski692519b2006-08-10 12:43:17 +0200516 return 1;
517 else
518 return 0;
519}
520#endif
wdenkc6097192002-11-03 00:24:07 +0000521
522/* ------------------------------------------------------------------------- */
523
wdenk8bde7f72003-06-27 21:31:46 +0000524int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
wdenkc6097192002-11-03 00:24:07 +0000525{
Stefan Roese1f94d162006-11-27 14:48:41 +0100526#if defined(CONFIG_BOARD_RESET)
527 board_reset();
Stefan Roese1729b922006-11-27 14:52:04 +0100528#else
Stefan Roese1c2ce222006-11-27 14:12:17 +0100529#if defined(CFG_4xx_RESET_TYPE)
530 mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
Stefan Roesec157d8e2005-08-01 16:41:48 +0200531#else
wdenk8bde7f72003-06-27 21:31:46 +0000532 /*
533 * Initiate system reset in debug control register DBCR
534 */
Stefan Roesef3443862006-10-07 11:30:52 +0200535 mtspr(dbcr0, 0x30000000);
Stefan Roese1729b922006-11-27 14:52:04 +0100536#endif /* defined(CFG_4xx_RESET_TYPE) */
Stefan Roesef3443862006-10-07 11:30:52 +0200537#endif /* defined(CONFIG_BOARD_RESET) */
Stefan Roesec157d8e2005-08-01 16:41:48 +0200538
wdenkc6097192002-11-03 00:24:07 +0000539 return 1;
540}
541
542#if defined(CONFIG_440)
Stefan Roese3d9569b2005-11-27 19:36:26 +0100543static int do_chip_reset (unsigned long sys0, unsigned long sys1)
wdenkc6097192002-11-03 00:24:07 +0000544{
wdenk4d816772003-09-03 14:03:26 +0000545 /* Changes to cpc0_sys0 and cpc0_sys1 require chip
546 * reset.
547 */
548 mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */
549 mtdcr (cpc0_sys0, sys0);
550 mtdcr (cpc0_sys1, sys1);
551 mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */
552 mtspr (dbcr0, 0x20000000); /* Reset the chip */
wdenkc6097192002-11-03 00:24:07 +0000553
wdenk4d816772003-09-03 14:03:26 +0000554 return 1;
wdenkc6097192002-11-03 00:24:07 +0000555}
556#endif
557
558
559/*
560 * Get timebase clock frequency
561 */
562unsigned long get_tbclk (void)
563{
Stefan Roese3d9569b2005-11-27 19:36:26 +0100564#if !defined(CONFIG_IOP480)
wdenkc6097192002-11-03 00:24:07 +0000565 sys_info_t sys_info;
566
567 get_sys_info(&sys_info);
568 return (sys_info.freqProcessor);
wdenkc6097192002-11-03 00:24:07 +0000569#else
Stefan Roese3d9569b2005-11-27 19:36:26 +0100570 return (66000000);
wdenkc6097192002-11-03 00:24:07 +0000571#endif
572
573}
574
575
576#if defined(CONFIG_WATCHDOG)
577void
578watchdog_reset(void)
579{
580 int re_enable = disable_interrupts();
581 reset_4xx_watchdog();
582 if (re_enable) enable_interrupts();
583}
584
585void
586reset_4xx_watchdog(void)
587{
588 /*
589 * Clear TSR(WIS) bit
590 */
591 mtspr(tsr, 0x40000000);
592}
593#endif /* CONFIG_WATCHDOG */