blob: b5f3fd134d410d98e8225e9c6cbd4feb7bdd6278 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Andy Fleming50586ef2008-10-30 16:47:16 -05002/*
Jerry Huangd621da02011-01-06 23:42:19 -06003 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
Yangbo Lu9abf6482020-05-19 11:06:43 +08004 * Copyright 2019-2020 NXP
Andy Fleming50586ef2008-10-30 16:47:16 -05005 * Andy Fleming
6 *
7 * Based vaguely on the pxa mmc code:
8 * (C) Copyright 2003
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
Andy Fleming50586ef2008-10-30 16:47:16 -050010 */
11
12#include <config.h>
13#include <common.h>
14#include <command.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070015#include <cpu_func.h>
Jaehoon Chung915ffa52016-07-19 16:33:36 +090016#include <errno.h>
Anton Vorontsovb33433a2009-06-10 00:25:29 +040017#include <hwconfig.h>
Andy Fleming50586ef2008-10-30 16:47:16 -050018#include <mmc.h>
19#include <part.h>
20#include <malloc.h>
Andy Fleming50586ef2008-10-30 16:47:16 -050021#include <fsl_esdhc.h>
Anton Vorontsovb33433a2009-06-10 00:25:29 +040022#include <fdt_support.h>
Simon Glass90526e92020-05-10 11:39:56 -060023#include <asm/cache.h>
Andy Fleming50586ef2008-10-30 16:47:16 -050024#include <asm/io.h>
Peng Fan96f04072016-03-25 14:16:56 +080025#include <dm.h>
Simon Glass336d4612020-02-03 07:36:16 -070026#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060027#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060028#include <linux/delay.h>
Michael Walleb1ba1462020-09-23 12:42:48 +020029#include <linux/dma-mapping.h>
Michael Walle361a4222020-10-12 10:07:14 +020030#include <sdhci.h>
Andy Fleming50586ef2008-10-30 16:47:16 -050031
Andy Fleming50586ef2008-10-30 16:47:16 -050032DECLARE_GLOBAL_DATA_PTR;
33
34struct fsl_esdhc {
Haijun.Zhang511948b2013-10-30 11:37:55 +080035 uint dsaddr; /* SDMA system address register */
36 uint blkattr; /* Block attributes register */
37 uint cmdarg; /* Command argument register */
38 uint xfertyp; /* Transfer type register */
39 uint cmdrsp0; /* Command response 0 register */
40 uint cmdrsp1; /* Command response 1 register */
41 uint cmdrsp2; /* Command response 2 register */
42 uint cmdrsp3; /* Command response 3 register */
43 uint datport; /* Buffer data port register */
44 uint prsstat; /* Present state register */
45 uint proctl; /* Protocol control register */
46 uint sysctl; /* System Control Register */
47 uint irqstat; /* Interrupt status register */
48 uint irqstaten; /* Interrupt status enable register */
49 uint irqsigen; /* Interrupt signal enable register */
50 uint autoc12err; /* Auto CMD error status register */
51 uint hostcapblt; /* Host controller capabilities register */
52 uint wml; /* Watermark level register */
Yangbo Lu4d8ff422019-06-21 11:42:29 +080053 char reserved1[8]; /* reserved */
Haijun.Zhang511948b2013-10-30 11:37:55 +080054 uint fevt; /* Force event register */
55 uint admaes; /* ADMA error status register */
Michael Walle361a4222020-10-12 10:07:14 +020056 uint adsaddrl; /* ADMA system address low register */
57 uint adsaddrh; /* ADMA system address high register */
58 char reserved2[156];
Haijun.Zhang511948b2013-10-30 11:37:55 +080059 uint hostver; /* Host controller version register */
Yangbo Lu4d8ff422019-06-21 11:42:29 +080060 char reserved3[4]; /* reserved */
Peng Fan59d37822018-01-21 19:00:22 +080061 uint dmaerraddr; /* DMA error address register */
Yangbo Lu4d8ff422019-06-21 11:42:29 +080062 char reserved4[4]; /* reserved */
Peng Fan59d37822018-01-21 19:00:22 +080063 uint dmaerrattr; /* DMA error attribute register */
Yangbo Lu4d8ff422019-06-21 11:42:29 +080064 char reserved5[4]; /* reserved */
Haijun.Zhang511948b2013-10-30 11:37:55 +080065 uint hostcapblt2; /* Host controller capabilities register 2 */
Yangbo Lub1a42472020-09-01 16:58:01 +080066 char reserved6[8]; /* reserved */
67 uint tbctl; /* Tuning block control register */
Yangbo Ludb8f9362020-09-01 16:58:05 +080068 char reserved7[32]; /* reserved */
69 uint sdclkctl; /* SD clock control register */
70 uint sdtimingctl; /* SD timing control register */
71 char reserved8[20]; /* reserved */
72 uint dllcfg0; /* DLL config 0 register */
Yangbo Lu8ee802f2020-10-20 11:04:52 +080073 char reserved9[12]; /* reserved */
74 uint dllstat0; /* DLL status 0 register */
75 char reserved10[664];/* reserved */
Yangbo Lu4d8ff422019-06-21 11:42:29 +080076 uint esdhcctl; /* eSDHC control register */
Andy Fleming50586ef2008-10-30 16:47:16 -050077};
78
Simon Glasse88e1d92017-07-29 11:35:21 -060079struct fsl_esdhc_plat {
80 struct mmc_config cfg;
81 struct mmc mmc;
82};
83
Peng Fan96f04072016-03-25 14:16:56 +080084/**
85 * struct fsl_esdhc_priv
86 *
87 * @esdhc_regs: registers of the sdhc controller
88 * @sdhc_clk: Current clk of the sdhc controller
89 * @bus_width: bus width, 1bit, 4bit or 8bit
90 * @cfg: mmc config
91 * @mmc: mmc
92 * Following is used when Driver Model is enabled for MMC
93 * @dev: pointer for the device
Peng Fan96f04072016-03-25 14:16:56 +080094 * @cd_gpio: gpio for card detection
Peng Fan14831512016-06-15 10:53:02 +080095 * @wp_gpio: gpio for write protection
Peng Fan96f04072016-03-25 14:16:56 +080096 */
97struct fsl_esdhc_priv {
98 struct fsl_esdhc *esdhc_regs;
99 unsigned int sdhc_clk;
Yangbo Luf1bce082019-12-19 18:59:30 +0800100 bool is_sdhc_per_clk;
Peng Fan51313b42018-01-21 19:00:24 +0800101 unsigned int clock;
Yangbo Lu41dec2f2019-10-21 18:09:07 +0800102#if !CONFIG_IS_ENABLED(DM_MMC)
Peng Fan96f04072016-03-25 14:16:56 +0800103 struct mmc *mmc;
Simon Glass653282b2017-07-29 11:35:24 -0600104#endif
Peng Fan96f04072016-03-25 14:16:56 +0800105 struct udevice *dev;
Michael Walle361a4222020-10-12 10:07:14 +0200106 struct sdhci_adma_desc *adma_desc_table;
Michael Walleb1ba1462020-09-23 12:42:48 +0200107 dma_addr_t dma_addr;
Peng Fan96f04072016-03-25 14:16:56 +0800108};
109
Andy Fleming50586ef2008-10-30 16:47:16 -0500110/* Return the XFERTYP flags for a given command and data packet */
Kim Phillipseafa90a2012-10-29 13:34:44 +0000111static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
Andy Fleming50586ef2008-10-30 16:47:16 -0500112{
113 uint xfertyp = 0;
114
115 if (data) {
Dipen Dudhat77c14582009-10-05 15:41:58 +0530116 xfertyp |= XFERTYP_DPSEL;
Michael Walle52faec32020-10-12 10:07:13 +0200117 if (!IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO) &&
118 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK &&
Yangbo Lub1a42472020-09-01 16:58:01 +0800119 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200)
120 xfertyp |= XFERTYP_DMAEN;
Andy Fleming50586ef2008-10-30 16:47:16 -0500121 if (data->blocks > 1) {
122 xfertyp |= XFERTYP_MSBSEL;
123 xfertyp |= XFERTYP_BCEN;
Michael Walle52faec32020-10-12 10:07:13 +0200124 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111))
125 xfertyp |= XFERTYP_AC12EN;
Andy Fleming50586ef2008-10-30 16:47:16 -0500126 }
127
128 if (data->flags & MMC_DATA_READ)
129 xfertyp |= XFERTYP_DTDSEL;
130 }
131
132 if (cmd->resp_type & MMC_RSP_CRC)
133 xfertyp |= XFERTYP_CCCEN;
134 if (cmd->resp_type & MMC_RSP_OPCODE)
135 xfertyp |= XFERTYP_CICEN;
136 if (cmd->resp_type & MMC_RSP_136)
137 xfertyp |= XFERTYP_RSPTYP_136;
138 else if (cmd->resp_type & MMC_RSP_BUSY)
139 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
140 else if (cmd->resp_type & MMC_RSP_PRESENT)
141 xfertyp |= XFERTYP_RSPTYP_48;
142
Jason Liu4571de32011-03-22 01:32:31 +0000143 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
144 xfertyp |= XFERTYP_CMDTYP_ABORT;
Yangbo Lu25503442016-01-21 17:33:19 +0800145
Andy Fleming50586ef2008-10-30 16:47:16 -0500146 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
147}
148
Dipen Dudhat77c14582009-10-05 15:41:58 +0530149/*
150 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
151 */
Simon Glass09b465f2017-07-29 11:35:17 -0600152static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
153 struct mmc_data *data)
Dipen Dudhat77c14582009-10-05 15:41:58 +0530154{
Peng Fan96f04072016-03-25 14:16:56 +0800155 struct fsl_esdhc *regs = priv->esdhc_regs;
Dipen Dudhat77c14582009-10-05 15:41:58 +0530156 uint blocks;
157 char *buffer;
158 uint databuf;
159 uint size;
160 uint irqstat;
Benoît Thébaudeaubcfb3652017-10-29 22:08:58 +0100161 ulong start;
Dipen Dudhat77c14582009-10-05 15:41:58 +0530162
163 if (data->flags & MMC_DATA_READ) {
164 blocks = data->blocks;
165 buffer = data->dest;
166 while (blocks) {
Benoît Thébaudeaubcfb3652017-10-29 22:08:58 +0100167 start = get_timer(0);
Dipen Dudhat77c14582009-10-05 15:41:58 +0530168 size = data->blocksize;
169 irqstat = esdhc_read32(&regs->irqstat);
Benoît Thébaudeaubcfb3652017-10-29 22:08:58 +0100170 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
171 if (get_timer(start) > PIO_TIMEOUT) {
172 printf("\nData Read Failed in PIO Mode.");
173 return;
174 }
Dipen Dudhat77c14582009-10-05 15:41:58 +0530175 }
176 while (size && (!(irqstat & IRQSTAT_TC))) {
177 udelay(100); /* Wait before last byte transfer complete */
178 irqstat = esdhc_read32(&regs->irqstat);
179 databuf = in_le32(&regs->datport);
180 *((uint *)buffer) = databuf;
181 buffer += 4;
182 size -= 4;
183 }
184 blocks--;
185 }
186 } else {
187 blocks = data->blocks;
Wolfgang Denk7b43db92010-05-09 23:52:59 +0200188 buffer = (char *)data->src;
Dipen Dudhat77c14582009-10-05 15:41:58 +0530189 while (blocks) {
Benoît Thébaudeaubcfb3652017-10-29 22:08:58 +0100190 start = get_timer(0);
Dipen Dudhat77c14582009-10-05 15:41:58 +0530191 size = data->blocksize;
192 irqstat = esdhc_read32(&regs->irqstat);
Benoît Thébaudeaubcfb3652017-10-29 22:08:58 +0100193 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
194 if (get_timer(start) > PIO_TIMEOUT) {
195 printf("\nData Write Failed in PIO Mode.");
196 return;
197 }
Dipen Dudhat77c14582009-10-05 15:41:58 +0530198 }
199 while (size && (!(irqstat & IRQSTAT_TC))) {
200 udelay(100); /* Wait before last byte transfer complete */
201 databuf = *((uint *)buffer);
202 buffer += 4;
203 size -= 4;
204 irqstat = esdhc_read32(&regs->irqstat);
205 out_le32(&regs->datport, databuf);
206 }
207 blocks--;
208 }
209 }
210}
Dipen Dudhat77c14582009-10-05 15:41:58 +0530211
Michael Walle7e48a022020-09-23 12:42:49 +0200212static void esdhc_setup_watermark_level(struct fsl_esdhc_priv *priv,
213 struct mmc_data *data)
Andy Fleming50586ef2008-10-30 16:47:16 -0500214{
Peng Fan96f04072016-03-25 14:16:56 +0800215 struct fsl_esdhc *regs = priv->esdhc_regs;
Michael Walle7e48a022020-09-23 12:42:49 +0200216 uint wml_value = data->blocksize / 4;
Andy Fleming50586ef2008-10-30 16:47:16 -0500217
218 if (data->flags & MMC_DATA_READ) {
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530219 if (wml_value > WML_RD_WML_MAX)
220 wml_value = WML_RD_WML_MAX_VAL;
Andy Fleming50586ef2008-10-30 16:47:16 -0500221
Roy Zangab467c52010-02-09 18:23:33 +0800222 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
Andy Fleming50586ef2008-10-30 16:47:16 -0500223 } else {
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530224 if (wml_value > WML_WR_WML_MAX)
225 wml_value = WML_WR_WML_MAX_VAL;
Yangbo Lu0cc127c2019-10-31 18:54:25 +0800226
Roy Zangab467c52010-02-09 18:23:33 +0800227 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
Michael Walle7e48a022020-09-23 12:42:49 +0200228 wml_value << 16);
229 }
230}
Michael Walle7e48a022020-09-23 12:42:49 +0200231
232static void esdhc_setup_dma(struct fsl_esdhc_priv *priv, struct mmc_data *data)
233{
234 uint trans_bytes = data->blocksize * data->blocks;
235 struct fsl_esdhc *regs = priv->esdhc_regs;
Michael Walle361a4222020-10-12 10:07:14 +0200236 phys_addr_t adma_addr;
Michael Walle7e48a022020-09-23 12:42:49 +0200237 void *buf;
238
239 if (data->flags & MMC_DATA_WRITE)
240 buf = (void *)data->src;
241 else
242 buf = data->dest;
243
244 priv->dma_addr = dma_map_single(buf, trans_bytes,
245 mmc_get_dma_dir(data));
Michael Walle361a4222020-10-12 10:07:14 +0200246
247 if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2) &&
248 priv->adma_desc_table) {
249 debug("Using ADMA2\n");
250 /* prefer ADMA2 if it is available */
251 sdhci_prepare_adma_table(priv->adma_desc_table, data,
252 priv->dma_addr);
253
254 adma_addr = virt_to_phys(priv->adma_desc_table);
255 esdhc_write32(&regs->adsaddrl, lower_32_bits(adma_addr));
256 if (IS_ENABLED(CONFIG_DMA_ADDR_T_64BIT))
257 esdhc_write32(&regs->adsaddrh, upper_32_bits(adma_addr));
258 esdhc_clrsetbits32(&regs->proctl, PROCTL_DMAS_MASK,
259 PROCTL_DMAS_ADMA2);
260 } else {
261 debug("Using SDMA\n");
262 if (upper_32_bits(priv->dma_addr))
263 printf("Cannot use 64 bit addresses with SDMA\n");
264 esdhc_write32(&regs->dsaddr, lower_32_bits(priv->dma_addr));
265 esdhc_clrsetbits32(&regs->proctl, PROCTL_DMAS_MASK,
266 PROCTL_DMAS_SDMA);
267 }
268
Michael Walle7e48a022020-09-23 12:42:49 +0200269 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
270}
271
272static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
273 struct mmc_data *data)
274{
275 int timeout;
276 bool is_write = data->flags & MMC_DATA_WRITE;
277 struct fsl_esdhc *regs = priv->esdhc_regs;
278
279 if (is_write && !(esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL)) {
280 printf("Can not write to locked SD card.\n");
281 return -EINVAL;
Andy Fleming50586ef2008-10-30 16:47:16 -0500282 }
283
Michael Walle52faec32020-10-12 10:07:13 +0200284 if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO))
285 esdhc_setup_watermark_level(priv, data);
286 else
287 esdhc_setup_dma(priv, data);
Andy Fleming50586ef2008-10-30 16:47:16 -0500288
289 /* Calculate the timeout period for data transactions */
Priyanka Jainb71ea332011-03-03 09:18:56 +0530290 /*
291 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
292 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
293 * So, Number of SD Clock cycles for 0.25sec should be minimum
294 * (SD Clock/sec * 0.25 sec) SD Clock cycles
Andrew Gabbasovfb823982014-03-24 02:40:41 -0500295 * = (mmc->clock * 1/4) SD Clock cycles
Priyanka Jainb71ea332011-03-03 09:18:56 +0530296 * As 1) >= 2)
Andrew Gabbasovfb823982014-03-24 02:40:41 -0500297 * => (2^(timeout+13)) >= mmc->clock * 1/4
Priyanka Jainb71ea332011-03-03 09:18:56 +0530298 * Taking log2 both the sides
Andrew Gabbasovfb823982014-03-24 02:40:41 -0500299 * => timeout + 13 >= log2(mmc->clock/4)
Priyanka Jainb71ea332011-03-03 09:18:56 +0530300 * Rounding up to next power of 2
Andrew Gabbasovfb823982014-03-24 02:40:41 -0500301 * => timeout + 13 = log2(mmc->clock/4) + 1
302 * => timeout + 13 = fls(mmc->clock/4)
Yangbo Lue978a312015-12-30 14:19:30 +0800303 *
304 * However, the MMC spec "It is strongly recommended for hosts to
305 * implement more than 500ms timeout value even if the card
306 * indicates the 250ms maximum busy length." Even the previous
307 * value of 300ms is known to be insufficient for some cards.
308 * So, we use
309 * => timeout + 13 = fls(mmc->clock/2)
Priyanka Jainb71ea332011-03-03 09:18:56 +0530310 */
Yangbo Lue978a312015-12-30 14:19:30 +0800311 timeout = fls(mmc->clock/2);
Andy Fleming50586ef2008-10-30 16:47:16 -0500312 timeout -= 13;
313
314 if (timeout > 14)
315 timeout = 14;
316
317 if (timeout < 0)
318 timeout = 0;
319
Michael Walle52faec32020-10-12 10:07:13 +0200320 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) &&
321 (timeout == 4 || timeout == 8 || timeout == 12))
Kumar Gala5103a032011-01-29 15:36:10 -0600322 timeout++;
Kumar Gala5103a032011-01-29 15:36:10 -0600323
Michael Walle52faec32020-10-12 10:07:13 +0200324 if (IS_ENABLED(ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE))
325 timeout = 0xE;
326
Stefano Babicc67bee12010-02-05 15:11:27 +0100327 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
Andy Fleming50586ef2008-10-30 16:47:16 -0500328
329 return 0;
330}
331
Andy Fleming50586ef2008-10-30 16:47:16 -0500332/*
333 * Sends a command out on the bus. Takes the mmc pointer,
334 * a command pointer, and an optional data pointer.
335 */
Simon Glass9586aa62017-07-29 11:35:18 -0600336static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
337 struct mmc_cmd *cmd, struct mmc_data *data)
Andy Fleming50586ef2008-10-30 16:47:16 -0500338{
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500339 int err = 0;
Andy Fleming50586ef2008-10-30 16:47:16 -0500340 uint xfertyp;
341 uint irqstat;
Peng Fan51313b42018-01-21 19:00:24 +0800342 u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
Peng Fan96f04072016-03-25 14:16:56 +0800343 struct fsl_esdhc *regs = priv->esdhc_regs;
Fabio Estevam29c2edb2018-11-19 10:31:53 -0200344 unsigned long start;
Andy Fleming50586ef2008-10-30 16:47:16 -0500345
Michael Walle52faec32020-10-12 10:07:13 +0200346 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC111) &&
347 cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
Jerry Huangd621da02011-01-06 23:42:19 -0600348 return 0;
Jerry Huangd621da02011-01-06 23:42:19 -0600349
Stefano Babicc67bee12010-02-05 15:11:27 +0100350 esdhc_write32(&regs->irqstat, -1);
Andy Fleming50586ef2008-10-30 16:47:16 -0500351
352 sync();
353
354 /* Wait for the bus to be idle */
Stefano Babicc67bee12010-02-05 15:11:27 +0100355 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
356 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
357 ;
Andy Fleming50586ef2008-10-30 16:47:16 -0500358
Stefano Babicc67bee12010-02-05 15:11:27 +0100359 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
360 ;
Andy Fleming50586ef2008-10-30 16:47:16 -0500361
362 /* Wait at least 8 SD clock cycles before the next command */
363 /*
364 * Note: This is way more than 8 cycles, but 1ms seems to
365 * resolve timing issues with some cards
366 */
367 udelay(1000);
368
369 /* Set up for a data transfer if we have one */
370 if (data) {
Simon Glass09b465f2017-07-29 11:35:17 -0600371 err = esdhc_setup_data(priv, mmc, data);
Andy Fleming50586ef2008-10-30 16:47:16 -0500372 if(err)
373 return err;
374 }
375
376 /* Figure out the transfer arguments */
377 xfertyp = esdhc_xfertyp(cmd, data);
378
Andrew Gabbasov01b77352013-06-11 10:34:22 -0500379 /* Mask all irqs */
380 esdhc_write32(&regs->irqsigen, 0);
381
Andy Fleming50586ef2008-10-30 16:47:16 -0500382 /* Send the command */
Stefano Babicc67bee12010-02-05 15:11:27 +0100383 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
384 esdhc_write32(&regs->xfertyp, xfertyp);
Dirk Behme7a5b8022012-03-26 03:13:05 +0000385
Yangbo Lub1a42472020-09-01 16:58:01 +0800386 if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
387 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
388 flags = IRQSTAT_BRR;
389
Andy Fleming50586ef2008-10-30 16:47:16 -0500390 /* Wait for the command to complete */
Fabio Estevam29c2edb2018-11-19 10:31:53 -0200391 start = get_timer(0);
392 while (!(esdhc_read32(&regs->irqstat) & flags)) {
393 if (get_timer(start) > 1000) {
394 err = -ETIMEDOUT;
395 goto out;
396 }
397 }
Andy Fleming50586ef2008-10-30 16:47:16 -0500398
Stefano Babicc67bee12010-02-05 15:11:27 +0100399 irqstat = esdhc_read32(&regs->irqstat);
Andy Fleming50586ef2008-10-30 16:47:16 -0500400
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500401 if (irqstat & CMD_ERR) {
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900402 err = -ECOMM;
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500403 goto out;
Dirk Behme7a5b8022012-03-26 03:13:05 +0000404 }
405
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500406 if (irqstat & IRQSTAT_CTOE) {
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900407 err = -ETIMEDOUT;
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500408 goto out;
409 }
Andy Fleming50586ef2008-10-30 16:47:16 -0500410
Dirk Behme7a5b8022012-03-26 03:13:05 +0000411 /* Workaround for ESDHC errata ENGcm03648 */
412 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
Yangbo Lu253d5bd2015-04-15 10:13:12 +0800413 int timeout = 6000;
Dirk Behme7a5b8022012-03-26 03:13:05 +0000414
Yangbo Lu253d5bd2015-04-15 10:13:12 +0800415 /* Poll on DATA0 line for cmd with busy signal for 600 ms */
Dirk Behme7a5b8022012-03-26 03:13:05 +0000416 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
417 PRSSTAT_DAT0)) {
418 udelay(100);
419 timeout--;
420 }
421
422 if (timeout <= 0) {
423 printf("Timeout waiting for DAT0 to go high!\n");
Jaehoon Chung915ffa52016-07-19 16:33:36 +0900424 err = -ETIMEDOUT;
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500425 goto out;
Dirk Behme7a5b8022012-03-26 03:13:05 +0000426 }
427 }
428
Andy Fleming50586ef2008-10-30 16:47:16 -0500429 /* Copy the response to the response buffer */
430 if (cmd->resp_type & MMC_RSP_136) {
431 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
432
Stefano Babicc67bee12010-02-05 15:11:27 +0100433 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
434 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
435 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
436 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
Rabin Vincent998be3d2009-04-05 13:30:56 +0530437 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
438 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
439 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
440 cmd->response[3] = (cmdrsp0 << 8);
Andy Fleming50586ef2008-10-30 16:47:16 -0500441 } else
Stefano Babicc67bee12010-02-05 15:11:27 +0100442 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
Andy Fleming50586ef2008-10-30 16:47:16 -0500443
444 /* Wait until all of the blocks are transferred */
445 if (data) {
Michael Walle52faec32020-10-12 10:07:13 +0200446 if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_USE_PIO)) {
447 esdhc_pio_read_write(priv, data);
448 } else {
449 flags = DATA_COMPLETE;
450 if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
451 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
452 flags = IRQSTAT_BRR;
Yangbo Lub1a42472020-09-01 16:58:01 +0800453
Michael Walle52faec32020-10-12 10:07:13 +0200454 do {
455 irqstat = esdhc_read32(&regs->irqstat);
Andy Fleming50586ef2008-10-30 16:47:16 -0500456
Michael Walle52faec32020-10-12 10:07:13 +0200457 if (irqstat & IRQSTAT_DTOE) {
458 err = -ETIMEDOUT;
459 goto out;
460 }
Frans Meulenbroeks63fb5a72010-07-31 04:45:18 +0000461
Michael Walle52faec32020-10-12 10:07:13 +0200462 if (irqstat & DATA_ERR) {
463 err = -ECOMM;
464 goto out;
465 }
466 } while ((irqstat & flags) != flags);
Ye.Li71689772014-02-20 18:00:57 +0800467
Michael Walle52faec32020-10-12 10:07:13 +0200468 /*
469 * Need invalidate the dcache here again to avoid any
470 * cache-fill during the DMA operations such as the
471 * speculative pre-fetching etc.
472 */
473 dma_unmap_single(priv->dma_addr,
474 data->blocks * data->blocksize,
475 mmc_get_dma_dir(data));
476 }
Andy Fleming50586ef2008-10-30 16:47:16 -0500477 }
478
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500479out:
480 /* Reset CMD and DATA portions on error */
481 if (err) {
482 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
483 SYSCTL_RSTC);
484 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
485 ;
486
487 if (data) {
488 esdhc_write32(&regs->sysctl,
489 esdhc_read32(&regs->sysctl) |
490 SYSCTL_RSTD);
491 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
492 ;
493 }
494 }
495
Stefano Babicc67bee12010-02-05 15:11:27 +0100496 esdhc_write32(&regs->irqstat, -1);
Andy Fleming50586ef2008-10-30 16:47:16 -0500497
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500498 return err;
Andy Fleming50586ef2008-10-30 16:47:16 -0500499}
500
Simon Glass09b465f2017-07-29 11:35:17 -0600501static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
Andy Fleming50586ef2008-10-30 16:47:16 -0500502{
Benoît Thébaudeaub9b4f142018-01-16 22:44:18 +0100503 struct fsl_esdhc *regs = priv->esdhc_regs;
Benoît Thébaudeau4f425282017-05-03 11:59:03 +0200504 int div = 1;
Benoît Thébaudeau4f425282017-05-03 11:59:03 +0200505 int pre_div = 2;
Yinbo Zhu6f883e52019-07-16 15:09:11 +0800506 unsigned int sdhc_clk = priv->sdhc_clk;
507 u32 time_out;
508 u32 value;
Andy Fleming50586ef2008-10-30 16:47:16 -0500509 uint clk;
510
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200511 if (clock < mmc->cfg->f_min)
512 clock = mmc->cfg->f_min;
Stefano Babicc67bee12010-02-05 15:11:27 +0100513
Yangbo Lu5d336d12019-10-21 18:09:09 +0800514 while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
Lukasz Majewskib6a04272019-05-07 17:47:28 +0200515 pre_div *= 2;
Andy Fleming50586ef2008-10-30 16:47:16 -0500516
Yangbo Lu5d336d12019-10-21 18:09:09 +0800517 while (sdhc_clk / (div * pre_div) > clock && div < 16)
Lukasz Majewskib6a04272019-05-07 17:47:28 +0200518 div++;
Andy Fleming50586ef2008-10-30 16:47:16 -0500519
Yangbo Lu30f64442020-09-01 16:58:06 +0800520 mmc->clock = sdhc_clk / pre_div / div;
521 priv->clock = mmc->clock;
522
Benoît Thébaudeau4f425282017-05-03 11:59:03 +0200523 pre_div >>= 1;
Andy Fleming50586ef2008-10-30 16:47:16 -0500524 div -= 1;
525
526 clk = (pre_div << 8) | (div << 4);
527
Kumar Galacc4d1222010-03-18 15:51:05 -0500528 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
Stefano Babicc67bee12010-02-05 15:11:27 +0100529
530 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
Andy Fleming50586ef2008-10-30 16:47:16 -0500531
Yinbo Zhu6f883e52019-07-16 15:09:11 +0800532 time_out = 20;
533 value = PRSSTAT_SDSTB;
534 while (!(esdhc_read32(&regs->prsstat) & value)) {
535 if (time_out == 0) {
536 printf("fsl_esdhc: Internal clock never stabilised.\n");
537 break;
538 }
539 time_out--;
540 mdelay(1);
541 }
Andy Fleming50586ef2008-10-30 16:47:16 -0500542
Eric Nelsonf0b5f232015-12-04 12:32:48 -0700543 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
Andy Fleming50586ef2008-10-30 16:47:16 -0500544}
545
Simon Glass09b465f2017-07-29 11:35:17 -0600546static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800547{
Peng Fan96f04072016-03-25 14:16:56 +0800548 struct fsl_esdhc *regs = priv->esdhc_regs;
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800549 u32 value;
550 u32 time_out;
551
552 value = esdhc_read32(&regs->sysctl);
553
554 if (enable)
555 value |= SYSCTL_CKEN;
556 else
557 value &= ~SYSCTL_CKEN;
558
559 esdhc_write32(&regs->sysctl, value);
560
561 time_out = 20;
562 value = PRSSTAT_SDSTB;
563 while (!(esdhc_read32(&regs->prsstat) & value)) {
564 if (time_out == 0) {
565 printf("fsl_esdhc: Internal clock never stabilised.\n");
566 break;
567 }
568 time_out--;
569 mdelay(1);
570 }
571}
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +0800572
Yangbo Ludb8f9362020-09-01 16:58:05 +0800573static void esdhc_flush_async_fifo(struct fsl_esdhc_priv *priv)
574{
575 struct fsl_esdhc *regs = priv->esdhc_regs;
576 u32 time_out;
577
578 esdhc_setbits32(&regs->esdhcctl, ESDHCCTL_FAF);
579
580 time_out = 20;
581 while (esdhc_read32(&regs->esdhcctl) & ESDHCCTL_FAF) {
582 if (time_out == 0) {
583 printf("fsl_esdhc: Flush asynchronous FIFO timeout.\n");
584 break;
585 }
586 time_out--;
587 mdelay(1);
588 }
589}
590
591static void esdhc_tuning_block_enable(struct fsl_esdhc_priv *priv,
592 bool en)
593{
594 struct fsl_esdhc *regs = priv->esdhc_regs;
595
596 esdhc_clock_control(priv, false);
597 esdhc_flush_async_fifo(priv);
598 if (en)
599 esdhc_setbits32(&regs->tbctl, TBCTL_TB_EN);
600 else
601 esdhc_clrbits32(&regs->tbctl, TBCTL_TB_EN);
602 esdhc_clock_control(priv, true);
603}
604
605static void esdhc_exit_hs400(struct fsl_esdhc_priv *priv)
606{
607 struct fsl_esdhc *regs = priv->esdhc_regs;
608
609 esdhc_clrbits32(&regs->sdtimingctl, FLW_CTL_BG);
610 esdhc_clrbits32(&regs->sdclkctl, CMD_CLK_CTL);
611
612 esdhc_clock_control(priv, false);
613 esdhc_clrbits32(&regs->tbctl, HS400_MODE);
614 esdhc_clock_control(priv, true);
615
616 esdhc_clrbits32(&regs->dllcfg0, DLL_FREQ_SEL | DLL_ENABLE);
617 esdhc_clrbits32(&regs->tbctl, HS400_WNDW_ADJUST);
618
619 esdhc_tuning_block_enable(priv, false);
620}
621
Yangbo Lu8ee802f2020-10-20 11:04:52 +0800622static int esdhc_set_timing(struct fsl_esdhc_priv *priv, enum bus_mode mode)
Yangbo Lub1a42472020-09-01 16:58:01 +0800623{
624 struct fsl_esdhc *regs = priv->esdhc_regs;
Yangbo Lu8ee802f2020-10-20 11:04:52 +0800625 ulong start;
626 u32 val;
Yangbo Lub1a42472020-09-01 16:58:01 +0800627
Yangbo Ludb8f9362020-09-01 16:58:05 +0800628 /* Exit HS400 mode before setting any other mode */
629 if (esdhc_read32(&regs->tbctl) & HS400_MODE &&
630 mode != MMC_HS_400)
631 esdhc_exit_hs400(priv);
632
Yangbo Lub1a42472020-09-01 16:58:01 +0800633 esdhc_clock_control(priv, false);
634
635 if (mode == MMC_HS_200)
636 esdhc_clrsetbits32(&regs->autoc12err, UHSM_MASK,
637 UHSM_SDR104_HS200);
Yangbo Ludb8f9362020-09-01 16:58:05 +0800638 if (mode == MMC_HS_400) {
639 esdhc_setbits32(&regs->tbctl, HS400_MODE);
640 esdhc_setbits32(&regs->sdclkctl, CMD_CLK_CTL);
641 esdhc_clock_control(priv, true);
Yangbo Lub1a42472020-09-01 16:58:01 +0800642
Yangbo Lu78804de2020-09-01 16:58:07 +0800643 if (priv->clock == 200000000)
644 esdhc_setbits32(&regs->dllcfg0, DLL_FREQ_SEL);
645
646 esdhc_setbits32(&regs->dllcfg0, DLL_ENABLE);
Yangbo Lu8ee802f2020-10-20 11:04:52 +0800647
648 esdhc_setbits32(&regs->dllcfg0, DLL_RESET);
649 udelay(1);
650 esdhc_clrbits32(&regs->dllcfg0, DLL_RESET);
651
652 start = get_timer(0);
653 val = DLL_STS_SLV_LOCK;
654 while (!(esdhc_read32(&regs->dllstat0) & val)) {
655 if (get_timer(start) > 1000) {
656 printf("fsl_esdhc: delay chain lock timeout\n");
657 return -ETIMEDOUT;
658 }
659 }
660
Yangbo Ludb8f9362020-09-01 16:58:05 +0800661 esdhc_setbits32(&regs->tbctl, HS400_WNDW_ADJUST);
662
663 esdhc_clock_control(priv, false);
664 esdhc_flush_async_fifo(priv);
665 }
Yangbo Lub1a42472020-09-01 16:58:01 +0800666 esdhc_clock_control(priv, true);
Yangbo Lu8ee802f2020-10-20 11:04:52 +0800667 return 0;
Yangbo Lub1a42472020-09-01 16:58:01 +0800668}
669
Simon Glass9586aa62017-07-29 11:35:18 -0600670static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
Andy Fleming50586ef2008-10-30 16:47:16 -0500671{
Peng Fan96f04072016-03-25 14:16:56 +0800672 struct fsl_esdhc *regs = priv->esdhc_regs;
Yangbo Lu8ee802f2020-10-20 11:04:52 +0800673 int ret;
Andy Fleming50586ef2008-10-30 16:47:16 -0500674
Yangbo Luf1bce082019-12-19 18:59:30 +0800675 if (priv->is_sdhc_per_clk) {
676 /* Select to use peripheral clock */
677 esdhc_clock_control(priv, false);
678 esdhc_setbits32(&regs->esdhcctl, ESDHCCTL_PCS);
679 esdhc_clock_control(priv, true);
680 }
681
Yangbo Ludb8f9362020-09-01 16:58:05 +0800682 if (mmc->selected_mode == MMC_HS_400)
683 esdhc_tuning_block_enable(priv, true);
684
Andy Fleming50586ef2008-10-30 16:47:16 -0500685 /* Set the clock speed */
Peng Fan51313b42018-01-21 19:00:24 +0800686 if (priv->clock != mmc->clock)
687 set_sysctl(priv, mmc, mmc->clock);
688
Yangbo Lub1a42472020-09-01 16:58:01 +0800689 /* Set timing */
Yangbo Lu8ee802f2020-10-20 11:04:52 +0800690 ret = esdhc_set_timing(priv, mmc->selected_mode);
691 if (ret)
692 return ret;
Yangbo Lub1a42472020-09-01 16:58:01 +0800693
Andy Fleming50586ef2008-10-30 16:47:16 -0500694 /* Set the bus width */
Stefano Babicc67bee12010-02-05 15:11:27 +0100695 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
Andy Fleming50586ef2008-10-30 16:47:16 -0500696
697 if (mmc->bus_width == 4)
Stefano Babicc67bee12010-02-05 15:11:27 +0100698 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
Andy Fleming50586ef2008-10-30 16:47:16 -0500699 else if (mmc->bus_width == 8)
Stefano Babicc67bee12010-02-05 15:11:27 +0100700 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
701
Jaehoon Chung07b0b9c2016-12-30 15:30:16 +0900702 return 0;
Andy Fleming50586ef2008-10-30 16:47:16 -0500703}
704
Rasmus Villemoesede28222020-01-30 12:06:45 +0000705static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs)
706{
707#ifdef CONFIG_ARCH_MPC830X
708 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
709 sysconf83xx_t *sysconf = &immr->sysconf;
710
711 setbits_be32(&sysconf->sdhccr, 0x02000000);
712#else
713 esdhc_write32(&regs->esdhcctl, 0x00000040);
714#endif
715}
716
Simon Glass9586aa62017-07-29 11:35:18 -0600717static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
Andy Fleming50586ef2008-10-30 16:47:16 -0500718{
Peng Fan96f04072016-03-25 14:16:56 +0800719 struct fsl_esdhc *regs = priv->esdhc_regs;
Simon Glass201e8282017-07-29 11:35:20 -0600720 ulong start;
Andy Fleming50586ef2008-10-30 16:47:16 -0500721
Stefano Babicc67bee12010-02-05 15:11:27 +0100722 /* Reset the entire host controller */
Dirk Behmea61da722013-07-15 15:44:29 +0200723 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
Stefano Babicc67bee12010-02-05 15:11:27 +0100724
725 /* Wait until the controller is available */
Simon Glass201e8282017-07-29 11:35:20 -0600726 start = get_timer(0);
727 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
728 if (get_timer(start) > 1000)
729 return -ETIMEDOUT;
730 }
Stefano Babicc67bee12010-02-05 15:11:27 +0100731
Yangbo Lu1b5f0ba2020-09-01 16:58:02 +0800732 /* Clean TBCTL[TB_EN] which is not able to be reset by reset all */
733 esdhc_clrbits32(&regs->tbctl, TBCTL_TB_EN);
734
Rasmus Villemoesede28222020-01-30 12:06:45 +0000735 esdhc_enable_cache_snooping(regs);
P.V.Suresh2c1764e2010-12-04 10:37:23 +0530736
Dirk Behmea61da722013-07-15 15:44:29 +0200737 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
Andy Fleming50586ef2008-10-30 16:47:16 -0500738
739 /* Set the initial clock speed */
Yangbo Lu263ddfc2020-10-20 11:04:51 +0800740 set_sysctl(priv, mmc, 400000);
Andy Fleming50586ef2008-10-30 16:47:16 -0500741
742 /* Disable the BRR and BWR bits in IRQSTAT */
Stefano Babicc67bee12010-02-05 15:11:27 +0100743 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
Andy Fleming50586ef2008-10-30 16:47:16 -0500744
745 /* Put the PROCTL reg back to the default */
Stefano Babicc67bee12010-02-05 15:11:27 +0100746 esdhc_write32(&regs->proctl, PROCTL_INIT);
Andy Fleming50586ef2008-10-30 16:47:16 -0500747
Stefano Babicc67bee12010-02-05 15:11:27 +0100748 /* Set timout to the maximum value */
749 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
Andy Fleming50586ef2008-10-30 16:47:16 -0500750
Thierry Redingd48d2e22012-01-02 01:15:38 +0000751 return 0;
752}
Andy Fleming50586ef2008-10-30 16:47:16 -0500753
Simon Glass9586aa62017-07-29 11:35:18 -0600754static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
Thierry Redingd48d2e22012-01-02 01:15:38 +0000755{
Peng Fan96f04072016-03-25 14:16:56 +0800756 struct fsl_esdhc *regs = priv->esdhc_regs;
Stefano Babicc67bee12010-02-05 15:11:27 +0100757
Haijun.Zhangf7e27cc2014-01-10 13:52:17 +0800758#ifdef CONFIG_ESDHC_DETECT_QUIRK
759 if (CONFIG_ESDHC_DETECT_QUIRK)
760 return 1;
761#endif
Yangbo Lu9abf6482020-05-19 11:06:43 +0800762 if (esdhc_read32(&regs->prsstat) & PRSSTAT_CINS)
763 return 1;
Thierry Redingd48d2e22012-01-02 01:15:38 +0000764
Yangbo Lu9abf6482020-05-19 11:06:43 +0800765 return 0;
Andy Fleming50586ef2008-10-30 16:47:16 -0500766}
767
Yangbo Lu57059732019-10-31 18:54:23 +0800768static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
769 struct mmc_config *cfg)
Andy Fleming50586ef2008-10-30 16:47:16 -0500770{
Yangbo Lu57059732019-10-31 18:54:23 +0800771 struct fsl_esdhc *regs = priv->esdhc_regs;
Yangbo Lu5b05fc02019-10-31 18:54:21 +0800772 u32 caps;
Andy Fleming50586ef2008-10-30 16:47:16 -0500773
Wang Huan19060bd2014-09-05 13:52:40 +0800774 caps = esdhc_read32(&regs->hostcapblt);
Michael Walle52faec32020-10-12 10:07:13 +0200775 if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135))
776 caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30);
777 if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33))
778 caps |= HOSTCAPBLT_VS33;
Yangbo Lu5b05fc02019-10-31 18:54:21 +0800779 if (caps & HOSTCAPBLT_VS18)
780 cfg->voltages |= MMC_VDD_165_195;
781 if (caps & HOSTCAPBLT_VS30)
782 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
783 if (caps & HOSTCAPBLT_VS33)
784 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
Li Yang030955c2010-11-25 17:06:09 +0000785
Simon Glasse88e1d92017-07-29 11:35:21 -0600786 cfg->name = "FSL_SDHC";
Abbas Razaaad46592013-03-25 09:13:34 +0000787
Yangbo Lu5b05fc02019-10-31 18:54:21 +0800788 if (caps & HOSTCAPBLT_HSS)
Simon Glasse88e1d92017-07-29 11:35:21 -0600789 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
Andy Fleming50586ef2008-10-30 16:47:16 -0500790
Simon Glasse88e1d92017-07-29 11:35:21 -0600791 cfg->f_min = 400000;
Peng Fan51313b42018-01-21 19:00:24 +0800792 cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
Simon Glasse88e1d92017-07-29 11:35:21 -0600793 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
Peng Fan96f04072016-03-25 14:16:56 +0800794}
795
Stefano Babicc67bee12010-02-05 15:11:27 +0100796#ifdef CONFIG_OF_LIBFDT
Yangbo Lufce1e162017-01-17 10:43:54 +0800797__weak int esdhc_status_fixup(void *blob, const char *compat)
798{
Michael Walle52faec32020-10-12 10:07:13 +0200799 if (IS_ENABLED(CONFIG_FSL_ESDHC_PIN_MUX) && !hwconfig("esdhc")) {
Yangbo Lufce1e162017-01-17 10:43:54 +0800800 do_fixup_by_compat(blob, compat, "status", "disabled",
801 sizeof("disabled"), 1);
802 return 1;
803 }
Michael Walle52faec32020-10-12 10:07:13 +0200804
Yangbo Lufce1e162017-01-17 10:43:54 +0800805 return 0;
806}
807
Yangbo Luc927d652020-05-19 11:06:44 +0800808
Michael Walle52faec32020-10-12 10:07:13 +0200809#if CONFIG_IS_ENABLED(DM_MMC)
810static int fsl_esdhc_get_cd(struct udevice *dev);
Yangbo Luc927d652020-05-19 11:06:44 +0800811static void esdhc_disable_for_no_card(void *blob)
812{
813 struct udevice *dev;
814
815 for (uclass_first_device(UCLASS_MMC, &dev);
816 dev;
817 uclass_next_device(&dev)) {
818 char esdhc_path[50];
819
820 if (fsl_esdhc_get_cd(dev))
821 continue;
822
823 snprintf(esdhc_path, sizeof(esdhc_path), "/soc/esdhc@%lx",
824 (unsigned long)dev_read_addr(dev));
825 do_fixup_by_path(blob, esdhc_path, "status", "disabled",
826 sizeof("disabled"), 1);
827 }
828}
Michael Walle52faec32020-10-12 10:07:13 +0200829#else
830static void esdhc_disable_for_no_card(void *blob)
831{
832}
Yangbo Luc927d652020-05-19 11:06:44 +0800833#endif
834
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900835void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400836{
837 const char *compat = "fsl,esdhc";
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400838
Yangbo Lufce1e162017-01-17 10:43:54 +0800839 if (esdhc_status_fixup(blob, compat))
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800840 return;
Michael Walle52faec32020-10-12 10:07:13 +0200841
842 if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND))
843 esdhc_disable_for_no_card(blob);
844
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400845 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
Simon Glasse9adeca2012-12-13 20:49:05 +0000846 gd->arch.sdhc_clk, 1);
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400847}
Stefano Babicc67bee12010-02-05 15:11:27 +0100848#endif
Peng Fan96f04072016-03-25 14:16:56 +0800849
Yangbo Lu61870472019-10-31 18:54:26 +0800850#if !CONFIG_IS_ENABLED(DM_MMC)
851static int esdhc_getcd(struct mmc *mmc)
852{
853 struct fsl_esdhc_priv *priv = mmc->priv;
854
855 return esdhc_getcd_common(priv);
856}
857
858static int esdhc_init(struct mmc *mmc)
859{
860 struct fsl_esdhc_priv *priv = mmc->priv;
861
862 return esdhc_init_common(priv, mmc);
863}
864
865static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
866 struct mmc_data *data)
867{
868 struct fsl_esdhc_priv *priv = mmc->priv;
869
870 return esdhc_send_cmd_common(priv, mmc, cmd, data);
871}
872
873static int esdhc_set_ios(struct mmc *mmc)
874{
875 struct fsl_esdhc_priv *priv = mmc->priv;
876
877 return esdhc_set_ios_common(priv, mmc);
878}
879
880static const struct mmc_ops esdhc_ops = {
881 .getcd = esdhc_getcd,
882 .init = esdhc_init,
883 .send_cmd = esdhc_send_cmd,
884 .set_ios = esdhc_set_ios,
885};
886
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900887int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
Yangbo Lu61870472019-10-31 18:54:26 +0800888{
889 struct fsl_esdhc_plat *plat;
890 struct fsl_esdhc_priv *priv;
891 struct mmc_config *mmc_cfg;
892 struct mmc *mmc;
893
894 if (!cfg)
895 return -EINVAL;
896
897 priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
898 if (!priv)
899 return -ENOMEM;
900 plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
901 if (!plat) {
902 free(priv);
903 return -ENOMEM;
904 }
905
906 priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
907 priv->sdhc_clk = cfg->sdhc_clk;
Yangbo Luf1bce082019-12-19 18:59:30 +0800908 if (gd->arch.sdhc_per_clk)
909 priv->is_sdhc_per_clk = true;
Yangbo Lu61870472019-10-31 18:54:26 +0800910
911 mmc_cfg = &plat->cfg;
912
913 if (cfg->max_bus_width == 8) {
914 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
915 MMC_MODE_8BIT;
916 } else if (cfg->max_bus_width == 4) {
917 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT;
918 } else if (cfg->max_bus_width == 1) {
919 mmc_cfg->host_caps |= MMC_MODE_1BIT;
920 } else {
921 mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT |
922 MMC_MODE_8BIT;
923 printf("No max bus width provided. Assume 8-bit supported.\n");
924 }
925
Michael Walle52faec32020-10-12 10:07:13 +0200926 if (IS_ENABLED(CONFIG_ESDHC_DETECT_8_BIT_QUIRK))
Yangbo Lu61870472019-10-31 18:54:26 +0800927 mmc_cfg->host_caps &= ~MMC_MODE_8BIT;
Michael Walle52faec32020-10-12 10:07:13 +0200928
Yangbo Lu61870472019-10-31 18:54:26 +0800929 mmc_cfg->ops = &esdhc_ops;
930
931 fsl_esdhc_get_cfg_common(priv, mmc_cfg);
932
933 mmc = mmc_create(mmc_cfg, priv);
934 if (!mmc)
935 return -EIO;
936
937 priv->mmc = mmc;
938 return 0;
939}
940
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900941int fsl_esdhc_mmc_init(struct bd_info *bis)
Yangbo Lu61870472019-10-31 18:54:26 +0800942{
943 struct fsl_esdhc_cfg *cfg;
944
945 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
946 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
Yangbo Luf1bce082019-12-19 18:59:30 +0800947 /* Prefer peripheral clock which provides higher frequency. */
948 if (gd->arch.sdhc_per_clk)
949 cfg->sdhc_clk = gd->arch.sdhc_per_clk;
950 else
951 cfg->sdhc_clk = gd->arch.sdhc_clk;
Yangbo Lu61870472019-10-31 18:54:26 +0800952 return fsl_esdhc_initialize(bis, cfg);
953}
954#else /* DM_MMC */
Peng Fan96f04072016-03-25 14:16:56 +0800955static int fsl_esdhc_probe(struct udevice *dev)
956{
957 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -0700958 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Peng Fan96f04072016-03-25 14:16:56 +0800959 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
Michael Walle361a4222020-10-12 10:07:14 +0200960 u32 caps, hostver;
Peng Fan96f04072016-03-25 14:16:56 +0800961 fdt_addr_t addr;
Simon Glass653282b2017-07-29 11:35:24 -0600962 struct mmc *mmc;
Yangbo Luc927d652020-05-19 11:06:44 +0800963 int ret;
Peng Fan96f04072016-03-25 14:16:56 +0800964
Simon Glass4aac33f2017-07-29 11:35:23 -0600965 addr = dev_read_addr(dev);
Peng Fan96f04072016-03-25 14:16:56 +0800966 if (addr == FDT_ADDR_T_NONE)
967 return -EINVAL;
Yinbo Zhub69e1d02019-04-11 11:01:50 +0000968#ifdef CONFIG_PPC
969 priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr);
970#else
Peng Fan96f04072016-03-25 14:16:56 +0800971 priv->esdhc_regs = (struct fsl_esdhc *)addr;
Yinbo Zhub69e1d02019-04-11 11:01:50 +0000972#endif
Peng Fan96f04072016-03-25 14:16:56 +0800973 priv->dev = dev;
974
Michael Walle361a4222020-10-12 10:07:14 +0200975 if (IS_ENABLED(CONFIG_FSL_ESDHC_SUPPORT_ADMA2)) {
976 /*
977 * Only newer eSDHC controllers can do ADMA2 if the ADMA flag
978 * is set in the host capabilities register.
979 */
980 caps = esdhc_read32(&priv->esdhc_regs->hostcapblt);
981 hostver = esdhc_read32(&priv->esdhc_regs->hostver);
982 if (caps & HOSTCAPBLT_DMAS &&
983 HOSTVER_VENDOR(hostver) > VENDOR_V_22) {
984 priv->adma_desc_table = sdhci_adma_init();
985 if (!priv->adma_desc_table)
986 debug("Could not allocate ADMA tables, falling back to SDMA\n");
987 }
988 }
989
Yangbo Luf1bce082019-12-19 18:59:30 +0800990 if (gd->arch.sdhc_per_clk) {
991 priv->sdhc_clk = gd->arch.sdhc_per_clk;
992 priv->is_sdhc_per_clk = true;
993 } else {
994 priv->sdhc_clk = gd->arch.sdhc_clk;
995 }
996
Yangbo Lu5e81cbf2019-11-12 19:28:36 +0800997 if (priv->sdhc_clk <= 0) {
998 dev_err(dev, "Unable to get clk for %s\n", dev->name);
999 return -EINVAL;
Peng Fan96f04072016-03-25 14:16:56 +08001000 }
1001
Yangbo Lu57059732019-10-31 18:54:23 +08001002 fsl_esdhc_get_cfg_common(priv, &plat->cfg);
Peng Fan96f04072016-03-25 14:16:56 +08001003
Yinbo Zhu6f883e52019-07-16 15:09:11 +08001004 mmc_of_parse(dev, &plat->cfg);
1005
Simon Glass653282b2017-07-29 11:35:24 -06001006 mmc = &plat->mmc;
1007 mmc->cfg = &plat->cfg;
1008 mmc->dev = dev;
Yangbo Lu66fa0352019-05-23 11:05:46 +08001009
Simon Glass653282b2017-07-29 11:35:24 -06001010 upriv->mmc = mmc;
Peng Fan96f04072016-03-25 14:16:56 +08001011
Yangbo Luc927d652020-05-19 11:06:44 +08001012 ret = esdhc_init_common(priv, mmc);
1013 if (ret)
1014 return ret;
1015
Michael Walle52faec32020-10-12 10:07:13 +02001016 if (IS_ENABLED(CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND) &&
1017 !fsl_esdhc_get_cd(dev))
Yangbo Luc927d652020-05-19 11:06:44 +08001018 esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL);
Michael Walle52faec32020-10-12 10:07:13 +02001019
Yangbo Luc927d652020-05-19 11:06:44 +08001020 return 0;
Peng Fan96f04072016-03-25 14:16:56 +08001021}
1022
Simon Glass653282b2017-07-29 11:35:24 -06001023static int fsl_esdhc_get_cd(struct udevice *dev)
1024{
Simon Glassc69cda22020-12-03 16:55:20 -07001025 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Simon Glass653282b2017-07-29 11:35:24 -06001026 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1027
Yangbo Lu08197cb2019-10-31 18:54:24 +08001028 if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE)
1029 return 1;
1030
Simon Glass653282b2017-07-29 11:35:24 -06001031 return esdhc_getcd_common(priv);
1032}
1033
1034static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1035 struct mmc_data *data)
1036{
Simon Glassc69cda22020-12-03 16:55:20 -07001037 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Simon Glass653282b2017-07-29 11:35:24 -06001038 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1039
1040 return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1041}
1042
1043static int fsl_esdhc_set_ios(struct udevice *dev)
1044{
Simon Glassc69cda22020-12-03 16:55:20 -07001045 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Simon Glass653282b2017-07-29 11:35:24 -06001046 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1047
1048 return esdhc_set_ios_common(priv, &plat->mmc);
1049}
1050
Yangbo Lu1fdefd12020-09-01 16:58:00 +08001051static int fsl_esdhc_reinit(struct udevice *dev)
1052{
Simon Glassc69cda22020-12-03 16:55:20 -07001053 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Yangbo Lu1fdefd12020-09-01 16:58:00 +08001054 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1055
1056 return esdhc_init_common(priv, &plat->mmc);
1057}
1058
Yangbo Lub1a42472020-09-01 16:58:01 +08001059#ifdef MMC_SUPPORTS_TUNING
Yangbo Lub1a42472020-09-01 16:58:01 +08001060static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
1061{
Simon Glassc69cda22020-12-03 16:55:20 -07001062 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Yangbo Lub1a42472020-09-01 16:58:01 +08001063 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1064 struct fsl_esdhc *regs = priv->esdhc_regs;
1065 u32 val, irqstaten;
1066 int i;
1067
1068 esdhc_tuning_block_enable(priv, true);
1069 esdhc_setbits32(&regs->autoc12err, EXECUTE_TUNING);
1070
1071 irqstaten = esdhc_read32(&regs->irqstaten);
1072 esdhc_write32(&regs->irqstaten, IRQSTATEN_BRR);
1073
1074 for (i = 0; i < MAX_TUNING_LOOP; i++) {
1075 mmc_send_tuning(&plat->mmc, opcode, NULL);
1076 mdelay(1);
1077
1078 val = esdhc_read32(&regs->autoc12err);
1079 if (!(val & EXECUTE_TUNING)) {
1080 if (val & SMPCLKSEL)
1081 break;
1082 }
1083 }
1084
1085 esdhc_write32(&regs->irqstaten, irqstaten);
1086
Yangbo Ludb8f9362020-09-01 16:58:05 +08001087 if (i != MAX_TUNING_LOOP) {
1088 if (plat->mmc.hs400_tuning)
1089 esdhc_setbits32(&regs->sdtimingctl, FLW_CTL_BG);
Yangbo Lub1a42472020-09-01 16:58:01 +08001090 return 0;
Yangbo Ludb8f9362020-09-01 16:58:05 +08001091 }
Yangbo Lub1a42472020-09-01 16:58:01 +08001092
1093 printf("fsl_esdhc: tuning failed!\n");
1094 esdhc_clrbits32(&regs->autoc12err, SMPCLKSEL);
1095 esdhc_clrbits32(&regs->autoc12err, EXECUTE_TUNING);
1096 esdhc_tuning_block_enable(priv, false);
1097 return -ETIMEDOUT;
1098}
1099#endif
1100
Yangbo Ludb8f9362020-09-01 16:58:05 +08001101int fsl_esdhc_hs400_prepare_ddr(struct udevice *dev)
1102{
1103 struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1104
1105 esdhc_tuning_block_enable(priv, false);
1106 return 0;
1107}
1108
Simon Glass653282b2017-07-29 11:35:24 -06001109static const struct dm_mmc_ops fsl_esdhc_ops = {
1110 .get_cd = fsl_esdhc_get_cd,
1111 .send_cmd = fsl_esdhc_send_cmd,
1112 .set_ios = fsl_esdhc_set_ios,
Yinbo Zhu6f883e52019-07-16 15:09:11 +08001113#ifdef MMC_SUPPORTS_TUNING
1114 .execute_tuning = fsl_esdhc_execute_tuning,
1115#endif
Yangbo Lu1fdefd12020-09-01 16:58:00 +08001116 .reinit = fsl_esdhc_reinit,
Yangbo Ludb8f9362020-09-01 16:58:05 +08001117 .hs400_prepare_ddr = fsl_esdhc_hs400_prepare_ddr,
Simon Glass653282b2017-07-29 11:35:24 -06001118};
Simon Glass653282b2017-07-29 11:35:24 -06001119
Peng Fan96f04072016-03-25 14:16:56 +08001120static const struct udevice_id fsl_esdhc_ids[] = {
Yangbo Lua6473f82016-12-07 11:54:31 +08001121 { .compatible = "fsl,esdhc", },
Peng Fan96f04072016-03-25 14:16:56 +08001122 { /* sentinel */ }
1123};
1124
Simon Glass653282b2017-07-29 11:35:24 -06001125static int fsl_esdhc_bind(struct udevice *dev)
1126{
Simon Glassc69cda22020-12-03 16:55:20 -07001127 struct fsl_esdhc_plat *plat = dev_get_plat(dev);
Simon Glass653282b2017-07-29 11:35:24 -06001128
1129 return mmc_bind(dev, &plat->mmc, &plat->cfg);
1130}
Simon Glass653282b2017-07-29 11:35:24 -06001131
Peng Fan96f04072016-03-25 14:16:56 +08001132U_BOOT_DRIVER(fsl_esdhc) = {
1133 .name = "fsl-esdhc-mmc",
1134 .id = UCLASS_MMC,
1135 .of_match = fsl_esdhc_ids,
Simon Glass653282b2017-07-29 11:35:24 -06001136 .ops = &fsl_esdhc_ops,
Simon Glass653282b2017-07-29 11:35:24 -06001137 .bind = fsl_esdhc_bind,
Peng Fan96f04072016-03-25 14:16:56 +08001138 .probe = fsl_esdhc_probe,
Simon Glasscaa4daa2020-12-03 16:55:18 -07001139 .plat_auto = sizeof(struct fsl_esdhc_plat),
Simon Glass41575d82020-12-03 16:55:17 -07001140 .priv_auto = sizeof(struct fsl_esdhc_priv),
Peng Fan96f04072016-03-25 14:16:56 +08001141};
1142#endif