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wdenk2d24a3a2004-06-09 21:50:45 +00001/*
2 * include/configs/mx1ads.h
wdenk49822e22004-06-19 21:19:10 +00003 *
wdenk2d24a3a2004-06-09 21:50:45 +00004 * (c) Copyright 2004
5 * Techware Information Technology, Inc.
6 * http://www.techware.com.tw/
7 *
8 * Ming-Len Wu <minglen_wu@techware.com.tw>
9 *
10 * This is the Configuration setting for Motorola MX1ADS board
11 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020012 * SPDX-License-Identifier: GPL-2.0+
wdenk2d24a3a2004-06-09 21:50:45 +000013 */
14
wdenk2d24a3a2004-06-09 21:50:45 +000015#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
wdenk2d24a3a2004-06-09 21:50:45 +000019 * High Level Configuration Options
20 * (easy to change)
21 */
22#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
wdenk281e00a2004-08-01 22:48:16 +000023#define CONFIG_IMX 1 /* It's a Motorola MC9328 SoC */
24#define CONFIG_MX1ADS 1 /* on a Motorola MX1ADS Board */
wdenk281e00a2004-08-01 22:48:16 +000025
26/*
27 * Select serial console configuration
28 */
Jean-Christophe PLAGNIOL-VILLARDd3e55d02009-03-30 18:58:38 +020029#define CONFIG_IMX_SERIAL
wdenk281e00a2004-08-01 22:48:16 +000030#define CONFIG_IMX_SERIAL1 /* internal uart 1 */
31/* #define _CONFIG_UART2 */ /* internal uart 2 */
32/* #define CONFIG_SILENT_CONSOLE */ /* use this to disable output */
wdenk2d24a3a2004-06-09 21:50:45 +000033
Helmut Raiger9660e442011-10-20 04:19:47 +000034#define CONFIG_BOARD_LATE_INIT
wdenk2d24a3a2004-06-09 21:50:45 +000035#define USE_920T_MMU 1
wdenk2d24a3a2004-06-09 21:50:45 +000036
wdenk49822e22004-06-19 21:19:10 +000037#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
39#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
40#define CONFIG_SYS_MX1_GPCR 0x000003AB /* for MX1ADS 0L44N */
wdenk49822e22004-06-19 21:19:10 +000041#endif
wdenk2d24a3a2004-06-09 21:50:45 +000042
43/*
44 * Size of malloc() pool
45 */
46
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenk281e00a2004-08-01 22:48:16 +000048
wdenk2d24a3a2004-06-09 21:50:45 +000049/*
50 * CS8900 Ethernet drivers
51 */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070052#define CONFIG_CS8900 /* we have a CS8900 on-board */
53#define CONFIG_CS8900_BASE 0x15000300
54#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
wdenk2d24a3a2004-06-09 21:50:45 +000055
56/*
57 * select serial console configuration
58 */
59
wdenk281e00a2004-08-01 22:48:16 +000060/* #define CONFIG_UART1 */
wdenk2d24a3a2004-06-09 21:50:45 +000061/* #define CONFIG_UART2 1 */
62
63#define CONFIG_BAUDRATE 115200
64
Jon Loeliger5dc11a52007-07-04 22:33:01 -050065/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050066 * BOOTP options
67 */
68#define CONFIG_BOOTP_BOOTFILESIZE
69#define CONFIG_BOOTP_BOOTPATH
70#define CONFIG_BOOTP_GATEWAY
71#define CONFIG_BOOTP_HOSTNAME
72
Jon Loeliger7f5c0152007-07-10 09:38:02 -050073/*
Jon Loeliger5dc11a52007-07-04 22:33:01 -050074 * Command line configuration.
75 */
76#include <config_cmd_default.h>
wdenk2d24a3a2004-06-09 21:50:45 +000077
Jon Loeliger5dc11a52007-07-04 22:33:01 -050078#define CONFIG_CMD_CACHE
79#define CONFIG_CMD_REGINFO
80#define CONFIG_CMD_ELF
81
wdenk2d24a3a2004-06-09 21:50:45 +000082#define CONFIG_BOOTDELAY 3
wdenk281e00a2004-08-01 22:48:16 +000083#define CONFIG_BOOTARGS "root=/dev/msdk mem=48M"
wdenk2d24a3a2004-06-09 21:50:45 +000084#define CONFIG_BOOTFILE "mx1ads"
wdenk281e00a2004-08-01 22:48:16 +000085#define CONFIG_BOOTCOMMAND "tftp; bootm"
wdenk2d24a3a2004-06-09 21:50:45 +000086
Jon Loeliger5dc11a52007-07-04 22:33:01 -050087#if defined(CONFIG_CMD_KGDB)
wdenk2d24a3a2004-06-09 21:50:45 +000088#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
89 /* what's this ? it's not used anywhere */
90#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
91#endif
92
93/*
94 * Miscellaneous configurable options
95 */
wdenk49822e22004-06-19 21:19:10 +000096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_HUSH_PARSER 1
wdenk49822e22004-06-19 21:19:10 +000098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk2d24a3a2004-06-09 21:50:45 +0000100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#ifdef CONFIG_SYS_HUSH_PARSER
102#define CONFIG_SYS_PROMPT "MX1ADS$ " /* Monitor Command Prompt */
wdenk2d24a3a2004-06-09 21:50:45 +0000103#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_PROMPT "MX1ADS=> " /* Monitor Command Prompt */
wdenk2d24a3a2004-06-09 21:50:45 +0000105#endif
106
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
108#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
wdenk2d24a3a2004-06-09 21:50:45 +0000109 /* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
111#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk2d24a3a2004-06-09 21:50:45 +0000112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_MEMTEST_START 0x09000000 /* memtest works on */
114#define CONFIG_SYS_MEMTEST_END 0x0AF00000 /* 63 MB in DRAM */
wdenk2d24a3a2004-06-09 21:50:45 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_LOAD_ADDR 0x08800000 /* default load address */
117/*#define CONFIG_SYS_HZ 1000 */
118#define CONFIG_SYS_HZ 3686400
119#define CONFIG_SYS_CPUSPEED 0x141
wdenk2d24a3a2004-06-09 21:50:45 +0000120
wdenk2d24a3a2004-06-09 21:50:45 +0000121/*-----------------------------------------------------------------------
wdenk2d24a3a2004-06-09 21:50:45 +0000122 * Physical Memory Map
123 */
wdenk49822e22004-06-19 21:19:10 +0000124
wdenk281e00a2004-08-01 22:48:16 +0000125#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
126#define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */
127#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
wdenk2d24a3a2004-06-09 21:50:45 +0000128
Fabio Estevame845f902011-06-11 15:16:32 +0000129#define CONFIG_SYS_TEXT_BASE 0x10000000
130
131#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
132#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000
133#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF
134#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
135 GENERATED_GBL_DATA_SIZE)
136#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
137 CONFIG_SYS_GBL_DATA_OFFSET)
138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */
140#define CONFIG_SYS_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */
wdenk281e00a2004-08-01 22:48:16 +0000141#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
wdenk2d24a3a2004-06-09 21:50:45 +0000142
143/*-----------------------------------------------------------------------
144 * FLASH and environment organization
145 */
146
wdenk2d24a3a2004-06-09 21:50:45 +0000147#define CONFIG_SYNCFLASH 1
148#define PHYS_FLASH_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_MAX_FLASH_SECT (16)
150#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x00ff8000)
wdenk49822e22004-06-19 21:19:10 +0000151
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200152#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200153#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
154#define CONFIG_ENV_SECT_SIZE 0x100000
wdenk281e00a2004-08-01 22:48:16 +0000155
156/*-----------------------------------------------------------------------
157 * Enable passing ATAGS
158 */
159
160#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
161#define CONFIG_SETUP_MEMORY_TAGS 1
162
163#define CONFIG_SYS_CLK_FREQ 16780000
164#define CONFIG_SYSPLL_CLK_FREQ 16000000
165
wdenk2d24a3a2004-06-09 21:50:45 +0000166#endif /* __CONFIG_H */