Tom Rini | af27382 | 2016-10-26 17:15:37 -0400 | [diff] [blame] | 1 | menuconfig PCI |
| 2 | bool "PCI support" |
Tom Rini | ac9fa57 | 2021-05-14 21:34:32 -0400 | [diff] [blame] | 3 | depends on DM |
Bin Meng | 6bf89de | 2017-07-30 06:23:09 -0700 | [diff] [blame] | 4 | default y if PPC |
Tom Rini | af27382 | 2016-10-26 17:15:37 -0400 | [diff] [blame] | 5 | help |
| 6 | Enable support for PCI (Peripheral Interconnect Bus), a type of bus |
| 7 | used on some devices to allow the CPU to communicate with its |
| 8 | peripherals. |
| 9 | |
Simon Glass | 3232bdf | 2021-08-01 18:54:44 -0600 | [diff] [blame] | 10 | This subsystem requires driver model. |
Simon Glass | ff3e077 | 2015-03-05 12:25:25 -0700 | [diff] [blame] | 11 | |
Tom Rini | ac9fa57 | 2021-05-14 21:34:32 -0400 | [diff] [blame] | 12 | if PCI |
| 13 | |
Simon Glass | 3ba5f74 | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 14 | config DM_PCI_COMPAT |
| 15 | bool "Enable compatible functions for PCI" |
Simon Glass | 3ba5f74 | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 16 | help |
| 17 | Enable compatibility functions for PCI so that old code can be used |
Simon Glass | 3232bdf | 2021-08-01 18:54:44 -0600 | [diff] [blame] | 18 | with CONFIG_PCI enabled. This should be used as an interim |
Simon Glass | 3ba5f74 | 2015-11-26 19:51:30 -0700 | [diff] [blame] | 19 | measure when porting a board to use driver model for PCI. Once the |
| 20 | board is fully supported, this option should be disabled. |
| 21 | |
Tom Rini | 7856cd5 | 2021-12-12 22:12:32 -0500 | [diff] [blame] | 22 | config SYS_PCI_64BIT |
| 23 | bool "Enable 64-bit PCI resources" |
| 24 | default y if PPC |
| 25 | help |
| 26 | Enable 64-bit PCI resource access. |
| 27 | |
Wilson Ding | e51f2b1 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 28 | config PCI_AARDVARK |
| 29 | bool "Enable Aardvark PCIe driver" |
Pali Rohár | 835d969 | 2020-08-25 10:45:04 +0200 | [diff] [blame] | 30 | depends on DM_GPIO |
Wilson Ding | e51f2b1 | 2018-03-26 15:57:29 +0800 | [diff] [blame] | 31 | depends on ARMADA_3700 |
| 32 | help |
| 33 | Say Y here if you want to enable PCIe controller support on |
| 34 | Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on |
| 35 | Aardvark hardware. |
| 36 | |
Bin Meng | c476215 | 2016-10-16 23:35:18 -0700 | [diff] [blame] | 37 | config PCI_PNP |
| 38 | bool "Enable Plug & Play support for PCI" |
Bin Meng | c476215 | 2016-10-16 23:35:18 -0700 | [diff] [blame] | 39 | default y |
| 40 | help |
| 41 | Enable PCI memory and I/O space resource allocation and assignment. |
| 42 | |
Mayuresh Chitale | 32f5e9e | 2023-06-03 19:32:55 +0530 | [diff] [blame] | 43 | config SPL_PCI_PNP |
| 44 | bool "Enable Plug & Play support for PCI" |
| 45 | help |
| 46 | Enable PCI memory and I/O space resource allocation and assignment. |
Simon Glass | db3820a | 2023-07-15 21:38:55 -0600 | [diff] [blame^] | 47 | |
Mayuresh Chitale | 32f5e9e | 2023-06-03 19:32:55 +0530 | [diff] [blame] | 48 | This is required to auto configure the enumerated devices. |
| 49 | |
Simon Glass | db3820a | 2023-07-15 21:38:55 -0600 | [diff] [blame^] | 50 | This is normally not done in SPL, but can be enabled if devices must |
| 51 | be set up in the SPL phase. Often it is enough to manually configure |
| 52 | one device, so this option can be disabled. |
| 53 | |
Suneel Garapati | 4cf56ec | 2019-10-19 17:10:20 -0700 | [diff] [blame] | 54 | config PCI_REGION_MULTI_ENTRY |
| 55 | bool "Enable Multiple entries of region type MEMORY in ranges for PCI" |
Suneel Garapati | 4cf56ec | 2019-10-19 17:10:20 -0700 | [diff] [blame] | 56 | help |
| 57 | Enable PCI memory regions to be of multiple entry. Multiple entry |
| 58 | here refers to allow more than one count of address ranges for MEMORY |
| 59 | region type. This helps to add support for SoC's like OcteonTX/TX2 |
| 60 | where every peripheral is on the PCI bus. |
| 61 | |
Tom Rini | e58eebb | 2022-06-20 08:07:50 -0400 | [diff] [blame] | 62 | config PCI_CONFIG_HOST_BRIDGE |
| 63 | bool "Configure PCI host bridges" |
| 64 | default y if X86 |
| 65 | |
Daniel Schwierzeck | a45343a | 2021-07-15 20:53:56 +0200 | [diff] [blame] | 66 | config PCI_MAP_SYSTEM_MEMORY |
| 67 | bool "Map local system memory from a virtual base address" |
Daniel Schwierzeck | a45343a | 2021-07-15 20:53:56 +0200 | [diff] [blame] | 68 | depends on MIPS |
Daniel Schwierzeck | a45343a | 2021-07-15 20:53:56 +0200 | [diff] [blame] | 69 | help |
| 70 | Say Y if base address of system memory is being used as a virtual address |
| 71 | instead of a physical address (e.g. on MIPS). The PCI core will then remap |
| 72 | the virtual memory base address to a physical address when adding the PCI |
| 73 | region of type PCI_REGION_SYS_MEMORY. |
Tom Rini | aa6e94d | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 74 | This should only be required on MIPS where CFG_SYS_SDRAM_BASE is still |
Daniel Schwierzeck | a45343a | 2021-07-15 20:53:56 +0200 | [diff] [blame] | 75 | being used as virtual address. |
| 76 | |
Suneel Garapati | b8852dc | 2019-10-19 16:07:20 -0700 | [diff] [blame] | 77 | config PCI_SRIOV |
| 78 | bool "Enable Single Root I/O Virtualization support for PCI" |
Suneel Garapati | b8852dc | 2019-10-19 16:07:20 -0700 | [diff] [blame] | 79 | help |
| 80 | Say Y here if you want to enable PCI Single Root I/O Virtualization |
| 81 | capability support. This helps to enumerate Virtual Function devices |
| 82 | if available on a PCI Physical Function device and probe for |
| 83 | applicable drivers. |
| 84 | |
Andrew Scull | 3b92018 | 2022-04-21 16:11:16 +0000 | [diff] [blame] | 85 | config PCI_ENHANCED_ALLOCATION |
| 86 | bool "Enable support for Enhanced Allocation of resources" |
| 87 | default y |
| 88 | help |
| 89 | Enable support for Enhanced Allocation which can be used by supported |
| 90 | devices in place of traditional BARS for allocation of resources. |
| 91 | |
Suneel Garapati | a3fac3f | 2019-10-23 18:40:36 -0700 | [diff] [blame] | 92 | config PCI_ARID |
| 93 | bool "Enable Alternate Routing-ID support for PCI" |
Suneel Garapati | a3fac3f | 2019-10-23 18:40:36 -0700 | [diff] [blame] | 94 | help |
| 95 | Say Y here if you want to enable Alternate Routing-ID capability |
| 96 | support on PCI devices. This helps to skip some devices in BDF |
| 97 | scan that are not present. |
| 98 | |
Tom Rini | f27bca4 | 2022-06-20 08:07:48 -0400 | [diff] [blame] | 99 | config PCI_SCAN_SHOW |
| 100 | bool "Show PCI devices during startup" |
| 101 | depends on PCIE_IMX |
| 102 | |
Tuomas Tynkkynen | 3675cb0 | 2017-09-19 23:18:06 +0300 | [diff] [blame] | 103 | config PCIE_ECAM_GENERIC |
| 104 | bool "Generic ECAM-based PCI host controller support" |
Tuomas Tynkkynen | 3675cb0 | 2017-09-19 23:18:06 +0300 | [diff] [blame] | 105 | help |
| 106 | Say Y here if you want to enable support for generic ECAM-based |
| 107 | PCIe host controllers, such as the one emulated by QEMU. |
| 108 | |
Masami Hiramatsu | 3296d52 | 2021-06-04 18:44:06 +0900 | [diff] [blame] | 109 | config PCIE_ECAM_SYNQUACER |
| 110 | bool "SynQuacer ECAM-based PCI host controller support" |
Masami Hiramatsu | 3296d52 | 2021-06-04 18:44:06 +0900 | [diff] [blame] | 111 | select PCI_INIT_R |
| 112 | select PCI_REGION_MULTI_ENTRY |
| 113 | help |
| 114 | Say Y here if you want to enable support for Socionext |
| 115 | SynQuacer SoC's ECAM-based PCIe host controllers. |
| 116 | Note that this must be configured when boot because Linux driver |
| 117 | expects the PCIe RC has been configured in the bootloader. |
| 118 | |
Mark Kettenis | bdebb00 | 2023-01-21 20:27:58 +0100 | [diff] [blame] | 119 | config PCIE_APPLE |
| 120 | bool "Enable Apple PCIe driver" |
| 121 | depends on ARCH_APPLE |
| 122 | imply PCI_INIT_R |
| 123 | default y |
| 124 | help |
| 125 | Say Y here if you want to enable PCIe controller support on |
| 126 | Apple SoCs. |
| 127 | |
Tom Rini | bf2c48f | 2022-06-20 08:07:49 -0400 | [diff] [blame] | 128 | config PCI_GT64120 |
| 129 | bool "GT64120 PCI support" |
| 130 | depends on MIPS |
| 131 | |
liu hao | e3aafef | 2019-10-31 07:51:08 +0000 | [diff] [blame] | 132 | config PCI_PHYTIUM |
| 133 | bool "Phytium PCIe support" |
liu hao | e3aafef | 2019-10-31 07:51:08 +0000 | [diff] [blame] | 134 | help |
| 135 | Say Y here if you want to enable PCIe controller support on |
| 136 | Phytium SoCs. |
| 137 | |
Shadi Ammouri | 182ba1a | 2016-10-27 13:29:41 +0200 | [diff] [blame] | 138 | config PCIE_DW_MVEBU |
| 139 | bool "Enable Armada-8K PCIe driver (DesignWare core)" |
Shadi Ammouri | 182ba1a | 2016-10-27 13:29:41 +0200 | [diff] [blame] | 140 | depends on ARMADA_8K |
| 141 | help |
| 142 | Say Y here if you want to enable PCIe controller support on |
| 143 | Armada-8K SoCs. The PCIe controller on Armada-8K is based on |
| 144 | DesignWare hardware. |
| 145 | |
Green Wan | 416395c | 2021-05-27 06:52:10 -0700 | [diff] [blame] | 146 | config PCIE_DW_SIFIVE |
| 147 | bool "Enable SiFive FU740 PCIe" |
| 148 | depends on CLK_SIFIVE_PRCI |
| 149 | depends on RESET_SIFIVE |
| 150 | depends on SIFIVE_GPIO |
| 151 | select PCIE_DW_COMMON |
| 152 | help |
| 153 | Say Y here if you want to enable PCIe controller support on |
| 154 | FU740. |
| 155 | |
Tom Rini | 6bb74fe | 2022-06-20 08:07:56 -0400 | [diff] [blame] | 156 | config SYS_FSL_PCI_VER_3_X |
| 157 | bool |
| 158 | |
Hou Zhiqiang | b89e3d9 | 2019-04-24 22:33:02 +0800 | [diff] [blame] | 159 | config PCIE_FSL |
| 160 | bool "FSL PowerPC PCIe support" |
Tom Rini | 6bb74fe | 2022-06-20 08:07:56 -0400 | [diff] [blame] | 161 | select SYS_FSL_PCI_VER_3_X if ARCH_T2080 || ARCH_T4240 |
Hou Zhiqiang | b89e3d9 | 2019-04-24 22:33:02 +0800 | [diff] [blame] | 162 | help |
| 163 | Say Y here if you want to enable PCIe controller support on FSL |
| 164 | PowerPC MPC85xx, MPC86xx, B series, P series and T series SoCs. |
| 165 | This driver does not support SRIO_PCIE_BOOT feature. |
| 166 | |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 167 | config PCI_MPC85XX |
| 168 | bool "MPC85XX PowerPC PCI support" |
Heiko Schocher | b61cbbd | 2019-10-14 11:29:39 +0200 | [diff] [blame] | 169 | help |
| 170 | Say Y here if you want to enable PCI controller support on FSL |
| 171 | PowerPC MPC85xx SoC. |
| 172 | |
Tom Rini | 363397a | 2022-06-20 08:07:55 -0400 | [diff] [blame] | 173 | config PCI_MSC01 |
| 174 | bool "MSC01 PCI support" |
| 175 | depends on TARGET_MALTA |
| 176 | |
Marek Vasut | 5f14f7d | 2018-01-18 14:35:35 +0100 | [diff] [blame] | 177 | config PCI_RCAR_GEN2 |
| 178 | bool "Renesas RCar Gen2 PCIe driver" |
Marek Vasut | 5f14f7d | 2018-01-18 14:35:35 +0100 | [diff] [blame] | 179 | depends on RCAR_32 |
| 180 | help |
| 181 | Say Y here if you want to enable PCIe controller support on |
| 182 | Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is |
| 183 | also used to access EHCI USB controller on the SoC. |
| 184 | |
Marek Vasut | 776abed | 2018-10-16 12:49:19 +0200 | [diff] [blame] | 185 | config PCI_RCAR_GEN3 |
| 186 | bool "Renesas RCar Gen3 PCIe driver" |
Marek Vasut | 776abed | 2018-10-16 12:49:19 +0200 | [diff] [blame] | 187 | depends on RCAR_GEN3 |
| 188 | help |
| 189 | Say Y here if you want to enable PCIe controller support on |
| 190 | Renesas RCar Gen3 SoCs. |
| 191 | |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 192 | config PCI_SANDBOX |
| 193 | bool "Sandbox PCI support" |
Simon Glass | 3232bdf | 2021-08-01 18:54:44 -0600 | [diff] [blame] | 194 | depends on SANDBOX |
Simon Glass | 537849a | 2015-03-05 12:25:27 -0700 | [diff] [blame] | 195 | help |
| 196 | Support PCI on sandbox, as an emulated bus. This permits testing of |
| 197 | PCI feature such as bus scanning, device configuration and device |
| 198 | access. The available (emulated) devices are defined statically in |
| 199 | the device tree but the normal PCI scan technique is used to find |
| 200 | then. |
| 201 | |
Tom Rini | 31a8f55 | 2022-06-20 08:07:53 -0400 | [diff] [blame] | 202 | config SH7751_PCI |
| 203 | bool "SH7751 PCI controller support" |
| 204 | depends on SH |
| 205 | help |
| 206 | SuperH PCI Bridge Configuration |
| 207 | |
Simon Glass | fde7e18 | 2015-11-19 20:26:55 -0700 | [diff] [blame] | 208 | config PCI_TEGRA |
| 209 | bool "Tegra PCI support" |
Trevor Woerner | 18138ab | 2020-05-06 08:02:41 -0400 | [diff] [blame] | 210 | depends on ARCH_TEGRA |
Stephen Warren | bbc5b36 | 2016-08-05 16:10:34 -0600 | [diff] [blame] | 211 | depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186) |
Simon Glass | fde7e18 | 2015-11-19 20:26:55 -0700 | [diff] [blame] | 212 | help |
| 213 | Enable support for the PCIe controller found on some generations of |
| 214 | Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has |
| 215 | 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports |
| 216 | with a total of 5 lanes. Some boards require this for Ethernet |
| 217 | support to work (e.g. beaver, jetson-tk1). |
| 218 | |
Suneel Garapati | 638d705 | 2019-10-19 17:28:01 -0700 | [diff] [blame] | 219 | config PCI_OCTEONTX |
| 220 | bool "OcteonTX PCI support" |
| 221 | depends on (ARCH_OCTEONTX || ARCH_OCTEONTX2) |
| 222 | help |
| 223 | Enable support for the OcteonTX/TX2 SoC family ECAM/PEM controllers. |
| 224 | These controllers provide PCI configuration access to all on-board |
| 225 | peripherals so it should only be disabled for testing purposes |
| 226 | |
Stefan Roese | ddafdb9 | 2021-04-07 08:43:35 +0200 | [diff] [blame] | 227 | config PCIE_OCTEON |
| 228 | bool "MIPS Octeon PCIe support" |
| 229 | depends on ARCH_OCTEON |
| 230 | help |
| 231 | Enable support for the MIPS Octeon SoC family PCIe controllers. |
| 232 | |
Paul Burton | a29e45a | 2016-09-08 07:47:31 +0100 | [diff] [blame] | 233 | config PCI_XILINX |
| 234 | bool "Xilinx AXI Bridge for PCI Express" |
Paul Burton | a29e45a | 2016-09-08 07:47:31 +0100 | [diff] [blame] | 235 | help |
| 236 | Enable support for the Xilinx AXI bridge for PCI express, an IP block |
| 237 | which can be used on some generations of Xilinx FPGAs. |
| 238 | |
Minghuan Lian | 80afc63 | 2016-12-13 14:54:17 +0800 | [diff] [blame] | 239 | config PCIE_LAYERSCAPE |
Hou Zhiqiang | ed188aa | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 240 | bool |
Hou Zhiqiang | ed188aa | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 241 | |
| 242 | config PCIE_LAYERSCAPE_RC |
| 243 | bool "Layerscape PCIe Root Complex mode support" |
Hou Zhiqiang | ed188aa | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 244 | select PCIE_LAYERSCAPE |
Minghuan Lian | 80afc63 | 2016-12-13 14:54:17 +0800 | [diff] [blame] | 245 | help |
Hou Zhiqiang | ed188aa | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 246 | Enable Layerscape PCIe Root Complex mode driver support. The Layerscape |
| 247 | SoC may have one or several PCIe controllers. Each controller can be |
| 248 | configured to Root Complex mode by clearing the corresponding bit of |
| 249 | RCW[HOST_AGT_PEX]. |
| 250 | |
Laurentiu Tudor | 2a5bbb1 | 2020-09-10 12:42:19 +0300 | [diff] [blame] | 251 | config PCI_IOMMU_EXTRA_MAPPINGS |
| 252 | bool "Support for specifying extra IOMMU mappings for PCI" |
| 253 | depends on PCIE_LAYERSCAPE_RC |
| 254 | help |
| 255 | Enable support for specifying extra IOMMU mappings for PCI |
| 256 | controllers through a special env var called "pci_iommu_extra" or |
| 257 | through a device tree property named "pci-iommu-extra" placed in |
| 258 | the node describing the PCI controller. |
| 259 | The intent is to cover SR-IOV scenarios which need mappings for VFs |
| 260 | and PCI hot-plug scenarios. More documentation can be found under: |
| 261 | arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra |
| 262 | |
Hou Zhiqiang | ed188aa | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 263 | config PCIE_LAYERSCAPE_EP |
| 264 | bool "Layerscape PCIe Endpoint mode support" |
Hou Zhiqiang | ed188aa | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 265 | select PCIE_LAYERSCAPE |
| 266 | select PCI_ENDPOINT |
| 267 | help |
| 268 | Enable Layerscape PCIe Endpoint mode driver support. The Layerscape |
| 269 | SoC may have one or several PCIe controllers. Each controller can be |
| 270 | configured to Endpoint mode by setting the corresponding bit of |
| 271 | RCW[HOST_AGT_PEX]. |
Minghuan Lian | 80afc63 | 2016-12-13 14:54:17 +0800 | [diff] [blame] | 272 | |
Hou Zhiqiang | 07ce19f | 2019-04-08 10:15:46 +0000 | [diff] [blame] | 273 | config PCIE_LAYERSCAPE_GEN4 |
| 274 | bool "Layerscape Gen4 PCIe support" |
Hou Zhiqiang | 07ce19f | 2019-04-08 10:15:46 +0000 | [diff] [blame] | 275 | help |
| 276 | Support PCIe Gen4 on NXP Layerscape SoCs, which may have one or |
| 277 | several PCIe controllers. The PCIe controller can work in RC or |
| 278 | EP mode according to RCW[HOST_AGT_PEX] setting. |
| 279 | |
Pankaj Bansal | ba7c966 | 2019-11-30 13:14:00 +0000 | [diff] [blame] | 280 | config FSL_PCIE_COMPAT |
| 281 | string "PCIe compatible of Kernel DT" |
Hou Zhiqiang | ed188aa | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 282 | depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4 |
Pankaj Bansal | ba7c966 | 2019-11-30 13:14:00 +0000 | [diff] [blame] | 283 | default "fsl,ls1012a-pcie" if ARCH_LS1012A |
| 284 | default "fsl,ls1028a-pcie" if ARCH_LS1028A |
| 285 | default "fsl,ls1043a-pcie" if ARCH_LS1043A |
| 286 | default "fsl,ls1046a-pcie" if ARCH_LS1046A |
| 287 | default "fsl,ls2080a-pcie" if ARCH_LS2080A |
| 288 | default "fsl,ls1088a-pcie" if ARCH_LS1088A |
Hou Zhiqiang | 18c62df | 2021-12-07 18:13:12 +0800 | [diff] [blame] | 289 | default "fsl,ls2088a-pcie" if ARCH_LX2160A || ARCH_LX2162A |
Pankaj Bansal | ba7c966 | 2019-11-30 13:14:00 +0000 | [diff] [blame] | 290 | default "fsl,ls1021a-pcie" if ARCH_LS1021A |
| 291 | help |
| 292 | This compatible is used to find pci controller node in Kernel DT |
| 293 | to complete fixup. |
| 294 | |
Pankaj Bansal | 63618e7 | 2019-11-30 13:14:10 +0000 | [diff] [blame] | 295 | config FSL_PCIE_EP_COMPAT |
| 296 | string "PCIe EP compatible of Kernel DT" |
Hou Zhiqiang | ed188aa | 2020-07-09 23:31:42 +0800 | [diff] [blame] | 297 | depends on PCIE_LAYERSCAPE_RC || PCIE_LAYERSCAPE_GEN4 |
Pankaj Bansal | 63618e7 | 2019-11-30 13:14:10 +0000 | [diff] [blame] | 298 | default "fsl,ls-pcie-ep" |
| 299 | help |
| 300 | This compatible is used to find pci controller ep node in Kernel DT |
| 301 | to complete fixup. |
| 302 | |
Tom Rini | 4547a1b | 2022-06-20 08:07:46 -0400 | [diff] [blame] | 303 | config PCIE_IMX |
| 304 | bool "i.MX PCIe support" |
| 305 | depends on ARCH_MX6 |
| 306 | |
Ley Foon Tan | 7c45862 | 2018-04-20 21:55:45 +0800 | [diff] [blame] | 307 | config PCIE_INTEL_FPGA |
| 308 | bool "Intel FPGA PCIe support" |
Ley Foon Tan | 7c45862 | 2018-04-20 21:55:45 +0800 | [diff] [blame] | 309 | help |
| 310 | Say Y here if you want to enable PCIe controller support on Intel |
| 311 | FPGA, example Stratix 10. |
| 312 | |
Srinath Mannam | 4848704 | 2020-05-12 13:29:50 +0530 | [diff] [blame] | 313 | config PCIE_IPROC |
| 314 | bool "Iproc PCIe support" |
Srinath Mannam | 4848704 | 2020-05-12 13:29:50 +0530 | [diff] [blame] | 315 | help |
| 316 | Broadcom iProc PCIe controller driver. |
| 317 | Say Y here if you want to enable Broadcom iProc PCIe controller, |
| 318 | |
Stefan Roese | 94f453e | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 319 | config PCI_MVEBU |
Pali Rohár | 4364071 | 2022-01-13 14:28:04 +0100 | [diff] [blame] | 320 | bool "Enable Kirkwood / Armada 370/XP/375/38x PCIe driver" |
| 321 | depends on (ARCH_KIRKWOOD || ARCH_MVEBU) |
Stefan Roese | 94f453e | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 322 | select MISC |
Pali Rohár | 94c30f9 | 2021-12-21 12:20:19 +0100 | [diff] [blame] | 323 | select DM_RESET |
Pali Rohár | ca3756c | 2022-08-05 16:03:41 +0200 | [diff] [blame] | 324 | select DM_GPIO |
Stefan Roese | 94f453e | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 325 | help |
| 326 | Say Y here if you want to enable PCIe controller support on |
Pali Rohár | 4364071 | 2022-01-13 14:28:04 +0100 | [diff] [blame] | 327 | Kirkwood and Armada 370/XP/375/38x SoCs. |
Stefan Roese | 94f453e | 2019-01-25 11:52:43 +0100 | [diff] [blame] | 328 | |
Neil Armstrong | dfadb94 | 2021-03-25 15:49:18 +0100 | [diff] [blame] | 329 | config PCIE_DW_COMMON |
| 330 | bool |
Neil Armstrong | dfadb94 | 2021-03-25 15:49:18 +0100 | [diff] [blame] | 331 | |
Sekhar Nori | 03c396b | 2019-08-01 19:12:57 +0530 | [diff] [blame] | 332 | config PCI_KEYSTONE |
| 333 | bool "TI Keystone PCIe controller" |
Neil Armstrong | 1a03182 | 2021-03-25 15:49:19 +0100 | [diff] [blame] | 334 | select PCIE_DW_COMMON |
Sekhar Nori | 03c396b | 2019-08-01 19:12:57 +0530 | [diff] [blame] | 335 | help |
| 336 | Say Y here if you want to enable PCI controller support on AM654 SoC. |
| 337 | |
Ryder Lee | 42d3745 | 2019-08-22 12:26:49 +0200 | [diff] [blame] | 338 | config PCIE_MEDIATEK |
| 339 | bool "MediaTek PCIe Gen2 controller" |
Ryder Lee | 42d3745 | 2019-08-22 12:26:49 +0200 | [diff] [blame] | 340 | depends on ARCH_MEDIATEK |
| 341 | help |
| 342 | Say Y here if you want to enable Gen2 PCIe controller, |
| 343 | which could be found on MT7623 SoC family. |
| 344 | |
Neil Armstrong | 2c32c70 | 2021-03-25 15:49:21 +0100 | [diff] [blame] | 345 | config PCIE_DW_MESON |
| 346 | bool "Amlogic Meson DesignWare based PCIe controller" |
| 347 | depends on ARCH_MESON |
| 348 | select PCIE_DW_COMMON |
| 349 | help |
| 350 | Say Y here if you want to enable DW PCIe controller support on |
| 351 | Amlogic SoCs. |
| 352 | |
Jagan Teki | 99d5906 | 2020-05-09 22:26:21 +0530 | [diff] [blame] | 353 | config PCIE_ROCKCHIP |
| 354 | bool "Enable Rockchip PCIe driver" |
Michal Simek | a261fdc | 2020-08-19 10:44:15 +0200 | [diff] [blame] | 355 | depends on ARCH_ROCKCHIP |
Jagan Teki | ce920e0 | 2020-07-09 23:41:02 +0530 | [diff] [blame] | 356 | select PHY_ROCKCHIP_PCIE |
Jagan Teki | 99d5906 | 2020-05-09 22:26:21 +0530 | [diff] [blame] | 357 | default y if ROCKCHIP_RK3399 |
| 358 | help |
| 359 | Say Y here if you want to enable PCIe controller support on |
| 360 | Rockchip SoCs. |
| 361 | |
Shawn Lin | 9ddc078 | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 362 | config PCIE_DW_ROCKCHIP |
| 363 | bool "Rockchip DesignWare based PCIe controller" |
| 364 | depends on ARCH_ROCKCHIP |
Neil Armstrong | c90f3d0 | 2021-03-25 15:49:20 +0100 | [diff] [blame] | 365 | select PCIE_DW_COMMON |
Shawn Lin | 9ddc078 | 2021-01-15 18:01:22 +0800 | [diff] [blame] | 366 | select PHY_ROCKCHIP_SNPS_PCIE3 |
| 367 | help |
| 368 | Say Y here if you want to enable DW PCIe controller support on |
| 369 | Rockchip SoCs. |
| 370 | |
Sylwester Nawrocki | 7b1c3f6 | 2020-05-25 13:39:58 +0200 | [diff] [blame] | 371 | config PCI_BRCMSTB |
| 372 | bool "Broadcom STB PCIe controller" |
Sylwester Nawrocki | 7b1c3f6 | 2020-05-25 13:39:58 +0200 | [diff] [blame] | 373 | depends on ARCH_BCM283X |
| 374 | help |
| 375 | Say Y here if you want to enable support for PCIe controller |
| 376 | on Broadcom set-top-box (STB) SoCs. |
| 377 | This driver currently supports only BCM2711 SoC and RC mode |
| 378 | of the controller. |
Kunihiko Hayashi | e22c256 | 2021-07-06 19:01:09 +0900 | [diff] [blame] | 379 | |
| 380 | config PCIE_UNIPHIER |
| 381 | bool "Socionext UniPhier PCIe driver" |
Kunihiko Hayashi | e22c256 | 2021-07-06 19:01:09 +0900 | [diff] [blame] | 382 | depends on ARCH_UNIPHIER |
| 383 | select PHY_UNIPHIER_PCIE |
| 384 | help |
| 385 | Say Y here if you want to enable PCIe controller support on |
| 386 | UniPhier SoCs. |
| 387 | |
Stefan Roese | 2f5ad77 | 2023-05-25 11:49:18 +0200 | [diff] [blame] | 388 | config PCIE_XILINX_NWL |
| 389 | bool "Xilinx NWL PCIe controller" |
| 390 | depends on ARCH_ZYNQMP |
| 391 | help |
| 392 | Say 'Y' here if you want support for Xilinx / AMD NWL PCIe |
| 393 | controller as Root Port. |
| 394 | |
Tom Rini | af27382 | 2016-10-26 17:15:37 -0400 | [diff] [blame] | 395 | endif |