blob: 94b2a41e1404af4886860c76e1fb5c886068070b [file] [log] [blame]
wdenk682011f2003-06-03 23:54:09 +00001/**************************************************************************
Andre Schwarzac3315c2008-03-06 16:45:44 +01002Intel Pro 1000 for ppcboot/das-u-boot
wdenk682011f2003-06-03 23:54:09 +00003Drivers are port from Intel's Linux driver e1000-4.3.15
4and from Etherboot pro 1000 driver by mrakes at vivato dot net
5tested on both gig copper and gig fiber boards
6***************************************************************************/
7/*******************************************************************************
8
wdenk8bde7f72003-06-27 21:31:46 +00009
wdenk682011f2003-06-03 23:54:09 +000010 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
wdenk8bde7f72003-06-27 21:31:46 +000011
12 This program is free software; you can redistribute it and/or modify it
13 under the terms of the GNU General Public License as published by the Free
14 Software Foundation; either version 2 of the License, or (at your option)
wdenk682011f2003-06-03 23:54:09 +000015 any later version.
wdenk8bde7f72003-06-27 21:31:46 +000016
17 This program is distributed in the hope that it will be useful, but WITHOUT
18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
wdenk682011f2003-06-03 23:54:09 +000020 more details.
wdenk8bde7f72003-06-27 21:31:46 +000021
wdenk682011f2003-06-03 23:54:09 +000022 You should have received a copy of the GNU General Public License along with
wdenk8bde7f72003-06-27 21:31:46 +000023 this program; if not, write to the Free Software Foundation, Inc., 59
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070024 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
wdenk8bde7f72003-06-27 21:31:46 +000025
wdenk682011f2003-06-03 23:54:09 +000026 The full GNU General Public License is included in this distribution in the
27 file called LICENSE.
wdenk8bde7f72003-06-27 21:31:46 +000028
wdenk682011f2003-06-03 23:54:09 +000029 Contact Information:
30 Linux NICS <linux.nics@intel.com>
31 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32
33*******************************************************************************/
34/*
35 * Copyright (C) Archway Digital Solutions.
36 *
37 * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
38 * 2/9/2002
39 *
40 * Copyright (C) Linux Networx.
41 * Massive upgrade to work with the new intel gigabit NICs.
42 * <ebiederman at lnxi dot com>
Roy Zang2c2668f2011-01-21 11:29:38 +080043 *
44 * Copyright 2011 Freescale Semiconductor, Inc.
wdenk682011f2003-06-03 23:54:09 +000045 */
46
47#include "e1000.h"
48
wdenk682011f2003-06-03 23:54:09 +000049#define TOUT_LOOP 100000
50
Timur Tabif81ecb52009-08-17 15:55:38 -050051#define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
wdenk682011f2003-06-03 23:54:09 +000052#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
wdenk682011f2003-06-03 23:54:09 +000053
Roy Zang9ea005f2009-08-22 03:49:52 +080054#define E1000_DEFAULT_PCI_PBA 0x00000030
55#define E1000_DEFAULT_PCIE_PBA 0x000a0026
wdenk682011f2003-06-03 23:54:09 +000056
57/* NIC specific static variables go here */
58
59static char tx_pool[128 + 16];
60static char rx_pool[128 + 16];
61static char packet[2096];
62
63static struct e1000_tx_desc *tx_base;
64static struct e1000_rx_desc *rx_base;
65
66static int tx_tail;
67static int rx_tail, rx_last;
68
Kyle Moffettd60626f82011-10-18 11:05:26 +000069static struct pci_device_id e1000_supported[] = {
wdenk682011f2003-06-03 23:54:09 +000070 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542},
71 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER},
72 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER},
73 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER},
74 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER},
75 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER},
76 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM},
77 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM},
78 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER},
Paul Gortmaker8915f112008-07-09 17:50:45 -040079 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER},
wdenk682011f2003-06-03 23:54:09 +000080 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER},
81 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER},
82 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER},
Reinhard Arlt2ab4a4d2009-12-04 09:52:17 +010083 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER},
wdenk682011f2003-06-03 23:54:09 +000084 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM},
Andre Schwarzac3315c2008-03-06 16:45:44 +010085 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER},
Wolfgang Grandeggeraa3b8bf2008-05-28 19:55:19 +020086 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF},
Roy Zangaa070782009-07-31 13:34:02 +080087 /* E1000 PCIe card */
88 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER},
89 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER },
90 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES },
91 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER},
92 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER},
93 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER},
94 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE},
95 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL},
96 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD},
97 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER},
98 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER},
99 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES},
100 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI},
101 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E},
102 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT},
103 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L},
Roy Zang2c2668f2011-01-21 11:29:38 +0800104 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L},
Roy Zangaa070782009-07-31 13:34:02 +0800105 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3},
106 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT},
107 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT},
108 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT},
109 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT},
Stefan Althoefer1bc43432008-12-20 19:40:41 +0100110 {}
wdenk682011f2003-06-03 23:54:09 +0000111};
112
113/* Function forward declarations */
114static int e1000_setup_link(struct eth_device *nic);
115static int e1000_setup_fiber_link(struct eth_device *nic);
116static int e1000_setup_copper_link(struct eth_device *nic);
117static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
118static void e1000_config_collision_dist(struct e1000_hw *hw);
119static int e1000_config_mac_to_phy(struct e1000_hw *hw);
120static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
121static int e1000_check_for_link(struct eth_device *nic);
122static int e1000_wait_autoneg(struct e1000_hw *hw);
Roy Zangaa070782009-07-31 13:34:02 +0800123static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
wdenk682011f2003-06-03 23:54:09 +0000124 uint16_t * duplex);
125static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
126 uint16_t * phy_data);
127static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
128 uint16_t phy_data);
Roy Zangaa070782009-07-31 13:34:02 +0800129static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
wdenk682011f2003-06-03 23:54:09 +0000130static int e1000_phy_reset(struct e1000_hw *hw);
131static int e1000_detect_gig_phy(struct e1000_hw *hw);
Roy Zangaa070782009-07-31 13:34:02 +0800132static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
133static void e1000_set_media_type(struct e1000_hw *hw);
wdenk682011f2003-06-03 23:54:09 +0000134
Roy Zangaa070782009-07-31 13:34:02 +0800135static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
136static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
wdenk682011f2003-06-03 23:54:09 +0000137
Wolfgang Denk7521af12005-10-09 01:04:33 +0200138#ifndef CONFIG_AP1000 /* remove for warnings */
Roy Zangecbd2072009-08-11 03:48:05 +0800139static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
140 uint16_t words,
141 uint16_t *data);
wdenk682011f2003-06-03 23:54:09 +0000142/******************************************************************************
143 * Raises the EEPROM's clock input.
144 *
145 * hw - Struct containing variables accessed by shared code
146 * eecd - EECD's current value
147 *****************************************************************************/
Kyle Moffett2326a942011-10-18 11:05:28 +0000148void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
wdenk682011f2003-06-03 23:54:09 +0000149{
150 /* Raise the clock input to the EEPROM (by setting the SK bit), and then
151 * wait 50 microseconds.
152 */
153 *eecd = *eecd | E1000_EECD_SK;
154 E1000_WRITE_REG(hw, EECD, *eecd);
155 E1000_WRITE_FLUSH(hw);
156 udelay(50);
157}
158
159/******************************************************************************
160 * Lowers the EEPROM's clock input.
161 *
wdenk8bde7f72003-06-27 21:31:46 +0000162 * hw - Struct containing variables accessed by shared code
wdenk682011f2003-06-03 23:54:09 +0000163 * eecd - EECD's current value
164 *****************************************************************************/
Kyle Moffett2326a942011-10-18 11:05:28 +0000165void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
wdenk682011f2003-06-03 23:54:09 +0000166{
wdenk8bde7f72003-06-27 21:31:46 +0000167 /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
168 * wait 50 microseconds.
wdenk682011f2003-06-03 23:54:09 +0000169 */
170 *eecd = *eecd & ~E1000_EECD_SK;
171 E1000_WRITE_REG(hw, EECD, *eecd);
172 E1000_WRITE_FLUSH(hw);
173 udelay(50);
174}
175
176/******************************************************************************
177 * Shift data bits out to the EEPROM.
178 *
179 * hw - Struct containing variables accessed by shared code
180 * data - data to send to the EEPROM
181 * count - number of bits to shift out
182 *****************************************************************************/
183static void
184e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
185{
186 uint32_t eecd;
187 uint32_t mask;
188
189 /* We need to shift "count" bits out to the EEPROM. So, value in the
190 * "data" parameter will be shifted out to the EEPROM one bit at a time.
wdenk8bde7f72003-06-27 21:31:46 +0000191 * In order to do this, "data" must be broken down into bits.
wdenk682011f2003-06-03 23:54:09 +0000192 */
193 mask = 0x01 << (count - 1);
194 eecd = E1000_READ_REG(hw, EECD);
195 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
196 do {
197 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
198 * and then raising and then lowering the clock (the SK bit controls
199 * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
200 * by setting "DI" to "0" and then raising and then lowering the clock.
201 */
202 eecd &= ~E1000_EECD_DI;
203
204 if (data & mask)
205 eecd |= E1000_EECD_DI;
206
207 E1000_WRITE_REG(hw, EECD, eecd);
208 E1000_WRITE_FLUSH(hw);
209
210 udelay(50);
211
212 e1000_raise_ee_clk(hw, &eecd);
213 e1000_lower_ee_clk(hw, &eecd);
214
215 mask = mask >> 1;
216
217 } while (mask);
218
219 /* We leave the "DI" bit set to "0" when we leave this routine. */
220 eecd &= ~E1000_EECD_DI;
221 E1000_WRITE_REG(hw, EECD, eecd);
222}
223
224/******************************************************************************
225 * Shift data bits in from the EEPROM
226 *
227 * hw - Struct containing variables accessed by shared code
228 *****************************************************************************/
229static uint16_t
Roy Zangaa070782009-07-31 13:34:02 +0800230e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
wdenk682011f2003-06-03 23:54:09 +0000231{
232 uint32_t eecd;
233 uint32_t i;
234 uint16_t data;
235
Roy Zangaa070782009-07-31 13:34:02 +0800236 /* In order to read a register from the EEPROM, we need to shift 'count'
237 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
238 * input to the EEPROM (setting the SK bit), and then reading the
239 * value of the "DO" bit. During this "shifting in" process the
240 * "DI" bit should always be clear.
wdenk682011f2003-06-03 23:54:09 +0000241 */
242
243 eecd = E1000_READ_REG(hw, EECD);
244
245 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
246 data = 0;
247
Roy Zangaa070782009-07-31 13:34:02 +0800248 for (i = 0; i < count; i++) {
wdenk682011f2003-06-03 23:54:09 +0000249 data = data << 1;
250 e1000_raise_ee_clk(hw, &eecd);
251
252 eecd = E1000_READ_REG(hw, EECD);
253
254 eecd &= ~(E1000_EECD_DI);
255 if (eecd & E1000_EECD_DO)
256 data |= 1;
257
258 e1000_lower_ee_clk(hw, &eecd);
259 }
260
261 return data;
262}
263
264/******************************************************************************
wdenk682011f2003-06-03 23:54:09 +0000265 * Returns EEPROM to a "standby" state
wdenk8bde7f72003-06-27 21:31:46 +0000266 *
wdenk682011f2003-06-03 23:54:09 +0000267 * hw - Struct containing variables accessed by shared code
268 *****************************************************************************/
Kyle Moffett2326a942011-10-18 11:05:28 +0000269void e1000_standby_eeprom(struct e1000_hw *hw)
wdenk682011f2003-06-03 23:54:09 +0000270{
Roy Zangaa070782009-07-31 13:34:02 +0800271 struct e1000_eeprom_info *eeprom = &hw->eeprom;
wdenk682011f2003-06-03 23:54:09 +0000272 uint32_t eecd;
273
274 eecd = E1000_READ_REG(hw, EECD);
275
Roy Zangaa070782009-07-31 13:34:02 +0800276 if (eeprom->type == e1000_eeprom_microwire) {
277 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
278 E1000_WRITE_REG(hw, EECD, eecd);
279 E1000_WRITE_FLUSH(hw);
280 udelay(eeprom->delay_usec);
wdenk682011f2003-06-03 23:54:09 +0000281
Roy Zangaa070782009-07-31 13:34:02 +0800282 /* Clock high */
283 eecd |= E1000_EECD_SK;
284 E1000_WRITE_REG(hw, EECD, eecd);
285 E1000_WRITE_FLUSH(hw);
286 udelay(eeprom->delay_usec);
wdenk682011f2003-06-03 23:54:09 +0000287
Roy Zangaa070782009-07-31 13:34:02 +0800288 /* Select EEPROM */
289 eecd |= E1000_EECD_CS;
290 E1000_WRITE_REG(hw, EECD, eecd);
291 E1000_WRITE_FLUSH(hw);
292 udelay(eeprom->delay_usec);
wdenk682011f2003-06-03 23:54:09 +0000293
Roy Zangaa070782009-07-31 13:34:02 +0800294 /* Clock low */
295 eecd &= ~E1000_EECD_SK;
296 E1000_WRITE_REG(hw, EECD, eecd);
297 E1000_WRITE_FLUSH(hw);
298 udelay(eeprom->delay_usec);
299 } else if (eeprom->type == e1000_eeprom_spi) {
300 /* Toggle CS to flush commands */
301 eecd |= E1000_EECD_CS;
302 E1000_WRITE_REG(hw, EECD, eecd);
303 E1000_WRITE_FLUSH(hw);
304 udelay(eeprom->delay_usec);
305 eecd &= ~E1000_EECD_CS;
306 E1000_WRITE_REG(hw, EECD, eecd);
307 E1000_WRITE_FLUSH(hw);
308 udelay(eeprom->delay_usec);
309 }
310}
311
312/***************************************************************************
313* Description: Determines if the onboard NVM is FLASH or EEPROM.
314*
315* hw - Struct containing variables accessed by shared code
316****************************************************************************/
317static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
318{
319 uint32_t eecd = 0;
320
321 DEBUGFUNC();
322
323 if (hw->mac_type == e1000_ich8lan)
324 return FALSE;
325
Roy Zang2c2668f2011-01-21 11:29:38 +0800326 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
Roy Zangaa070782009-07-31 13:34:02 +0800327 eecd = E1000_READ_REG(hw, EECD);
328
329 /* Isolate bits 15 & 16 */
330 eecd = ((eecd >> 15) & 0x03);
331
332 /* If both bits are set, device is Flash type */
333 if (eecd == 0x03)
334 return FALSE;
335 }
336 return TRUE;
337}
338
339/******************************************************************************
340 * Prepares EEPROM for access
341 *
342 * hw - Struct containing variables accessed by shared code
343 *
344 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
345 * function should be called before issuing a command to the EEPROM.
346 *****************************************************************************/
Kyle Moffett2326a942011-10-18 11:05:28 +0000347int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
Roy Zangaa070782009-07-31 13:34:02 +0800348{
349 struct e1000_eeprom_info *eeprom = &hw->eeprom;
350 uint32_t eecd, i = 0;
351
Timur Tabif81ecb52009-08-17 15:55:38 -0500352 DEBUGFUNC();
Roy Zangaa070782009-07-31 13:34:02 +0800353
354 if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
355 return -E1000_ERR_SWFW_SYNC;
356 eecd = E1000_READ_REG(hw, EECD);
357
Roy Zang2c2668f2011-01-21 11:29:38 +0800358 if (hw->mac_type != e1000_82573 || hw->mac_type != e1000_82574) {
Roy Zangaa070782009-07-31 13:34:02 +0800359 /* Request EEPROM Access */
360 if (hw->mac_type > e1000_82544) {
361 eecd |= E1000_EECD_REQ;
362 E1000_WRITE_REG(hw, EECD, eecd);
363 eecd = E1000_READ_REG(hw, EECD);
364 while ((!(eecd & E1000_EECD_GNT)) &&
365 (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
366 i++;
367 udelay(5);
368 eecd = E1000_READ_REG(hw, EECD);
369 }
370 if (!(eecd & E1000_EECD_GNT)) {
371 eecd &= ~E1000_EECD_REQ;
372 E1000_WRITE_REG(hw, EECD, eecd);
373 DEBUGOUT("Could not acquire EEPROM grant\n");
374 return -E1000_ERR_EEPROM;
375 }
376 }
377 }
378
379 /* Setup EEPROM for Read/Write */
380
381 if (eeprom->type == e1000_eeprom_microwire) {
382 /* Clear SK and DI */
383 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
384 E1000_WRITE_REG(hw, EECD, eecd);
385
386 /* Set CS */
387 eecd |= E1000_EECD_CS;
388 E1000_WRITE_REG(hw, EECD, eecd);
389 } else if (eeprom->type == e1000_eeprom_spi) {
390 /* Clear SK and CS */
391 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
392 E1000_WRITE_REG(hw, EECD, eecd);
393 udelay(1);
394 }
395
396 return E1000_SUCCESS;
397}
398
399/******************************************************************************
400 * Sets up eeprom variables in the hw struct. Must be called after mac_type
401 * is configured. Additionally, if this is ICH8, the flash controller GbE
402 * registers must be mapped, or this will crash.
403 *
404 * hw - Struct containing variables accessed by shared code
405 *****************************************************************************/
406static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
407{
408 struct e1000_eeprom_info *eeprom = &hw->eeprom;
409 uint32_t eecd = E1000_READ_REG(hw, EECD);
410 int32_t ret_val = E1000_SUCCESS;
411 uint16_t eeprom_size;
412
Timur Tabif81ecb52009-08-17 15:55:38 -0500413 DEBUGFUNC();
Roy Zangaa070782009-07-31 13:34:02 +0800414
415 switch (hw->mac_type) {
416 case e1000_82542_rev2_0:
417 case e1000_82542_rev2_1:
418 case e1000_82543:
419 case e1000_82544:
420 eeprom->type = e1000_eeprom_microwire;
421 eeprom->word_size = 64;
422 eeprom->opcode_bits = 3;
423 eeprom->address_bits = 6;
424 eeprom->delay_usec = 50;
425 eeprom->use_eerd = FALSE;
426 eeprom->use_eewr = FALSE;
427 break;
428 case e1000_82540:
429 case e1000_82545:
430 case e1000_82545_rev_3:
431 case e1000_82546:
432 case e1000_82546_rev_3:
433 eeprom->type = e1000_eeprom_microwire;
434 eeprom->opcode_bits = 3;
435 eeprom->delay_usec = 50;
436 if (eecd & E1000_EECD_SIZE) {
437 eeprom->word_size = 256;
438 eeprom->address_bits = 8;
439 } else {
440 eeprom->word_size = 64;
441 eeprom->address_bits = 6;
442 }
443 eeprom->use_eerd = FALSE;
444 eeprom->use_eewr = FALSE;
445 break;
446 case e1000_82541:
447 case e1000_82541_rev_2:
448 case e1000_82547:
449 case e1000_82547_rev_2:
450 if (eecd & E1000_EECD_TYPE) {
451 eeprom->type = e1000_eeprom_spi;
452 eeprom->opcode_bits = 8;
453 eeprom->delay_usec = 1;
454 if (eecd & E1000_EECD_ADDR_BITS) {
455 eeprom->page_size = 32;
456 eeprom->address_bits = 16;
457 } else {
458 eeprom->page_size = 8;
459 eeprom->address_bits = 8;
460 }
461 } else {
462 eeprom->type = e1000_eeprom_microwire;
463 eeprom->opcode_bits = 3;
464 eeprom->delay_usec = 50;
465 if (eecd & E1000_EECD_ADDR_BITS) {
466 eeprom->word_size = 256;
467 eeprom->address_bits = 8;
468 } else {
469 eeprom->word_size = 64;
470 eeprom->address_bits = 6;
471 }
472 }
473 eeprom->use_eerd = FALSE;
474 eeprom->use_eewr = FALSE;
475 break;
476 case e1000_82571:
477 case e1000_82572:
478 eeprom->type = e1000_eeprom_spi;
479 eeprom->opcode_bits = 8;
480 eeprom->delay_usec = 1;
481 if (eecd & E1000_EECD_ADDR_BITS) {
482 eeprom->page_size = 32;
483 eeprom->address_bits = 16;
484 } else {
485 eeprom->page_size = 8;
486 eeprom->address_bits = 8;
487 }
488 eeprom->use_eerd = FALSE;
489 eeprom->use_eewr = FALSE;
490 break;
491 case e1000_82573:
Roy Zang2c2668f2011-01-21 11:29:38 +0800492 case e1000_82574:
Roy Zangaa070782009-07-31 13:34:02 +0800493 eeprom->type = e1000_eeprom_spi;
494 eeprom->opcode_bits = 8;
495 eeprom->delay_usec = 1;
496 if (eecd & E1000_EECD_ADDR_BITS) {
497 eeprom->page_size = 32;
498 eeprom->address_bits = 16;
499 } else {
500 eeprom->page_size = 8;
501 eeprom->address_bits = 8;
502 }
503 eeprom->use_eerd = TRUE;
504 eeprom->use_eewr = TRUE;
505 if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
506 eeprom->type = e1000_eeprom_flash;
507 eeprom->word_size = 2048;
508
509 /* Ensure that the Autonomous FLASH update bit is cleared due to
510 * Flash update issue on parts which use a FLASH for NVM. */
511 eecd &= ~E1000_EECD_AUPDEN;
512 E1000_WRITE_REG(hw, EECD, eecd);
513 }
514 break;
515 case e1000_80003es2lan:
516 eeprom->type = e1000_eeprom_spi;
517 eeprom->opcode_bits = 8;
518 eeprom->delay_usec = 1;
519 if (eecd & E1000_EECD_ADDR_BITS) {
520 eeprom->page_size = 32;
521 eeprom->address_bits = 16;
522 } else {
523 eeprom->page_size = 8;
524 eeprom->address_bits = 8;
525 }
526 eeprom->use_eerd = TRUE;
527 eeprom->use_eewr = FALSE;
528 break;
529
530 /* ich8lan does not support currently. if needed, please
531 * add corresponding code and functions.
532 */
533#if 0
534 case e1000_ich8lan:
535 {
536 int32_t i = 0;
537
538 eeprom->type = e1000_eeprom_ich8;
539 eeprom->use_eerd = FALSE;
540 eeprom->use_eewr = FALSE;
541 eeprom->word_size = E1000_SHADOW_RAM_WORDS;
542 uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw,
543 ICH_FLASH_GFPREG);
544 /* Zero the shadow RAM structure. But don't load it from NVM
545 * so as to save time for driver init */
546 if (hw->eeprom_shadow_ram != NULL) {
547 for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
548 hw->eeprom_shadow_ram[i].modified = FALSE;
549 hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
550 }
551 }
552
553 hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
554 ICH_FLASH_SECTOR_SIZE;
555
556 hw->flash_bank_size = ((flash_size >> 16)
557 & ICH_GFPREG_BASE_MASK) + 1;
558 hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
559
560 hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
561
562 hw->flash_bank_size /= 2 * sizeof(uint16_t);
563 break;
564 }
565#endif
566 default:
567 break;
568 }
569
570 if (eeprom->type == e1000_eeprom_spi) {
571 /* eeprom_size will be an enum [0..8] that maps
572 * to eeprom sizes 128B to
573 * 32KB (incremented by powers of 2).
574 */
575 if (hw->mac_type <= e1000_82547_rev_2) {
576 /* Set to default value for initial eeprom read. */
577 eeprom->word_size = 64;
578 ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
579 &eeprom_size);
580 if (ret_val)
581 return ret_val;
582 eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
583 >> EEPROM_SIZE_SHIFT;
584 /* 256B eeprom size was not supported in earlier
585 * hardware, so we bump eeprom_size up one to
586 * ensure that "1" (which maps to 256B) is never
587 * the result used in the shifting logic below. */
588 if (eeprom_size)
589 eeprom_size++;
590 } else {
591 eeprom_size = (uint16_t)((eecd &
592 E1000_EECD_SIZE_EX_MASK) >>
593 E1000_EECD_SIZE_EX_SHIFT);
594 }
595
596 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
597 }
598 return ret_val;
599}
600
601/******************************************************************************
602 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
603 *
604 * hw - Struct containing variables accessed by shared code
605 *****************************************************************************/
606static int32_t
607e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
608{
609 uint32_t attempts = 100000;
610 uint32_t i, reg = 0;
611 int32_t done = E1000_ERR_EEPROM;
612
613 for (i = 0; i < attempts; i++) {
614 if (eerd == E1000_EEPROM_POLL_READ)
615 reg = E1000_READ_REG(hw, EERD);
616 else
617 reg = E1000_READ_REG(hw, EEWR);
618
619 if (reg & E1000_EEPROM_RW_REG_DONE) {
620 done = E1000_SUCCESS;
621 break;
622 }
623 udelay(5);
624 }
625
626 return done;
627}
628
629/******************************************************************************
630 * Reads a 16 bit word from the EEPROM using the EERD register.
631 *
632 * hw - Struct containing variables accessed by shared code
633 * offset - offset of word in the EEPROM to read
634 * data - word read from the EEPROM
635 * words - number of words to read
636 *****************************************************************************/
637static int32_t
638e1000_read_eeprom_eerd(struct e1000_hw *hw,
639 uint16_t offset,
640 uint16_t words,
641 uint16_t *data)
642{
643 uint32_t i, eerd = 0;
644 int32_t error = 0;
645
646 for (i = 0; i < words; i++) {
647 eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
648 E1000_EEPROM_RW_REG_START;
649
650 E1000_WRITE_REG(hw, EERD, eerd);
651 error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
652
653 if (error)
654 break;
655 data[i] = (E1000_READ_REG(hw, EERD) >>
656 E1000_EEPROM_RW_REG_DATA);
657
658 }
659
660 return error;
661}
662
Kyle Moffett2326a942011-10-18 11:05:28 +0000663void e1000_release_eeprom(struct e1000_hw *hw)
Roy Zangaa070782009-07-31 13:34:02 +0800664{
665 uint32_t eecd;
666
667 DEBUGFUNC();
668
669 eecd = E1000_READ_REG(hw, EECD);
670
671 if (hw->eeprom.type == e1000_eeprom_spi) {
672 eecd |= E1000_EECD_CS; /* Pull CS high */
673 eecd &= ~E1000_EECD_SK; /* Lower SCK */
674
675 E1000_WRITE_REG(hw, EECD, eecd);
676
677 udelay(hw->eeprom.delay_usec);
678 } else if (hw->eeprom.type == e1000_eeprom_microwire) {
679 /* cleanup eeprom */
680
681 /* CS on Microwire is active-high */
682 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
683
684 E1000_WRITE_REG(hw, EECD, eecd);
685
686 /* Rising edge of clock */
687 eecd |= E1000_EECD_SK;
688 E1000_WRITE_REG(hw, EECD, eecd);
689 E1000_WRITE_FLUSH(hw);
690 udelay(hw->eeprom.delay_usec);
691
692 /* Falling edge of clock */
693 eecd &= ~E1000_EECD_SK;
694 E1000_WRITE_REG(hw, EECD, eecd);
695 E1000_WRITE_FLUSH(hw);
696 udelay(hw->eeprom.delay_usec);
697 }
698
699 /* Stop requesting EEPROM access */
700 if (hw->mac_type > e1000_82544) {
701 eecd &= ~E1000_EECD_REQ;
702 E1000_WRITE_REG(hw, EECD, eecd);
703 }
704}
705/******************************************************************************
706 * Reads a 16 bit word from the EEPROM.
707 *
708 * hw - Struct containing variables accessed by shared code
709 *****************************************************************************/
710static int32_t
711e1000_spi_eeprom_ready(struct e1000_hw *hw)
712{
713 uint16_t retry_count = 0;
714 uint8_t spi_stat_reg;
715
716 DEBUGFUNC();
717
718 /* Read "Status Register" repeatedly until the LSB is cleared. The
719 * EEPROM will signal that the command has been completed by clearing
720 * bit 0 of the internal status register. If it's not cleared within
721 * 5 milliseconds, then error out.
722 */
723 retry_count = 0;
724 do {
725 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
726 hw->eeprom.opcode_bits);
727 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
728 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
729 break;
730
731 udelay(5);
732 retry_count += 5;
733
734 e1000_standby_eeprom(hw);
735 } while (retry_count < EEPROM_MAX_RETRY_SPI);
736
737 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
738 * only 0-5mSec on 5V devices)
739 */
740 if (retry_count >= EEPROM_MAX_RETRY_SPI) {
741 DEBUGOUT("SPI EEPROM Status error\n");
742 return -E1000_ERR_EEPROM;
743 }
744
745 return E1000_SUCCESS;
wdenk682011f2003-06-03 23:54:09 +0000746}
747
748/******************************************************************************
749 * Reads a 16 bit word from the EEPROM.
750 *
751 * hw - Struct containing variables accessed by shared code
752 * offset - offset of word in the EEPROM to read
wdenk8bde7f72003-06-27 21:31:46 +0000753 * data - word read from the EEPROM
wdenk682011f2003-06-03 23:54:09 +0000754 *****************************************************************************/
Roy Zangaa070782009-07-31 13:34:02 +0800755static int32_t
756e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
757 uint16_t words, uint16_t *data)
wdenk682011f2003-06-03 23:54:09 +0000758{
Roy Zangaa070782009-07-31 13:34:02 +0800759 struct e1000_eeprom_info *eeprom = &hw->eeprom;
wdenk682011f2003-06-03 23:54:09 +0000760 uint32_t i = 0;
wdenk682011f2003-06-03 23:54:09 +0000761
Roy Zangaa070782009-07-31 13:34:02 +0800762 DEBUGFUNC();
763
764 /* If eeprom is not yet detected, do so now */
765 if (eeprom->word_size == 0)
766 e1000_init_eeprom_params(hw);
767
768 /* A check for invalid values: offset too large, too many words,
769 * and not enough words.
770 */
771 if ((offset >= eeprom->word_size) ||
772 (words > eeprom->word_size - offset) ||
773 (words == 0)) {
774 DEBUGOUT("\"words\" parameter out of bounds."
775 "Words = %d, size = %d\n", offset, eeprom->word_size);
776 return -E1000_ERR_EEPROM;
777 }
778
779 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
780 * directly. In this case, we need to acquire the EEPROM so that
781 * FW or other port software does not interrupt.
782 */
783 if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
784 hw->eeprom.use_eerd == FALSE) {
785
786 /* Prepare the EEPROM for bit-bang reading */
787 if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
788 return -E1000_ERR_EEPROM;
789 }
790
791 /* Eerd register EEPROM access requires no eeprom aquire/release */
792 if (eeprom->use_eerd == TRUE)
793 return e1000_read_eeprom_eerd(hw, offset, words, data);
794
795 /* ich8lan does not support currently. if needed, please
796 * add corresponding code and functions.
797 */
798#if 0
799 /* ICH EEPROM access is done via the ICH flash controller */
800 if (eeprom->type == e1000_eeprom_ich8)
801 return e1000_read_eeprom_ich8(hw, offset, words, data);
802#endif
803 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
804 * acquired the EEPROM at this point, so any returns should relase it */
805 if (eeprom->type == e1000_eeprom_spi) {
806 uint16_t word_in;
807 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
808
809 if (e1000_spi_eeprom_ready(hw)) {
810 e1000_release_eeprom(hw);
wdenk682011f2003-06-03 23:54:09 +0000811 return -E1000_ERR_EEPROM;
812 }
Roy Zangaa070782009-07-31 13:34:02 +0800813
814 e1000_standby_eeprom(hw);
815
816 /* Some SPI eeproms use the 8th address bit embedded in
817 * the opcode */
818 if ((eeprom->address_bits == 8) && (offset >= 128))
819 read_opcode |= EEPROM_A8_OPCODE_SPI;
820
821 /* Send the READ command (opcode + addr) */
822 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
823 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
824 eeprom->address_bits);
825
826 /* Read the data. The address of the eeprom internally
827 * increments with each byte (spi) being read, saving on the
828 * overhead of eeprom setup and tear-down. The address
829 * counter will roll over if reading beyond the size of
830 * the eeprom, thus allowing the entire memory to be read
831 * starting from any offset. */
832 for (i = 0; i < words; i++) {
833 word_in = e1000_shift_in_ee_bits(hw, 16);
834 data[i] = (word_in >> 8) | (word_in << 8);
835 }
836 } else if (eeprom->type == e1000_eeprom_microwire) {
837 for (i = 0; i < words; i++) {
838 /* Send the READ command (opcode + addr) */
839 e1000_shift_out_ee_bits(hw,
840 EEPROM_READ_OPCODE_MICROWIRE,
841 eeprom->opcode_bits);
842 e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
843 eeprom->address_bits);
844
845 /* Read the data. For microwire, each word requires
846 * the overhead of eeprom setup and tear-down. */
847 data[i] = e1000_shift_in_ee_bits(hw, 16);
848 e1000_standby_eeprom(hw);
849 }
wdenk682011f2003-06-03 23:54:09 +0000850 }
851
wdenk682011f2003-06-03 23:54:09 +0000852 /* End this read operation */
Roy Zangaa070782009-07-31 13:34:02 +0800853 e1000_release_eeprom(hw);
wdenk682011f2003-06-03 23:54:09 +0000854
Roy Zangaa070782009-07-31 13:34:02 +0800855 return E1000_SUCCESS;
wdenk682011f2003-06-03 23:54:09 +0000856}
857
wdenk682011f2003-06-03 23:54:09 +0000858/******************************************************************************
859 * Verifies that the EEPROM has a valid checksum
wdenk8bde7f72003-06-27 21:31:46 +0000860 *
wdenk682011f2003-06-03 23:54:09 +0000861 * hw - Struct containing variables accessed by shared code
862 *
863 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
864 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
865 * valid.
866 *****************************************************************************/
Kyle Moffett114d7fc2011-10-18 11:05:27 +0000867static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
wdenk682011f2003-06-03 23:54:09 +0000868{
Kyle Moffett114d7fc2011-10-18 11:05:27 +0000869 uint16_t i, checksum, checksum_reg, *buf;
wdenk682011f2003-06-03 23:54:09 +0000870
871 DEBUGFUNC();
872
Kyle Moffett114d7fc2011-10-18 11:05:27 +0000873 /* Allocate a temporary buffer */
874 buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
875 if (!buf) {
876 E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n");
wdenk682011f2003-06-03 23:54:09 +0000877 return -E1000_ERR_EEPROM;
878 }
Kyle Moffett114d7fc2011-10-18 11:05:27 +0000879
880 /* Read the EEPROM */
881 if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
882 E1000_ERR(hw->nic, "Unable to read EEPROM!\n");
883 return -E1000_ERR_EEPROM;
884 }
885
886 /* Compute the checksum */
Wolfgang Denk7a341062011-10-28 07:37:04 +0200887 checksum = 0;
Kyle Moffett114d7fc2011-10-18 11:05:27 +0000888 for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
889 checksum += buf[i];
890 checksum = ((uint16_t)EEPROM_SUM) - checksum;
891 checksum_reg = buf[i];
892
893 /* Verify it! */
894 if (checksum == checksum_reg)
895 return 0;
896
897 /* Hrm, verification failed, print an error */
898 E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n");
899 E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n",
900 checksum_reg, checksum);
901
902 return -E1000_ERR_EEPROM;
wdenk682011f2003-06-03 23:54:09 +0000903}
Roy Zangecbd2072009-08-11 03:48:05 +0800904
905/*****************************************************************************
906 * Set PHY to class A mode
907 * Assumes the following operations will follow to enable the new class mode.
908 * 1. Do a PHY soft reset
909 * 2. Restart auto-negotiation or force link.
910 *
911 * hw - Struct containing variables accessed by shared code
912 ****************************************************************************/
913static int32_t
914e1000_set_phy_mode(struct e1000_hw *hw)
915{
916 int32_t ret_val;
917 uint16_t eeprom_data;
918
919 DEBUGFUNC();
920
921 if ((hw->mac_type == e1000_82545_rev_3) &&
922 (hw->media_type == e1000_media_type_copper)) {
923 ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
924 1, &eeprom_data);
925 if (ret_val)
926 return ret_val;
927
928 if ((eeprom_data != EEPROM_RESERVED_WORD) &&
929 (eeprom_data & EEPROM_PHY_CLASS_A)) {
930 ret_val = e1000_write_phy_reg(hw,
931 M88E1000_PHY_PAGE_SELECT, 0x000B);
932 if (ret_val)
933 return ret_val;
934 ret_val = e1000_write_phy_reg(hw,
935 M88E1000_PHY_GEN_CONTROL, 0x8104);
936 if (ret_val)
937 return ret_val;
938
939 hw->phy_reset_disable = FALSE;
940 }
941 }
942
943 return E1000_SUCCESS;
944}
Wolfgang Denk7521af12005-10-09 01:04:33 +0200945#endif /* #ifndef CONFIG_AP1000 */
wdenk682011f2003-06-03 23:54:09 +0000946
Roy Zangaa070782009-07-31 13:34:02 +0800947/***************************************************************************
948 *
949 * Obtaining software semaphore bit (SMBI) before resetting PHY.
950 *
951 * hw: Struct containing variables accessed by shared code
952 *
953 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
954 * E1000_SUCCESS at any other case.
955 *
956 ***************************************************************************/
957static int32_t
958e1000_get_software_semaphore(struct e1000_hw *hw)
959{
960 int32_t timeout = hw->eeprom.word_size + 1;
961 uint32_t swsm;
962
963 DEBUGFUNC();
964
965 if (hw->mac_type != e1000_80003es2lan)
966 return E1000_SUCCESS;
967
968 while (timeout) {
969 swsm = E1000_READ_REG(hw, SWSM);
970 /* If SMBI bit cleared, it is now set and we hold
971 * the semaphore */
972 if (!(swsm & E1000_SWSM_SMBI))
973 break;
974 mdelay(1);
975 timeout--;
976 }
977
978 if (!timeout) {
979 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
980 return -E1000_ERR_RESET;
981 }
982
983 return E1000_SUCCESS;
984}
985
986/***************************************************************************
987 * This function clears HW semaphore bits.
988 *
989 * hw: Struct containing variables accessed by shared code
990 *
991 * returns: - None.
992 *
993 ***************************************************************************/
994static void
995e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
996{
997 uint32_t swsm;
998
999 DEBUGFUNC();
1000
1001 if (!hw->eeprom_semaphore_present)
1002 return;
1003
1004 swsm = E1000_READ_REG(hw, SWSM);
1005 if (hw->mac_type == e1000_80003es2lan) {
1006 /* Release both semaphores. */
1007 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1008 } else
1009 swsm &= ~(E1000_SWSM_SWESMBI);
1010 E1000_WRITE_REG(hw, SWSM, swsm);
1011}
1012
1013/***************************************************************************
1014 *
1015 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
1016 * adapter or Eeprom access.
1017 *
1018 * hw: Struct containing variables accessed by shared code
1019 *
1020 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1021 * E1000_SUCCESS at any other case.
1022 *
1023 ***************************************************************************/
1024static int32_t
1025e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
1026{
1027 int32_t timeout;
1028 uint32_t swsm;
1029
1030 DEBUGFUNC();
1031
1032 if (!hw->eeprom_semaphore_present)
1033 return E1000_SUCCESS;
1034
1035 if (hw->mac_type == e1000_80003es2lan) {
1036 /* Get the SW semaphore. */
1037 if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
1038 return -E1000_ERR_EEPROM;
1039 }
1040
1041 /* Get the FW semaphore. */
1042 timeout = hw->eeprom.word_size + 1;
1043 while (timeout) {
1044 swsm = E1000_READ_REG(hw, SWSM);
1045 swsm |= E1000_SWSM_SWESMBI;
1046 E1000_WRITE_REG(hw, SWSM, swsm);
1047 /* if we managed to set the bit we got the semaphore. */
1048 swsm = E1000_READ_REG(hw, SWSM);
1049 if (swsm & E1000_SWSM_SWESMBI)
1050 break;
1051
1052 udelay(50);
1053 timeout--;
1054 }
1055
1056 if (!timeout) {
1057 /* Release semaphores */
1058 e1000_put_hw_eeprom_semaphore(hw);
1059 DEBUGOUT("Driver can't access the Eeprom - "
1060 "SWESMBI bit is set.\n");
1061 return -E1000_ERR_EEPROM;
1062 }
1063
1064 return E1000_SUCCESS;
1065}
1066
1067static int32_t
1068e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
1069{
1070 uint32_t swfw_sync = 0;
1071 uint32_t swmask = mask;
1072 uint32_t fwmask = mask << 16;
1073 int32_t timeout = 200;
1074
1075 DEBUGFUNC();
1076 while (timeout) {
1077 if (e1000_get_hw_eeprom_semaphore(hw))
1078 return -E1000_ERR_SWFW_SYNC;
1079
1080 swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
1081 if (!(swfw_sync & (fwmask | swmask)))
1082 break;
1083
1084 /* firmware currently using resource (fwmask) */
1085 /* or other software thread currently using resource (swmask) */
1086 e1000_put_hw_eeprom_semaphore(hw);
1087 mdelay(5);
1088 timeout--;
1089 }
1090
1091 if (!timeout) {
1092 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1093 return -E1000_ERR_SWFW_SYNC;
1094 }
1095
1096 swfw_sync |= swmask;
1097 E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
1098
1099 e1000_put_hw_eeprom_semaphore(hw);
1100 return E1000_SUCCESS;
1101}
1102
Kyle Moffett987b43a2010-09-13 05:52:22 +00001103static boolean_t e1000_is_second_port(struct e1000_hw *hw)
1104{
1105 switch (hw->mac_type) {
1106 case e1000_80003es2lan:
1107 case e1000_82546:
1108 case e1000_82571:
1109 if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
1110 return TRUE;
1111 /* Fallthrough */
1112 default:
1113 return FALSE;
1114 }
1115}
1116
wdenk682011f2003-06-03 23:54:09 +00001117/******************************************************************************
1118 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1119 * second function of dual function devices
1120 *
1121 * nic - Struct containing variables accessed by shared code
1122 *****************************************************************************/
1123static int
1124e1000_read_mac_addr(struct eth_device *nic)
1125{
Wolfgang Denk7521af12005-10-09 01:04:33 +02001126#ifndef CONFIG_AP1000
wdenk682011f2003-06-03 23:54:09 +00001127 struct e1000_hw *hw = nic->priv;
1128 uint16_t offset;
1129 uint16_t eeprom_data;
1130 int i;
1131
1132 DEBUGFUNC();
1133
1134 for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
1135 offset = i >> 1;
Roy Zangaa070782009-07-31 13:34:02 +08001136 if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
wdenk682011f2003-06-03 23:54:09 +00001137 DEBUGOUT("EEPROM Read Error\n");
1138 return -E1000_ERR_EEPROM;
1139 }
1140 nic->enetaddr[i] = eeprom_data & 0xff;
1141 nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
1142 }
Kyle Moffett987b43a2010-09-13 05:52:22 +00001143
1144 /* Invert the last bit if this is the second device */
1145 if (e1000_is_second_port(hw))
1146 nic->enetaddr[5] ^= 1;
1147
Andre Schwarzac3315c2008-03-06 16:45:44 +01001148#ifdef CONFIG_E1000_FALLBACK_MAC
Anatolij Gustschin40867a22011-12-20 07:36:39 +00001149 if (!is_valid_ether_addr(nic->enetaddr)) {
Stefan Roesef2302d42008-08-06 14:05:38 +02001150 unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC;
1151
1152 memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
1153 }
Andre Schwarzac3315c2008-03-06 16:45:44 +01001154#endif
Wolfgang Denk7521af12005-10-09 01:04:33 +02001155#else
1156 /*
1157 * The AP1000's e1000 has no eeprom; the MAC address is stored in the
1158 * environment variables. Currently this does not support the addition
1159 * of a PMC e1000 card, which is certainly a possibility, so this should
1160 * be updated to properly use the env variable only for the onboard e1000
1161 */
1162
1163 int ii;
1164 char *s, *e;
1165
1166 DEBUGFUNC();
1167
1168 s = getenv ("ethaddr");
Stefan Roesef2302d42008-08-06 14:05:38 +02001169 if (s == NULL) {
Wolfgang Denk7521af12005-10-09 01:04:33 +02001170 return -E1000_ERR_EEPROM;
Stefan Roesef2302d42008-08-06 14:05:38 +02001171 } else {
Wolfgang Denk7521af12005-10-09 01:04:33 +02001172 for(ii = 0; ii < 6; ii++) {
1173 nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
1174 if (s){
1175 s = (*e) ? e + 1 : e;
1176 }
1177 }
1178 }
1179#endif
wdenk682011f2003-06-03 23:54:09 +00001180 return 0;
1181}
1182
1183/******************************************************************************
1184 * Initializes receive address filters.
1185 *
wdenk8bde7f72003-06-27 21:31:46 +00001186 * hw - Struct containing variables accessed by shared code
wdenk682011f2003-06-03 23:54:09 +00001187 *
1188 * Places the MAC address in receive address register 0 and clears the rest
1189 * of the receive addresss registers. Clears the multicast table. Assumes
1190 * the receiver is in reset when the routine is called.
1191 *****************************************************************************/
1192static void
1193e1000_init_rx_addrs(struct eth_device *nic)
1194{
1195 struct e1000_hw *hw = nic->priv;
1196 uint32_t i;
1197 uint32_t addr_low;
1198 uint32_t addr_high;
1199
1200 DEBUGFUNC();
1201
1202 /* Setup the receive address. */
1203 DEBUGOUT("Programming MAC Address into RAR[0]\n");
1204 addr_low = (nic->enetaddr[0] |
1205 (nic->enetaddr[1] << 8) |
1206 (nic->enetaddr[2] << 16) | (nic->enetaddr[3] << 24));
1207
1208 addr_high = (nic->enetaddr[4] | (nic->enetaddr[5] << 8) | E1000_RAH_AV);
1209
1210 E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
1211 E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
1212
1213 /* Zero out the other 15 receive addresses. */
1214 DEBUGOUT("Clearing RAR[1-15]\n");
1215 for (i = 1; i < E1000_RAR_ENTRIES; i++) {
1216 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
1217 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
1218 }
1219}
1220
1221/******************************************************************************
1222 * Clears the VLAN filer table
1223 *
1224 * hw - Struct containing variables accessed by shared code
1225 *****************************************************************************/
1226static void
1227e1000_clear_vfta(struct e1000_hw *hw)
1228{
1229 uint32_t offset;
1230
1231 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
1232 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
1233}
1234
1235/******************************************************************************
1236 * Set the mac type member in the hw struct.
wdenk8bde7f72003-06-27 21:31:46 +00001237 *
wdenk682011f2003-06-03 23:54:09 +00001238 * hw - Struct containing variables accessed by shared code
1239 *****************************************************************************/
Roy Zangaa070782009-07-31 13:34:02 +08001240int32_t
wdenk682011f2003-06-03 23:54:09 +00001241e1000_set_mac_type(struct e1000_hw *hw)
1242{
1243 DEBUGFUNC();
1244
1245 switch (hw->device_id) {
1246 case E1000_DEV_ID_82542:
1247 switch (hw->revision_id) {
1248 case E1000_82542_2_0_REV_ID:
1249 hw->mac_type = e1000_82542_rev2_0;
1250 break;
1251 case E1000_82542_2_1_REV_ID:
1252 hw->mac_type = e1000_82542_rev2_1;
1253 break;
1254 default:
1255 /* Invalid 82542 revision ID */
1256 return -E1000_ERR_MAC_TYPE;
1257 }
1258 break;
1259 case E1000_DEV_ID_82543GC_FIBER:
1260 case E1000_DEV_ID_82543GC_COPPER:
1261 hw->mac_type = e1000_82543;
1262 break;
1263 case E1000_DEV_ID_82544EI_COPPER:
1264 case E1000_DEV_ID_82544EI_FIBER:
1265 case E1000_DEV_ID_82544GC_COPPER:
1266 case E1000_DEV_ID_82544GC_LOM:
1267 hw->mac_type = e1000_82544;
1268 break;
1269 case E1000_DEV_ID_82540EM:
1270 case E1000_DEV_ID_82540EM_LOM:
Roy Zangaa070782009-07-31 13:34:02 +08001271 case E1000_DEV_ID_82540EP:
1272 case E1000_DEV_ID_82540EP_LOM:
1273 case E1000_DEV_ID_82540EP_LP:
wdenk682011f2003-06-03 23:54:09 +00001274 hw->mac_type = e1000_82540;
1275 break;
1276 case E1000_DEV_ID_82545EM_COPPER:
1277 case E1000_DEV_ID_82545EM_FIBER:
1278 hw->mac_type = e1000_82545;
1279 break;
Roy Zangaa070782009-07-31 13:34:02 +08001280 case E1000_DEV_ID_82545GM_COPPER:
1281 case E1000_DEV_ID_82545GM_FIBER:
1282 case E1000_DEV_ID_82545GM_SERDES:
1283 hw->mac_type = e1000_82545_rev_3;
1284 break;
wdenk682011f2003-06-03 23:54:09 +00001285 case E1000_DEV_ID_82546EB_COPPER:
1286 case E1000_DEV_ID_82546EB_FIBER:
Roy Zangaa070782009-07-31 13:34:02 +08001287 case E1000_DEV_ID_82546EB_QUAD_COPPER:
wdenk682011f2003-06-03 23:54:09 +00001288 hw->mac_type = e1000_82546;
1289 break;
Roy Zangaa070782009-07-31 13:34:02 +08001290 case E1000_DEV_ID_82546GB_COPPER:
1291 case E1000_DEV_ID_82546GB_FIBER:
1292 case E1000_DEV_ID_82546GB_SERDES:
1293 case E1000_DEV_ID_82546GB_PCIE:
1294 case E1000_DEV_ID_82546GB_QUAD_COPPER:
1295 case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
1296 hw->mac_type = e1000_82546_rev_3;
1297 break;
1298 case E1000_DEV_ID_82541EI:
1299 case E1000_DEV_ID_82541EI_MOBILE:
1300 case E1000_DEV_ID_82541ER_LOM:
1301 hw->mac_type = e1000_82541;
1302 break;
Andre Schwarzac3315c2008-03-06 16:45:44 +01001303 case E1000_DEV_ID_82541ER:
Roy Zangaa070782009-07-31 13:34:02 +08001304 case E1000_DEV_ID_82541GI:
Wolfgang Grandeggeraa3b8bf2008-05-28 19:55:19 +02001305 case E1000_DEV_ID_82541GI_LF:
Roy Zangaa070782009-07-31 13:34:02 +08001306 case E1000_DEV_ID_82541GI_MOBILE:
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07001307 hw->mac_type = e1000_82541_rev_2;
1308 break;
Roy Zangaa070782009-07-31 13:34:02 +08001309 case E1000_DEV_ID_82547EI:
1310 case E1000_DEV_ID_82547EI_MOBILE:
1311 hw->mac_type = e1000_82547;
1312 break;
1313 case E1000_DEV_ID_82547GI:
1314 hw->mac_type = e1000_82547_rev_2;
1315 break;
1316 case E1000_DEV_ID_82571EB_COPPER:
1317 case E1000_DEV_ID_82571EB_FIBER:
1318 case E1000_DEV_ID_82571EB_SERDES:
1319 case E1000_DEV_ID_82571EB_SERDES_DUAL:
1320 case E1000_DEV_ID_82571EB_SERDES_QUAD:
1321 case E1000_DEV_ID_82571EB_QUAD_COPPER:
1322 case E1000_DEV_ID_82571PT_QUAD_COPPER:
1323 case E1000_DEV_ID_82571EB_QUAD_FIBER:
1324 case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
1325 hw->mac_type = e1000_82571;
1326 break;
1327 case E1000_DEV_ID_82572EI_COPPER:
1328 case E1000_DEV_ID_82572EI_FIBER:
1329 case E1000_DEV_ID_82572EI_SERDES:
1330 case E1000_DEV_ID_82572EI:
1331 hw->mac_type = e1000_82572;
1332 break;
1333 case E1000_DEV_ID_82573E:
1334 case E1000_DEV_ID_82573E_IAMT:
1335 case E1000_DEV_ID_82573L:
1336 hw->mac_type = e1000_82573;
1337 break;
Roy Zang2c2668f2011-01-21 11:29:38 +08001338 case E1000_DEV_ID_82574L:
1339 hw->mac_type = e1000_82574;
1340 break;
Roy Zangaa070782009-07-31 13:34:02 +08001341 case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
1342 case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
1343 case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
1344 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
1345 hw->mac_type = e1000_80003es2lan;
1346 break;
1347 case E1000_DEV_ID_ICH8_IGP_M_AMT:
1348 case E1000_DEV_ID_ICH8_IGP_AMT:
1349 case E1000_DEV_ID_ICH8_IGP_C:
1350 case E1000_DEV_ID_ICH8_IFE:
1351 case E1000_DEV_ID_ICH8_IFE_GT:
1352 case E1000_DEV_ID_ICH8_IFE_G:
1353 case E1000_DEV_ID_ICH8_IGP_M:
1354 hw->mac_type = e1000_ich8lan;
1355 break;
wdenk682011f2003-06-03 23:54:09 +00001356 default:
1357 /* Should never have loaded on this device */
1358 return -E1000_ERR_MAC_TYPE;
1359 }
1360 return E1000_SUCCESS;
1361}
1362
1363/******************************************************************************
1364 * Reset the transmit and receive units; mask and clear all interrupts.
1365 *
1366 * hw - Struct containing variables accessed by shared code
1367 *****************************************************************************/
1368void
1369e1000_reset_hw(struct e1000_hw *hw)
1370{
1371 uint32_t ctrl;
1372 uint32_t ctrl_ext;
wdenk682011f2003-06-03 23:54:09 +00001373 uint32_t manc;
Roy Zang9ea005f2009-08-22 03:49:52 +08001374 uint32_t pba = 0;
wdenk682011f2003-06-03 23:54:09 +00001375
1376 DEBUGFUNC();
1377
Roy Zang9ea005f2009-08-22 03:49:52 +08001378 /* get the correct pba value for both PCI and PCIe*/
1379 if (hw->mac_type < e1000_82571)
1380 pba = E1000_DEFAULT_PCI_PBA;
1381 else
1382 pba = E1000_DEFAULT_PCIE_PBA;
1383
wdenk682011f2003-06-03 23:54:09 +00001384 /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
1385 if (hw->mac_type == e1000_82542_rev2_0) {
1386 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1387 pci_write_config_word(hw->pdev, PCI_COMMAND,
Roy Zangaa070782009-07-31 13:34:02 +08001388 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
wdenk682011f2003-06-03 23:54:09 +00001389 }
1390
1391 /* Clear interrupt mask to stop board from generating interrupts */
1392 DEBUGOUT("Masking off all interrupts\n");
1393 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1394
1395 /* Disable the Transmit and Receive units. Then delay to allow
1396 * any pending transactions to complete before we hit the MAC with
1397 * the global reset.
1398 */
1399 E1000_WRITE_REG(hw, RCTL, 0);
1400 E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
1401 E1000_WRITE_FLUSH(hw);
1402
1403 /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
1404 hw->tbi_compatibility_on = FALSE;
1405
1406 /* Delay to allow any outstanding PCI transactions to complete before
1407 * resetting the device
1408 */
1409 mdelay(10);
1410
1411 /* Issue a global reset to the MAC. This will reset the chip's
1412 * transmit, receive, DMA, and link units. It will not effect
1413 * the current PCI configuration. The global reset bit is self-
1414 * clearing, and should clear within a microsecond.
1415 */
1416 DEBUGOUT("Issuing a global reset to MAC\n");
1417 ctrl = E1000_READ_REG(hw, CTRL);
1418
Roy Zangaa070782009-07-31 13:34:02 +08001419 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
wdenk682011f2003-06-03 23:54:09 +00001420
1421 /* Force a reload from the EEPROM if necessary */
1422 if (hw->mac_type < e1000_82540) {
1423 /* Wait for reset to complete */
1424 udelay(10);
1425 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1426 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1427 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1428 E1000_WRITE_FLUSH(hw);
1429 /* Wait for EEPROM reload */
1430 mdelay(2);
1431 } else {
1432 /* Wait for EEPROM reload (it happens automatically) */
1433 mdelay(4);
1434 /* Dissable HW ARPs on ASF enabled adapters */
1435 manc = E1000_READ_REG(hw, MANC);
1436 manc &= ~(E1000_MANC_ARP_EN);
1437 E1000_WRITE_REG(hw, MANC, manc);
1438 }
1439
1440 /* Clear interrupt mask to stop board from generating interrupts */
1441 DEBUGOUT("Masking off all interrupts\n");
1442 E1000_WRITE_REG(hw, IMC, 0xffffffff);
1443
1444 /* Clear any pending interrupt events. */
Zang Roy-R6191156b13b12011-11-06 22:22:36 +00001445 E1000_READ_REG(hw, ICR);
wdenk682011f2003-06-03 23:54:09 +00001446
1447 /* If MWI was previously enabled, reenable it. */
1448 if (hw->mac_type == e1000_82542_rev2_0) {
1449 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1450 }
Roy Zang9ea005f2009-08-22 03:49:52 +08001451 E1000_WRITE_REG(hw, PBA, pba);
Roy Zangaa070782009-07-31 13:34:02 +08001452}
1453
1454/******************************************************************************
1455 *
1456 * Initialize a number of hardware-dependent bits
1457 *
1458 * hw: Struct containing variables accessed by shared code
1459 *
1460 * This function contains hardware limitation workarounds for PCI-E adapters
1461 *
1462 *****************************************************************************/
1463static void
1464e1000_initialize_hardware_bits(struct e1000_hw *hw)
1465{
1466 if ((hw->mac_type >= e1000_82571) &&
1467 (!hw->initialize_hw_bits_disable)) {
1468 /* Settings common to all PCI-express silicon */
1469 uint32_t reg_ctrl, reg_ctrl_ext;
1470 uint32_t reg_tarc0, reg_tarc1;
1471 uint32_t reg_tctl;
1472 uint32_t reg_txdctl, reg_txdctl1;
1473
1474 /* link autonegotiation/sync workarounds */
1475 reg_tarc0 = E1000_READ_REG(hw, TARC0);
1476 reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
1477
1478 /* Enable not-done TX descriptor counting */
1479 reg_txdctl = E1000_READ_REG(hw, TXDCTL);
1480 reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
1481 E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
1482
1483 reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
1484 reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
1485 E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
1486
1487 switch (hw->mac_type) {
1488 case e1000_82571:
1489 case e1000_82572:
1490 /* Clear PHY TX compatible mode bits */
1491 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1492 reg_tarc1 &= ~((1 << 30)|(1 << 29));
1493
1494 /* link autonegotiation/sync workarounds */
1495 reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
1496
1497 /* TX ring control fixes */
1498 reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
1499
1500 /* Multiple read bit is reversed polarity */
1501 reg_tctl = E1000_READ_REG(hw, TCTL);
1502 if (reg_tctl & E1000_TCTL_MULR)
1503 reg_tarc1 &= ~(1 << 28);
1504 else
1505 reg_tarc1 |= (1 << 28);
1506
1507 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1508 break;
1509 case e1000_82573:
Roy Zang2c2668f2011-01-21 11:29:38 +08001510 case e1000_82574:
Roy Zangaa070782009-07-31 13:34:02 +08001511 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1512 reg_ctrl_ext &= ~(1 << 23);
1513 reg_ctrl_ext |= (1 << 22);
1514
1515 /* TX byte count fix */
1516 reg_ctrl = E1000_READ_REG(hw, CTRL);
1517 reg_ctrl &= ~(1 << 29);
1518
1519 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1520 E1000_WRITE_REG(hw, CTRL, reg_ctrl);
1521 break;
1522 case e1000_80003es2lan:
1523 /* improve small packet performace for fiber/serdes */
1524 if ((hw->media_type == e1000_media_type_fiber)
1525 || (hw->media_type ==
1526 e1000_media_type_internal_serdes)) {
1527 reg_tarc0 &= ~(1 << 20);
1528 }
1529
1530 /* Multiple read bit is reversed polarity */
1531 reg_tctl = E1000_READ_REG(hw, TCTL);
1532 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1533 if (reg_tctl & E1000_TCTL_MULR)
1534 reg_tarc1 &= ~(1 << 28);
1535 else
1536 reg_tarc1 |= (1 << 28);
1537
1538 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1539 break;
1540 case e1000_ich8lan:
1541 /* Reduce concurrent DMA requests to 3 from 4 */
1542 if ((hw->revision_id < 3) ||
1543 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1544 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
1545 reg_tarc0 |= ((1 << 29)|(1 << 28));
1546
1547 reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1548 reg_ctrl_ext |= (1 << 22);
1549 E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
1550
1551 /* workaround TX hang with TSO=on */
1552 reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
1553
1554 /* Multiple read bit is reversed polarity */
1555 reg_tctl = E1000_READ_REG(hw, TCTL);
1556 reg_tarc1 = E1000_READ_REG(hw, TARC1);
1557 if (reg_tctl & E1000_TCTL_MULR)
1558 reg_tarc1 &= ~(1 << 28);
1559 else
1560 reg_tarc1 |= (1 << 28);
1561
1562 /* workaround TX hang with TSO=on */
1563 reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
1564
1565 E1000_WRITE_REG(hw, TARC1, reg_tarc1);
1566 break;
1567 default:
1568 break;
1569 }
1570
1571 E1000_WRITE_REG(hw, TARC0, reg_tarc0);
1572 }
wdenk682011f2003-06-03 23:54:09 +00001573}
1574
1575/******************************************************************************
1576 * Performs basic configuration of the adapter.
1577 *
1578 * hw - Struct containing variables accessed by shared code
wdenk8bde7f72003-06-27 21:31:46 +00001579 *
1580 * Assumes that the controller has previously been reset and is in a
wdenk682011f2003-06-03 23:54:09 +00001581 * post-reset uninitialized state. Initializes the receive address registers,
1582 * multicast table, and VLAN filter table. Calls routines to setup link
1583 * configuration and flow control settings. Clears all on-chip counters. Leaves
1584 * the transmit and receive units disabled and uninitialized.
1585 *****************************************************************************/
1586static int
1587e1000_init_hw(struct eth_device *nic)
1588{
1589 struct e1000_hw *hw = nic->priv;
Roy Zangaa070782009-07-31 13:34:02 +08001590 uint32_t ctrl;
wdenk682011f2003-06-03 23:54:09 +00001591 uint32_t i;
1592 int32_t ret_val;
1593 uint16_t pcix_cmd_word;
1594 uint16_t pcix_stat_hi_word;
1595 uint16_t cmd_mmrbc;
1596 uint16_t stat_mmrbc;
Roy Zangaa070782009-07-31 13:34:02 +08001597 uint32_t mta_size;
1598 uint32_t reg_data;
1599 uint32_t ctrl_ext;
wdenk682011f2003-06-03 23:54:09 +00001600 DEBUGFUNC();
Roy Zangaa070782009-07-31 13:34:02 +08001601 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
1602 if ((hw->mac_type == e1000_ich8lan) &&
1603 ((hw->revision_id < 3) ||
1604 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
1605 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
1606 reg_data = E1000_READ_REG(hw, STATUS);
1607 reg_data &= ~0x80000000;
1608 E1000_WRITE_REG(hw, STATUS, reg_data);
wdenk682011f2003-06-03 23:54:09 +00001609 }
Roy Zangaa070782009-07-31 13:34:02 +08001610 /* Do not need initialize Identification LED */
wdenk682011f2003-06-03 23:54:09 +00001611
Roy Zangaa070782009-07-31 13:34:02 +08001612 /* Set the media type and TBI compatibility */
1613 e1000_set_media_type(hw);
1614
1615 /* Must be called after e1000_set_media_type
1616 * because media_type is used */
1617 e1000_initialize_hardware_bits(hw);
wdenk682011f2003-06-03 23:54:09 +00001618
1619 /* Disabling VLAN filtering. */
1620 DEBUGOUT("Initializing the IEEE VLAN\n");
Roy Zangaa070782009-07-31 13:34:02 +08001621 /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
1622 if (hw->mac_type != e1000_ich8lan) {
1623 if (hw->mac_type < e1000_82545_rev_3)
1624 E1000_WRITE_REG(hw, VET, 0);
1625 e1000_clear_vfta(hw);
1626 }
wdenk682011f2003-06-03 23:54:09 +00001627
1628 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1629 if (hw->mac_type == e1000_82542_rev2_0) {
1630 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1631 pci_write_config_word(hw->pdev, PCI_COMMAND,
1632 hw->
1633 pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
1634 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1635 E1000_WRITE_FLUSH(hw);
1636 mdelay(5);
1637 }
1638
1639 /* Setup the receive address. This involves initializing all of the Receive
1640 * Address Registers (RARs 0 - 15).
1641 */
1642 e1000_init_rx_addrs(nic);
1643
1644 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1645 if (hw->mac_type == e1000_82542_rev2_0) {
1646 E1000_WRITE_REG(hw, RCTL, 0);
1647 E1000_WRITE_FLUSH(hw);
1648 mdelay(1);
1649 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
1650 }
1651
1652 /* Zero out the Multicast HASH table */
1653 DEBUGOUT("Zeroing the MTA\n");
Roy Zangaa070782009-07-31 13:34:02 +08001654 mta_size = E1000_MC_TBL_SIZE;
1655 if (hw->mac_type == e1000_ich8lan)
1656 mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
1657 for (i = 0; i < mta_size; i++) {
wdenk682011f2003-06-03 23:54:09 +00001658 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
Roy Zangaa070782009-07-31 13:34:02 +08001659 /* use write flush to prevent Memory Write Block (MWB) from
1660 * occuring when accessing our register space */
1661 E1000_WRITE_FLUSH(hw);
1662 }
wdenk682011f2003-06-03 23:54:09 +00001663#if 0
1664 /* Set the PCI priority bit correctly in the CTRL register. This
1665 * determines if the adapter gives priority to receives, or if it
Roy Zangaa070782009-07-31 13:34:02 +08001666 * gives equal priority to transmits and receives. Valid only on
1667 * 82542 and 82543 silicon.
wdenk682011f2003-06-03 23:54:09 +00001668 */
Roy Zangaa070782009-07-31 13:34:02 +08001669 if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
wdenk682011f2003-06-03 23:54:09 +00001670 ctrl = E1000_READ_REG(hw, CTRL);
1671 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1672 }
1673#endif
Roy Zangaa070782009-07-31 13:34:02 +08001674 switch (hw->mac_type) {
1675 case e1000_82545_rev_3:
1676 case e1000_82546_rev_3:
1677 break;
1678 default:
wdenk682011f2003-06-03 23:54:09 +00001679 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
Roy Zangaa070782009-07-31 13:34:02 +08001680 if (hw->bus_type == e1000_bus_type_pcix) {
wdenk682011f2003-06-03 23:54:09 +00001681 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1682 &pcix_cmd_word);
1683 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
1684 &pcix_stat_hi_word);
1685 cmd_mmrbc =
1686 (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1687 PCIX_COMMAND_MMRBC_SHIFT;
1688 stat_mmrbc =
1689 (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1690 PCIX_STATUS_HI_MMRBC_SHIFT;
1691 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1692 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1693 if (cmd_mmrbc > stat_mmrbc) {
1694 pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1695 pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1696 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
1697 pcix_cmd_word);
1698 }
1699 }
Roy Zangaa070782009-07-31 13:34:02 +08001700 break;
1701 }
1702
1703 /* More time needed for PHY to initialize */
1704 if (hw->mac_type == e1000_ich8lan)
1705 mdelay(15);
wdenk682011f2003-06-03 23:54:09 +00001706
1707 /* Call a subroutine to configure the link and setup flow control. */
1708 ret_val = e1000_setup_link(nic);
1709
1710 /* Set the transmit descriptor write-back policy */
1711 if (hw->mac_type > e1000_82544) {
1712 ctrl = E1000_READ_REG(hw, TXDCTL);
1713 ctrl =
1714 (ctrl & ~E1000_TXDCTL_WTHRESH) |
1715 E1000_TXDCTL_FULL_TX_DESC_WB;
1716 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1717 }
Roy Zangaa070782009-07-31 13:34:02 +08001718
1719 switch (hw->mac_type) {
1720 default:
1721 break;
1722 case e1000_80003es2lan:
1723 /* Enable retransmit on late collisions */
1724 reg_data = E1000_READ_REG(hw, TCTL);
1725 reg_data |= E1000_TCTL_RTLC;
1726 E1000_WRITE_REG(hw, TCTL, reg_data);
1727
1728 /* Configure Gigabit Carry Extend Padding */
1729 reg_data = E1000_READ_REG(hw, TCTL_EXT);
1730 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1731 reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1732 E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1733
1734 /* Configure Transmit Inter-Packet Gap */
1735 reg_data = E1000_READ_REG(hw, TIPG);
1736 reg_data &= ~E1000_TIPG_IPGT_MASK;
1737 reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1738 E1000_WRITE_REG(hw, TIPG, reg_data);
1739
1740 reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1741 reg_data &= ~0x00100000;
1742 E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1743 /* Fall through */
1744 case e1000_82571:
1745 case e1000_82572:
1746 case e1000_ich8lan:
1747 ctrl = E1000_READ_REG(hw, TXDCTL1);
1748 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
1749 | E1000_TXDCTL_FULL_TX_DESC_WB;
1750 E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1751 break;
Roy Zang2c2668f2011-01-21 11:29:38 +08001752 case e1000_82573:
1753 case e1000_82574:
1754 reg_data = E1000_READ_REG(hw, GCR);
1755 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1756 E1000_WRITE_REG(hw, GCR, reg_data);
Roy Zangaa070782009-07-31 13:34:02 +08001757 }
1758
wdenk682011f2003-06-03 23:54:09 +00001759#if 0
1760 /* Clear all of the statistics registers (clear on read). It is
1761 * important that we do this after we have tried to establish link
1762 * because the symbol error count will increment wildly if there
1763 * is no link.
1764 */
1765 e1000_clear_hw_cntrs(hw);
Roy Zangaa070782009-07-31 13:34:02 +08001766
1767 /* ICH8 No-snoop bits are opposite polarity.
1768 * Set to snoop by default after reset. */
1769 if (hw->mac_type == e1000_ich8lan)
1770 e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
wdenk682011f2003-06-03 23:54:09 +00001771#endif
1772
Roy Zangaa070782009-07-31 13:34:02 +08001773 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
1774 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1775 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1776 /* Relaxed ordering must be disabled to avoid a parity
1777 * error crash in a PCI slot. */
1778 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1779 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1780 }
1781
wdenk682011f2003-06-03 23:54:09 +00001782 return ret_val;
1783}
1784
1785/******************************************************************************
1786 * Configures flow control and link settings.
wdenk8bde7f72003-06-27 21:31:46 +00001787 *
wdenk682011f2003-06-03 23:54:09 +00001788 * hw - Struct containing variables accessed by shared code
wdenk8bde7f72003-06-27 21:31:46 +00001789 *
wdenk682011f2003-06-03 23:54:09 +00001790 * Determines which flow control settings to use. Calls the apropriate media-
1791 * specific link configuration function. Configures the flow control settings.
1792 * Assuming the adapter has a valid link partner, a valid link should be
wdenk8bde7f72003-06-27 21:31:46 +00001793 * established. Assumes the hardware has previously been reset and the
wdenk682011f2003-06-03 23:54:09 +00001794 * transmitter and receiver are not enabled.
1795 *****************************************************************************/
1796static int
1797e1000_setup_link(struct eth_device *nic)
1798{
1799 struct e1000_hw *hw = nic->priv;
1800 uint32_t ctrl_ext;
1801 int32_t ret_val;
1802 uint16_t eeprom_data;
1803
1804 DEBUGFUNC();
1805
Roy Zangaa070782009-07-31 13:34:02 +08001806 /* In the case of the phy reset being blocked, we already have a link.
1807 * We do not have to set it up again. */
1808 if (e1000_check_phy_reset_block(hw))
1809 return E1000_SUCCESS;
1810
Wolfgang Denk7521af12005-10-09 01:04:33 +02001811#ifndef CONFIG_AP1000
wdenk682011f2003-06-03 23:54:09 +00001812 /* Read and store word 0x0F of the EEPROM. This word contains bits
1813 * that determine the hardware's default PAUSE (flow control) mode,
1814 * a bit that determines whether the HW defaults to enabling or
1815 * disabling auto-negotiation, and the direction of the
1816 * SW defined pins. If there is no SW over-ride of the flow
1817 * control setting, then the variable hw->fc will
1818 * be initialized based on a value in the EEPROM.
1819 */
Roy Zangaa070782009-07-31 13:34:02 +08001820 if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
1821 &eeprom_data) < 0) {
wdenk682011f2003-06-03 23:54:09 +00001822 DEBUGOUT("EEPROM Read Error\n");
1823 return -E1000_ERR_EEPROM;
1824 }
Wolfgang Denk7521af12005-10-09 01:04:33 +02001825#else
1826 /* we have to hardcode the proper value for our hardware. */
1827 /* this value is for the 82540EM pci card used for prototyping, and it works. */
1828 eeprom_data = 0xb220;
1829#endif
wdenk682011f2003-06-03 23:54:09 +00001830
1831 if (hw->fc == e1000_fc_default) {
Roy Zangaa070782009-07-31 13:34:02 +08001832 switch (hw->mac_type) {
1833 case e1000_ich8lan:
1834 case e1000_82573:
Roy Zang2c2668f2011-01-21 11:29:38 +08001835 case e1000_82574:
wdenk682011f2003-06-03 23:54:09 +00001836 hw->fc = e1000_fc_full;
Roy Zangaa070782009-07-31 13:34:02 +08001837 break;
1838 default:
1839#ifndef CONFIG_AP1000
1840 ret_val = e1000_read_eeprom(hw,
1841 EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
1842 if (ret_val) {
1843 DEBUGOUT("EEPROM Read Error\n");
1844 return -E1000_ERR_EEPROM;
1845 }
1846#else
1847 eeprom_data = 0xb220;
1848#endif
1849 if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1850 hw->fc = e1000_fc_none;
1851 else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1852 EEPROM_WORD0F_ASM_DIR)
1853 hw->fc = e1000_fc_tx_pause;
1854 else
1855 hw->fc = e1000_fc_full;
1856 break;
1857 }
wdenk682011f2003-06-03 23:54:09 +00001858 }
1859
1860 /* We want to save off the original Flow Control configuration just
1861 * in case we get disconnected and then reconnected into a different
1862 * hub or switch with different Flow Control capabilities.
1863 */
1864 if (hw->mac_type == e1000_82542_rev2_0)
1865 hw->fc &= (~e1000_fc_tx_pause);
1866
1867 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1868 hw->fc &= (~e1000_fc_rx_pause);
1869
1870 hw->original_fc = hw->fc;
1871
1872 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
1873
1874 /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1875 * polarity value for the SW controlled pins, and setup the
1876 * Extended Device Control reg with that info.
1877 * This is needed because one of the SW controlled pins is used for
1878 * signal detection. So this should be done before e1000_setup_pcs_link()
1879 * or e1000_phy_setup() is called.
1880 */
1881 if (hw->mac_type == e1000_82543) {
1882 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1883 SWDPIO__EXT_SHIFT);
1884 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1885 }
1886
1887 /* Call the necessary subroutine to configure the link. */
1888 ret_val = (hw->media_type == e1000_media_type_fiber) ?
1889 e1000_setup_fiber_link(nic) : e1000_setup_copper_link(nic);
1890 if (ret_val < 0) {
1891 return ret_val;
1892 }
1893
1894 /* Initialize the flow control address, type, and PAUSE timer
1895 * registers to their default values. This is done even if flow
1896 * control is disabled, because it does not hurt anything to
1897 * initialize these registers.
1898 */
Roy Zangaa070782009-07-31 13:34:02 +08001899 DEBUGOUT("Initializing the Flow Control address, type"
1900 "and timer regs\n");
wdenk682011f2003-06-03 23:54:09 +00001901
Roy Zangaa070782009-07-31 13:34:02 +08001902 /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1903 if (hw->mac_type != e1000_ich8lan) {
1904 E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1905 E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1906 E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1907 }
1908
wdenk682011f2003-06-03 23:54:09 +00001909 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1910
1911 /* Set the flow control receive threshold registers. Normally,
1912 * these registers will be set to a default threshold that may be
1913 * adjusted later by the driver's runtime code. However, if the
1914 * ability to transmit pause frames in not enabled, then these
wdenk8bde7f72003-06-27 21:31:46 +00001915 * registers will be set to 0.
wdenk682011f2003-06-03 23:54:09 +00001916 */
1917 if (!(hw->fc & e1000_fc_tx_pause)) {
1918 E1000_WRITE_REG(hw, FCRTL, 0);
1919 E1000_WRITE_REG(hw, FCRTH, 0);
1920 } else {
1921 /* We need to set up the Receive Threshold high and low water marks
1922 * as well as (optionally) enabling the transmission of XON frames.
1923 */
1924 if (hw->fc_send_xon) {
1925 E1000_WRITE_REG(hw, FCRTL,
1926 (hw->fc_low_water | E1000_FCRTL_XONE));
1927 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1928 } else {
1929 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1930 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1931 }
1932 }
1933 return ret_val;
1934}
1935
1936/******************************************************************************
1937 * Sets up link for a fiber based adapter
1938 *
1939 * hw - Struct containing variables accessed by shared code
1940 *
1941 * Manipulates Physical Coding Sublayer functions in order to configure
1942 * link. Assumes the hardware has been previously reset and the transmitter
1943 * and receiver are not enabled.
1944 *****************************************************************************/
1945static int
1946e1000_setup_fiber_link(struct eth_device *nic)
1947{
1948 struct e1000_hw *hw = nic->priv;
1949 uint32_t ctrl;
1950 uint32_t status;
1951 uint32_t txcw = 0;
1952 uint32_t i;
1953 uint32_t signal;
1954 int32_t ret_val;
1955
1956 DEBUGFUNC();
wdenk8bde7f72003-06-27 21:31:46 +00001957 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
1958 * set when the optics detect a signal. On older adapters, it will be
wdenk682011f2003-06-03 23:54:09 +00001959 * cleared when there is a signal
1960 */
1961 ctrl = E1000_READ_REG(hw, CTRL);
1962 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
1963 signal = E1000_CTRL_SWDPIN1;
1964 else
1965 signal = 0;
1966
1967 printf("signal for %s is %x (ctrl %08x)!!!!\n", nic->name, signal,
1968 ctrl);
1969 /* Take the link out of reset */
1970 ctrl &= ~(E1000_CTRL_LRST);
1971
1972 e1000_config_collision_dist(hw);
1973
1974 /* Check for a software override of the flow control settings, and setup
1975 * the device accordingly. If auto-negotiation is enabled, then software
1976 * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1977 * Config Word Register (TXCW) and re-start auto-negotiation. However, if
wdenk8bde7f72003-06-27 21:31:46 +00001978 * auto-negotiation is disabled, then software will have to manually
wdenk682011f2003-06-03 23:54:09 +00001979 * configure the two flow control enable bits in the CTRL register.
1980 *
1981 * The possible values of the "fc" parameter are:
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07001982 * 0: Flow control is completely disabled
1983 * 1: Rx flow control is enabled (we can receive pause frames, but
1984 * not send pause frames).
1985 * 2: Tx flow control is enabled (we can send pause frames but we do
1986 * not support receiving pause frames).
1987 * 3: Both Rx and TX flow control (symmetric) are enabled.
wdenk682011f2003-06-03 23:54:09 +00001988 */
1989 switch (hw->fc) {
1990 case e1000_fc_none:
1991 /* Flow control is completely disabled by a software over-ride. */
1992 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1993 break;
1994 case e1000_fc_rx_pause:
wdenk8bde7f72003-06-27 21:31:46 +00001995 /* RX Flow control is enabled and TX Flow control is disabled by a
1996 * software over-ride. Since there really isn't a way to advertise
wdenk682011f2003-06-03 23:54:09 +00001997 * that we are capable of RX Pause ONLY, we will advertise that we
1998 * support both symmetric and asymmetric RX PAUSE. Later, we will
1999 * disable the adapter's ability to send PAUSE frames.
2000 */
2001 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2002 break;
2003 case e1000_fc_tx_pause:
wdenk8bde7f72003-06-27 21:31:46 +00002004 /* TX Flow control is enabled, and RX Flow control is disabled, by a
wdenk682011f2003-06-03 23:54:09 +00002005 * software over-ride.
2006 */
2007 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
2008 break;
2009 case e1000_fc_full:
2010 /* Flow control (both RX and TX) is enabled by a software over-ride. */
2011 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
2012 break;
2013 default:
2014 DEBUGOUT("Flow control param set incorrectly\n");
2015 return -E1000_ERR_CONFIG;
2016 break;
2017 }
2018
2019 /* Since auto-negotiation is enabled, take the link out of reset (the link
2020 * will be in reset, because we previously reset the chip). This will
2021 * restart auto-negotiation. If auto-neogtiation is successful then the
2022 * link-up status bit will be set and the flow control enable bits (RFCE
2023 * and TFCE) will be set according to their negotiated value.
2024 */
2025 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
2026
2027 E1000_WRITE_REG(hw, TXCW, txcw);
2028 E1000_WRITE_REG(hw, CTRL, ctrl);
2029 E1000_WRITE_FLUSH(hw);
2030
2031 hw->txcw = txcw;
2032 mdelay(1);
2033
2034 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
wdenk8bde7f72003-06-27 21:31:46 +00002035 * indication in the Device Status Register. Time-out if a link isn't
2036 * seen in 500 milliseconds seconds (Auto-negotiation should complete in
wdenk682011f2003-06-03 23:54:09 +00002037 * less than 500 milliseconds even if the other end is doing it in SW).
2038 */
2039 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
2040 DEBUGOUT("Looking for Link\n");
2041 for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
2042 mdelay(10);
2043 status = E1000_READ_REG(hw, STATUS);
2044 if (status & E1000_STATUS_LU)
2045 break;
2046 }
2047 if (i == (LINK_UP_TIMEOUT / 10)) {
wdenk8bde7f72003-06-27 21:31:46 +00002048 /* AutoNeg failed to achieve a link, so we'll call
wdenk682011f2003-06-03 23:54:09 +00002049 * e1000_check_for_link. This routine will force the link up if we
2050 * detect a signal. This will allow us to communicate with
2051 * non-autonegotiating link partners.
2052 */
2053 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
2054 hw->autoneg_failed = 1;
2055 ret_val = e1000_check_for_link(nic);
2056 if (ret_val < 0) {
2057 DEBUGOUT("Error while checking for link\n");
2058 return ret_val;
2059 }
2060 hw->autoneg_failed = 0;
2061 } else {
2062 hw->autoneg_failed = 0;
2063 DEBUGOUT("Valid Link Found\n");
2064 }
2065 } else {
2066 DEBUGOUT("No Signal Detected\n");
2067 return -E1000_ERR_NOLINK;
2068 }
2069 return 0;
2070}
2071
2072/******************************************************************************
Roy Zangaa070782009-07-31 13:34:02 +08002073* Make sure we have a valid PHY and change PHY mode before link setup.
wdenk682011f2003-06-03 23:54:09 +00002074*
2075* hw - Struct containing variables accessed by shared code
2076******************************************************************************/
Roy Zangaa070782009-07-31 13:34:02 +08002077static int32_t
2078e1000_copper_link_preconfig(struct e1000_hw *hw)
wdenk682011f2003-06-03 23:54:09 +00002079{
wdenk682011f2003-06-03 23:54:09 +00002080 uint32_t ctrl;
2081 int32_t ret_val;
wdenk682011f2003-06-03 23:54:09 +00002082 uint16_t phy_data;
2083
2084 DEBUGFUNC();
2085
2086 ctrl = E1000_READ_REG(hw, CTRL);
2087 /* With 82543, we need to force speed and duplex on the MAC equal to what
2088 * the PHY speed and duplex configuration is. In addition, we need to
2089 * perform a hardware reset on the PHY to take it out of reset.
2090 */
2091 if (hw->mac_type > e1000_82543) {
2092 ctrl |= E1000_CTRL_SLU;
2093 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2094 E1000_WRITE_REG(hw, CTRL, ctrl);
2095 } else {
Roy Zangaa070782009-07-31 13:34:02 +08002096 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
2097 | E1000_CTRL_SLU);
wdenk682011f2003-06-03 23:54:09 +00002098 E1000_WRITE_REG(hw, CTRL, ctrl);
Roy Zangaa070782009-07-31 13:34:02 +08002099 ret_val = e1000_phy_hw_reset(hw);
2100 if (ret_val)
2101 return ret_val;
wdenk682011f2003-06-03 23:54:09 +00002102 }
2103
2104 /* Make sure we have a valid PHY */
2105 ret_val = e1000_detect_gig_phy(hw);
Roy Zangaa070782009-07-31 13:34:02 +08002106 if (ret_val) {
wdenk682011f2003-06-03 23:54:09 +00002107 DEBUGOUT("Error, did not detect valid phy.\n");
2108 return ret_val;
2109 }
2110 DEBUGOUT("Phy ID = %x \n", hw->phy_id);
2111
Roy Zangaa070782009-07-31 13:34:02 +08002112#ifndef CONFIG_AP1000
2113 /* Set PHY to class A mode (if necessary) */
2114 ret_val = e1000_set_phy_mode(hw);
2115 if (ret_val)
2116 return ret_val;
2117#endif
2118 if ((hw->mac_type == e1000_82545_rev_3) ||
2119 (hw->mac_type == e1000_82546_rev_3)) {
2120 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2121 &phy_data);
2122 phy_data |= 0x00000008;
2123 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
2124 phy_data);
wdenk682011f2003-06-03 23:54:09 +00002125 }
Roy Zangaa070782009-07-31 13:34:02 +08002126
2127 if (hw->mac_type <= e1000_82543 ||
2128 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
2129 hw->mac_type == e1000_82541_rev_2
2130 || hw->mac_type == e1000_82547_rev_2)
2131 hw->phy_reset_disable = FALSE;
2132
2133 return E1000_SUCCESS;
2134}
2135
2136/*****************************************************************************
2137 *
2138 * This function sets the lplu state according to the active flag. When
2139 * activating lplu this function also disables smart speed and vise versa.
2140 * lplu will not be activated unless the device autonegotiation advertisment
2141 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2142 * hw: Struct containing variables accessed by shared code
2143 * active - true to enable lplu false to disable lplu.
2144 *
2145 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2146 * E1000_SUCCESS at any other case.
2147 *
2148 ****************************************************************************/
2149
2150static int32_t
2151e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active)
2152{
2153 uint32_t phy_ctrl = 0;
2154 int32_t ret_val;
2155 uint16_t phy_data;
2156 DEBUGFUNC();
2157
2158 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
2159 && hw->phy_type != e1000_phy_igp_3)
2160 return E1000_SUCCESS;
2161
2162 /* During driver activity LPLU should not be used or it will attain link
2163 * from the lowest speeds starting from 10Mbps. The capability is used
2164 * for Dx transitions and states */
2165 if (hw->mac_type == e1000_82541_rev_2
2166 || hw->mac_type == e1000_82547_rev_2) {
2167 ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
2168 &phy_data);
2169 if (ret_val)
2170 return ret_val;
2171 } else if (hw->mac_type == e1000_ich8lan) {
2172 /* MAC writes into PHY register based on the state transition
2173 * and start auto-negotiation. SW driver can overwrite the
2174 * settings in CSR PHY power control E1000_PHY_CTRL register. */
2175 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2176 } else {
2177 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2178 &phy_data);
2179 if (ret_val)
2180 return ret_val;
2181 }
2182
2183 if (!active) {
2184 if (hw->mac_type == e1000_82541_rev_2 ||
2185 hw->mac_type == e1000_82547_rev_2) {
2186 phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
2187 ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
2188 phy_data);
2189 if (ret_val)
2190 return ret_val;
2191 } else {
2192 if (hw->mac_type == e1000_ich8lan) {
2193 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2194 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2195 } else {
2196 phy_data &= ~IGP02E1000_PM_D3_LPLU;
2197 ret_val = e1000_write_phy_reg(hw,
2198 IGP02E1000_PHY_POWER_MGMT, phy_data);
2199 if (ret_val)
2200 return ret_val;
2201 }
2202 }
2203
2204 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2205 * Dx states where the power conservation is most important. During
2206 * driver activity we should enable SmartSpeed, so performance is
2207 * maintained. */
2208 if (hw->smart_speed == e1000_smart_speed_on) {
2209 ret_val = e1000_read_phy_reg(hw,
2210 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2211 if (ret_val)
2212 return ret_val;
2213
2214 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2215 ret_val = e1000_write_phy_reg(hw,
2216 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2217 if (ret_val)
2218 return ret_val;
2219 } else if (hw->smart_speed == e1000_smart_speed_off) {
2220 ret_val = e1000_read_phy_reg(hw,
2221 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2222 if (ret_val)
2223 return ret_val;
2224
2225 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2226 ret_val = e1000_write_phy_reg(hw,
2227 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2228 if (ret_val)
2229 return ret_val;
2230 }
2231
2232 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
2233 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
2234 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
2235
2236 if (hw->mac_type == e1000_82541_rev_2 ||
2237 hw->mac_type == e1000_82547_rev_2) {
2238 phy_data |= IGP01E1000_GMII_FLEX_SPD;
2239 ret_val = e1000_write_phy_reg(hw,
2240 IGP01E1000_GMII_FIFO, phy_data);
2241 if (ret_val)
2242 return ret_val;
2243 } else {
2244 if (hw->mac_type == e1000_ich8lan) {
2245 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2246 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2247 } else {
2248 phy_data |= IGP02E1000_PM_D3_LPLU;
2249 ret_val = e1000_write_phy_reg(hw,
2250 IGP02E1000_PHY_POWER_MGMT, phy_data);
2251 if (ret_val)
2252 return ret_val;
2253 }
2254 }
2255
2256 /* When LPLU is enabled we should disable SmartSpeed */
2257 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2258 &phy_data);
2259 if (ret_val)
2260 return ret_val;
2261
2262 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2263 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
2264 phy_data);
2265 if (ret_val)
2266 return ret_val;
2267 }
2268 return E1000_SUCCESS;
2269}
2270
2271/*****************************************************************************
2272 *
2273 * This function sets the lplu d0 state according to the active flag. When
2274 * activating lplu this function also disables smart speed and vise versa.
2275 * lplu will not be activated unless the device autonegotiation advertisment
2276 * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
2277 * hw: Struct containing variables accessed by shared code
2278 * active - true to enable lplu false to disable lplu.
2279 *
2280 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2281 * E1000_SUCCESS at any other case.
2282 *
2283 ****************************************************************************/
2284
2285static int32_t
2286e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active)
2287{
2288 uint32_t phy_ctrl = 0;
2289 int32_t ret_val;
2290 uint16_t phy_data;
2291 DEBUGFUNC();
2292
2293 if (hw->mac_type <= e1000_82547_rev_2)
2294 return E1000_SUCCESS;
2295
2296 if (hw->mac_type == e1000_ich8lan) {
2297 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
2298 } else {
2299 ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
2300 &phy_data);
2301 if (ret_val)
2302 return ret_val;
2303 }
2304
2305 if (!active) {
2306 if (hw->mac_type == e1000_ich8lan) {
2307 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2308 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2309 } else {
2310 phy_data &= ~IGP02E1000_PM_D0_LPLU;
2311 ret_val = e1000_write_phy_reg(hw,
2312 IGP02E1000_PHY_POWER_MGMT, phy_data);
2313 if (ret_val)
2314 return ret_val;
2315 }
2316
2317 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
2318 * Dx states where the power conservation is most important. During
2319 * driver activity we should enable SmartSpeed, so performance is
2320 * maintained. */
2321 if (hw->smart_speed == e1000_smart_speed_on) {
2322 ret_val = e1000_read_phy_reg(hw,
2323 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2324 if (ret_val)
2325 return ret_val;
2326
2327 phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
2328 ret_val = e1000_write_phy_reg(hw,
2329 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2330 if (ret_val)
2331 return ret_val;
2332 } else if (hw->smart_speed == e1000_smart_speed_off) {
2333 ret_val = e1000_read_phy_reg(hw,
2334 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2335 if (ret_val)
2336 return ret_val;
2337
2338 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2339 ret_val = e1000_write_phy_reg(hw,
2340 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2341 if (ret_val)
2342 return ret_val;
2343 }
2344
2345
2346 } else {
2347
2348 if (hw->mac_type == e1000_ich8lan) {
2349 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2350 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
2351 } else {
2352 phy_data |= IGP02E1000_PM_D0_LPLU;
2353 ret_val = e1000_write_phy_reg(hw,
2354 IGP02E1000_PHY_POWER_MGMT, phy_data);
2355 if (ret_val)
2356 return ret_val;
2357 }
2358
2359 /* When LPLU is enabled we should disable SmartSpeed */
2360 ret_val = e1000_read_phy_reg(hw,
2361 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2362 if (ret_val)
2363 return ret_val;
2364
2365 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2366 ret_val = e1000_write_phy_reg(hw,
2367 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2368 if (ret_val)
2369 return ret_val;
2370
2371 }
2372 return E1000_SUCCESS;
2373}
2374
2375/********************************************************************
2376* Copper link setup for e1000_phy_igp series.
2377*
2378* hw - Struct containing variables accessed by shared code
2379*********************************************************************/
2380static int32_t
2381e1000_copper_link_igp_setup(struct e1000_hw *hw)
2382{
2383 uint32_t led_ctrl;
2384 int32_t ret_val;
2385 uint16_t phy_data;
2386
Timur Tabif81ecb52009-08-17 15:55:38 -05002387 DEBUGFUNC();
Roy Zangaa070782009-07-31 13:34:02 +08002388
2389 if (hw->phy_reset_disable)
2390 return E1000_SUCCESS;
2391
2392 ret_val = e1000_phy_reset(hw);
2393 if (ret_val) {
2394 DEBUGOUT("Error Resetting the PHY\n");
2395 return ret_val;
2396 }
2397
2398 /* Wait 15ms for MAC to configure PHY from eeprom settings */
2399 mdelay(15);
2400 if (hw->mac_type != e1000_ich8lan) {
2401 /* Configure activity LED after PHY reset */
2402 led_ctrl = E1000_READ_REG(hw, LEDCTL);
2403 led_ctrl &= IGP_ACTIVITY_LED_MASK;
2404 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
2405 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
2406 }
2407
2408 /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
2409 if (hw->phy_type == e1000_phy_igp) {
2410 /* disable lplu d3 during driver init */
2411 ret_val = e1000_set_d3_lplu_state(hw, FALSE);
2412 if (ret_val) {
2413 DEBUGOUT("Error Disabling LPLU D3\n");
2414 return ret_val;
2415 }
2416 }
2417
2418 /* disable lplu d0 during driver init */
2419 ret_val = e1000_set_d0_lplu_state(hw, FALSE);
2420 if (ret_val) {
2421 DEBUGOUT("Error Disabling LPLU D0\n");
2422 return ret_val;
2423 }
2424 /* Configure mdi-mdix settings */
2425 ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2426 if (ret_val)
2427 return ret_val;
2428
2429 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
2430 hw->dsp_config_state = e1000_dsp_config_disabled;
2431 /* Force MDI for earlier revs of the IGP PHY */
2432 phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
2433 | IGP01E1000_PSCR_FORCE_MDI_MDIX);
2434 hw->mdix = 1;
2435
2436 } else {
2437 hw->dsp_config_state = e1000_dsp_config_enabled;
2438 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2439
2440 switch (hw->mdix) {
2441 case 1:
2442 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2443 break;
2444 case 2:
2445 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
2446 break;
2447 case 0:
2448 default:
2449 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
2450 break;
2451 }
2452 }
2453 ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2454 if (ret_val)
2455 return ret_val;
2456
2457 /* set auto-master slave resolution settings */
2458 if (hw->autoneg) {
2459 e1000_ms_type phy_ms_setting = hw->master_slave;
2460
2461 if (hw->ffe_config_state == e1000_ffe_config_active)
2462 hw->ffe_config_state = e1000_ffe_config_enabled;
2463
2464 if (hw->dsp_config_state == e1000_dsp_config_activated)
2465 hw->dsp_config_state = e1000_dsp_config_enabled;
2466
2467 /* when autonegotiation advertisment is only 1000Mbps then we
2468 * should disable SmartSpeed and enable Auto MasterSlave
2469 * resolution as hardware default. */
2470 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
2471 /* Disable SmartSpeed */
2472 ret_val = e1000_read_phy_reg(hw,
2473 IGP01E1000_PHY_PORT_CONFIG, &phy_data);
2474 if (ret_val)
2475 return ret_val;
2476 phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2477 ret_val = e1000_write_phy_reg(hw,
2478 IGP01E1000_PHY_PORT_CONFIG, phy_data);
2479 if (ret_val)
2480 return ret_val;
2481 /* Set auto Master/Slave resolution process */
2482 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
2483 &phy_data);
2484 if (ret_val)
2485 return ret_val;
2486 phy_data &= ~CR_1000T_MS_ENABLE;
2487 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
2488 phy_data);
2489 if (ret_val)
2490 return ret_val;
2491 }
2492
2493 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
2494 if (ret_val)
2495 return ret_val;
2496
2497 /* load defaults for future use */
2498 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
2499 ((phy_data & CR_1000T_MS_VALUE) ?
2500 e1000_ms_force_master :
2501 e1000_ms_force_slave) :
2502 e1000_ms_auto;
2503
2504 switch (phy_ms_setting) {
2505 case e1000_ms_force_master:
2506 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2507 break;
2508 case e1000_ms_force_slave:
2509 phy_data |= CR_1000T_MS_ENABLE;
2510 phy_data &= ~(CR_1000T_MS_VALUE);
2511 break;
2512 case e1000_ms_auto:
2513 phy_data &= ~CR_1000T_MS_ENABLE;
2514 default:
2515 break;
2516 }
2517 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
2518 if (ret_val)
2519 return ret_val;
2520 }
2521
2522 return E1000_SUCCESS;
2523}
2524
2525/*****************************************************************************
2526 * This function checks the mode of the firmware.
2527 *
2528 * returns - TRUE when the mode is IAMT or FALSE.
2529 ****************************************************************************/
2530boolean_t
2531e1000_check_mng_mode(struct e1000_hw *hw)
2532{
2533 uint32_t fwsm;
2534 DEBUGFUNC();
2535
2536 fwsm = E1000_READ_REG(hw, FWSM);
2537
2538 if (hw->mac_type == e1000_ich8lan) {
2539 if ((fwsm & E1000_FWSM_MODE_MASK) ==
2540 (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2541 return TRUE;
2542 } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
2543 (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
2544 return TRUE;
2545
2546 return FALSE;
2547}
2548
2549static int32_t
2550e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
2551{
Kyle Moffett987b43a2010-09-13 05:52:22 +00002552 uint16_t swfw = E1000_SWFW_PHY0_SM;
Roy Zangaa070782009-07-31 13:34:02 +08002553 uint32_t reg_val;
Roy Zangaa070782009-07-31 13:34:02 +08002554 DEBUGFUNC();
2555
Kyle Moffett987b43a2010-09-13 05:52:22 +00002556 if (e1000_is_second_port(hw))
Roy Zangaa070782009-07-31 13:34:02 +08002557 swfw = E1000_SWFW_PHY1_SM;
Kyle Moffett987b43a2010-09-13 05:52:22 +00002558
Roy Zangaa070782009-07-31 13:34:02 +08002559 if (e1000_swfw_sync_acquire(hw, swfw))
2560 return -E1000_ERR_SWFW_SYNC;
2561
2562 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
2563 & E1000_KUMCTRLSTA_OFFSET) | data;
2564 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2565 udelay(2);
2566
2567 return E1000_SUCCESS;
2568}
2569
2570static int32_t
2571e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
2572{
Kyle Moffett987b43a2010-09-13 05:52:22 +00002573 uint16_t swfw = E1000_SWFW_PHY0_SM;
Roy Zangaa070782009-07-31 13:34:02 +08002574 uint32_t reg_val;
Roy Zangaa070782009-07-31 13:34:02 +08002575 DEBUGFUNC();
2576
Kyle Moffett987b43a2010-09-13 05:52:22 +00002577 if (e1000_is_second_port(hw))
Roy Zangaa070782009-07-31 13:34:02 +08002578 swfw = E1000_SWFW_PHY1_SM;
Kyle Moffett987b43a2010-09-13 05:52:22 +00002579
Roy Zangaa070782009-07-31 13:34:02 +08002580 if (e1000_swfw_sync_acquire(hw, swfw))
2581 return -E1000_ERR_SWFW_SYNC;
2582
2583 /* Write register address */
2584 reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
2585 E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
2586 E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
2587 udelay(2);
2588
2589 /* Read the data returned */
2590 reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
2591 *data = (uint16_t)reg_val;
2592
2593 return E1000_SUCCESS;
2594}
2595
2596/********************************************************************
2597* Copper link setup for e1000_phy_gg82563 series.
2598*
2599* hw - Struct containing variables accessed by shared code
2600*********************************************************************/
2601static int32_t
2602e1000_copper_link_ggp_setup(struct e1000_hw *hw)
2603{
2604 int32_t ret_val;
2605 uint16_t phy_data;
2606 uint32_t reg_data;
2607
2608 DEBUGFUNC();
2609
2610 if (!hw->phy_reset_disable) {
2611 /* Enable CRS on TX for half-duplex operation. */
2612 ret_val = e1000_read_phy_reg(hw,
2613 GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2614 if (ret_val)
2615 return ret_val;
2616
2617 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
2618 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
2619 phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
2620
2621 ret_val = e1000_write_phy_reg(hw,
2622 GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2623 if (ret_val)
2624 return ret_val;
2625
2626 /* Options:
2627 * MDI/MDI-X = 0 (default)
2628 * 0 - Auto for all speeds
2629 * 1 - MDI mode
2630 * 2 - MDI-X mode
2631 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2632 */
2633 ret_val = e1000_read_phy_reg(hw,
2634 GG82563_PHY_SPEC_CTRL, &phy_data);
2635 if (ret_val)
2636 return ret_val;
2637
2638 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
2639
2640 switch (hw->mdix) {
2641 case 1:
2642 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
2643 break;
2644 case 2:
2645 phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
2646 break;
2647 case 0:
2648 default:
2649 phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
2650 break;
2651 }
2652
2653 /* Options:
2654 * disable_polarity_correction = 0 (default)
2655 * Automatic Correction for Reversed Cable Polarity
2656 * 0 - Disabled
2657 * 1 - Enabled
2658 */
2659 phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
2660 ret_val = e1000_write_phy_reg(hw,
2661 GG82563_PHY_SPEC_CTRL, phy_data);
2662
2663 if (ret_val)
2664 return ret_val;
2665
2666 /* SW Reset the PHY so all changes take effect */
2667 ret_val = e1000_phy_reset(hw);
2668 if (ret_val) {
2669 DEBUGOUT("Error Resetting the PHY\n");
2670 return ret_val;
2671 }
2672 } /* phy_reset_disable */
2673
2674 if (hw->mac_type == e1000_80003es2lan) {
2675 /* Bypass RX and TX FIFO's */
2676 ret_val = e1000_write_kmrn_reg(hw,
2677 E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
2678 E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
2679 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
2680 if (ret_val)
2681 return ret_val;
2682
2683 ret_val = e1000_read_phy_reg(hw,
2684 GG82563_PHY_SPEC_CTRL_2, &phy_data);
2685 if (ret_val)
2686 return ret_val;
2687
2688 phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
2689 ret_val = e1000_write_phy_reg(hw,
2690 GG82563_PHY_SPEC_CTRL_2, phy_data);
2691
2692 if (ret_val)
2693 return ret_val;
2694
2695 reg_data = E1000_READ_REG(hw, CTRL_EXT);
2696 reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
2697 E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
2698
2699 ret_val = e1000_read_phy_reg(hw,
2700 GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
2701 if (ret_val)
2702 return ret_val;
2703
2704 /* Do not init these registers when the HW is in IAMT mode, since the
2705 * firmware will have already initialized them. We only initialize
2706 * them if the HW is not in IAMT mode.
2707 */
2708 if (e1000_check_mng_mode(hw) == FALSE) {
2709 /* Enable Electrical Idle on the PHY */
2710 phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
2711 ret_val = e1000_write_phy_reg(hw,
2712 GG82563_PHY_PWR_MGMT_CTRL, phy_data);
2713 if (ret_val)
2714 return ret_val;
2715
2716 ret_val = e1000_read_phy_reg(hw,
2717 GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
2718 if (ret_val)
2719 return ret_val;
2720
2721 phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2722 ret_val = e1000_write_phy_reg(hw,
2723 GG82563_PHY_KMRN_MODE_CTRL, phy_data);
2724
2725 if (ret_val)
2726 return ret_val;
2727 }
2728
2729 /* Workaround: Disable padding in Kumeran interface in the MAC
2730 * and in the PHY to avoid CRC errors.
2731 */
2732 ret_val = e1000_read_phy_reg(hw,
2733 GG82563_PHY_INBAND_CTRL, &phy_data);
2734 if (ret_val)
2735 return ret_val;
2736 phy_data |= GG82563_ICR_DIS_PADDING;
2737 ret_val = e1000_write_phy_reg(hw,
2738 GG82563_PHY_INBAND_CTRL, phy_data);
2739 if (ret_val)
2740 return ret_val;
2741 }
2742 return E1000_SUCCESS;
2743}
2744
2745/********************************************************************
2746* Copper link setup for e1000_phy_m88 series.
2747*
2748* hw - Struct containing variables accessed by shared code
2749*********************************************************************/
2750static int32_t
2751e1000_copper_link_mgp_setup(struct e1000_hw *hw)
2752{
2753 int32_t ret_val;
2754 uint16_t phy_data;
2755
2756 DEBUGFUNC();
2757
2758 if (hw->phy_reset_disable)
2759 return E1000_SUCCESS;
2760
2761 /* Enable CRS on TX. This must be set for half-duplex operation. */
2762 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2763 if (ret_val)
2764 return ret_val;
2765
wdenk682011f2003-06-03 23:54:09 +00002766 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2767
wdenk682011f2003-06-03 23:54:09 +00002768 /* Options:
2769 * MDI/MDI-X = 0 (default)
2770 * 0 - Auto for all speeds
2771 * 1 - MDI mode
2772 * 2 - MDI-X mode
2773 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
2774 */
2775 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
Roy Zangaa070782009-07-31 13:34:02 +08002776
wdenk682011f2003-06-03 23:54:09 +00002777 switch (hw->mdix) {
2778 case 1:
2779 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
2780 break;
2781 case 2:
2782 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
2783 break;
2784 case 3:
2785 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
2786 break;
2787 case 0:
2788 default:
2789 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
2790 break;
2791 }
wdenk682011f2003-06-03 23:54:09 +00002792
wdenk682011f2003-06-03 23:54:09 +00002793 /* Options:
2794 * disable_polarity_correction = 0 (default)
Roy Zangaa070782009-07-31 13:34:02 +08002795 * Automatic Correction for Reversed Cable Polarity
wdenk682011f2003-06-03 23:54:09 +00002796 * 0 - Disabled
2797 * 1 - Enabled
2798 */
2799 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
Roy Zangaa070782009-07-31 13:34:02 +08002800 ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2801 if (ret_val)
2802 return ret_val;
wdenk682011f2003-06-03 23:54:09 +00002803
Roy Zangaa070782009-07-31 13:34:02 +08002804 if (hw->phy_revision < M88E1011_I_REV_4) {
2805 /* Force TX_CLK in the Extended PHY Specific Control Register
2806 * to 25MHz clock.
2807 */
2808 ret_val = e1000_read_phy_reg(hw,
2809 M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2810 if (ret_val)
2811 return ret_val;
2812
2813 phy_data |= M88E1000_EPSCR_TX_CLK_25;
2814
2815 if ((hw->phy_revision == E1000_REVISION_2) &&
2816 (hw->phy_id == M88E1111_I_PHY_ID)) {
2817 /* Vidalia Phy, set the downshift counter to 5x */
2818 phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
2819 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
2820 ret_val = e1000_write_phy_reg(hw,
2821 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2822 if (ret_val)
2823 return ret_val;
2824 } else {
2825 /* Configure Master and Slave downshift values */
2826 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
2827 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
2828 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
2829 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
2830 ret_val = e1000_write_phy_reg(hw,
2831 M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2832 if (ret_val)
2833 return ret_val;
2834 }
wdenk682011f2003-06-03 23:54:09 +00002835 }
2836
2837 /* SW Reset the PHY so all changes take effect */
2838 ret_val = e1000_phy_reset(hw);
Roy Zangaa070782009-07-31 13:34:02 +08002839 if (ret_val) {
wdenk682011f2003-06-03 23:54:09 +00002840 DEBUGOUT("Error Resetting the PHY\n");
2841 return ret_val;
2842 }
2843
Roy Zangaa070782009-07-31 13:34:02 +08002844 return E1000_SUCCESS;
2845}
wdenk682011f2003-06-03 23:54:09 +00002846
Roy Zangaa070782009-07-31 13:34:02 +08002847/********************************************************************
2848* Setup auto-negotiation and flow control advertisements,
2849* and then perform auto-negotiation.
2850*
2851* hw - Struct containing variables accessed by shared code
2852*********************************************************************/
2853static int32_t
2854e1000_copper_link_autoneg(struct e1000_hw *hw)
2855{
2856 int32_t ret_val;
2857 uint16_t phy_data;
2858
2859 DEBUGFUNC();
2860
wdenk682011f2003-06-03 23:54:09 +00002861 /* Perform some bounds checking on the hw->autoneg_advertised
2862 * parameter. If this variable is zero, then set it to the default.
2863 */
2864 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
2865
2866 /* If autoneg_advertised is zero, we assume it was not defaulted
2867 * by the calling code so we set to advertise full capability.
2868 */
2869 if (hw->autoneg_advertised == 0)
2870 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
2871
Roy Zangaa070782009-07-31 13:34:02 +08002872 /* IFE phy only supports 10/100 */
2873 if (hw->phy_type == e1000_phy_ife)
2874 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
2875
wdenk682011f2003-06-03 23:54:09 +00002876 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
2877 ret_val = e1000_phy_setup_autoneg(hw);
Roy Zangaa070782009-07-31 13:34:02 +08002878 if (ret_val) {
wdenk682011f2003-06-03 23:54:09 +00002879 DEBUGOUT("Error Setting up Auto-Negotiation\n");
2880 return ret_val;
2881 }
2882 DEBUGOUT("Restarting Auto-Neg\n");
2883
2884 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
2885 * the Auto Neg Restart bit in the PHY control register.
2886 */
Roy Zangaa070782009-07-31 13:34:02 +08002887 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
2888 if (ret_val)
2889 return ret_val;
2890
wdenk682011f2003-06-03 23:54:09 +00002891 phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
Roy Zangaa070782009-07-31 13:34:02 +08002892 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
2893 if (ret_val)
2894 return ret_val;
2895
wdenk682011f2003-06-03 23:54:09 +00002896 /* Does the user want to wait for Auto-Neg to complete here, or
2897 * check at a later time (for example, callback routine).
2898 */
Roy Zangaa070782009-07-31 13:34:02 +08002899 /* If we do not wait for autonegtation to complete I
2900 * do not see a valid link status.
2901 * wait_autoneg_complete = 1 .
2902 */
wdenk682011f2003-06-03 23:54:09 +00002903 if (hw->wait_autoneg_complete) {
2904 ret_val = e1000_wait_autoneg(hw);
Roy Zangaa070782009-07-31 13:34:02 +08002905 if (ret_val) {
2906 DEBUGOUT("Error while waiting for autoneg"
2907 "to complete\n");
wdenk682011f2003-06-03 23:54:09 +00002908 return ret_val;
2909 }
2910 }
Roy Zangaa070782009-07-31 13:34:02 +08002911
2912 hw->get_link_status = TRUE;
2913
2914 return E1000_SUCCESS;
2915}
2916
2917/******************************************************************************
2918* Config the MAC and the PHY after link is up.
2919* 1) Set up the MAC to the current PHY speed/duplex
2920* if we are on 82543. If we
2921* are on newer silicon, we only need to configure
2922* collision distance in the Transmit Control Register.
2923* 2) Set up flow control on the MAC to that established with
2924* the link partner.
2925* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
2926*
2927* hw - Struct containing variables accessed by shared code
2928******************************************************************************/
2929static int32_t
2930e1000_copper_link_postconfig(struct e1000_hw *hw)
2931{
2932 int32_t ret_val;
2933 DEBUGFUNC();
2934
2935 if (hw->mac_type >= e1000_82544) {
2936 e1000_config_collision_dist(hw);
2937 } else {
2938 ret_val = e1000_config_mac_to_phy(hw);
2939 if (ret_val) {
2940 DEBUGOUT("Error configuring MAC to PHY settings\n");
2941 return ret_val;
2942 }
2943 }
2944 ret_val = e1000_config_fc_after_link_up(hw);
2945 if (ret_val) {
2946 DEBUGOUT("Error Configuring Flow Control\n");
wdenk682011f2003-06-03 23:54:09 +00002947 return ret_val;
2948 }
Roy Zangaa070782009-07-31 13:34:02 +08002949 return E1000_SUCCESS;
2950}
2951
2952/******************************************************************************
2953* Detects which PHY is present and setup the speed and duplex
2954*
2955* hw - Struct containing variables accessed by shared code
2956******************************************************************************/
2957static int
2958e1000_setup_copper_link(struct eth_device *nic)
2959{
2960 struct e1000_hw *hw = nic->priv;
2961 int32_t ret_val;
2962 uint16_t i;
2963 uint16_t phy_data;
2964 uint16_t reg_data;
2965
2966 DEBUGFUNC();
2967
2968 switch (hw->mac_type) {
2969 case e1000_80003es2lan:
2970 case e1000_ich8lan:
2971 /* Set the mac to wait the maximum time between each
2972 * iteration and increase the max iterations when
2973 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
2974 ret_val = e1000_write_kmrn_reg(hw,
2975 GG82563_REG(0x34, 4), 0xFFFF);
2976 if (ret_val)
2977 return ret_val;
2978 ret_val = e1000_read_kmrn_reg(hw,
2979 GG82563_REG(0x34, 9), &reg_data);
2980 if (ret_val)
2981 return ret_val;
2982 reg_data |= 0x3F;
2983 ret_val = e1000_write_kmrn_reg(hw,
2984 GG82563_REG(0x34, 9), reg_data);
2985 if (ret_val)
2986 return ret_val;
2987 default:
2988 break;
2989 }
2990
2991 /* Check if it is a valid PHY and set PHY mode if necessary. */
2992 ret_val = e1000_copper_link_preconfig(hw);
2993 if (ret_val)
2994 return ret_val;
2995 switch (hw->mac_type) {
2996 case e1000_80003es2lan:
2997 /* Kumeran registers are written-only */
2998 reg_data =
2999 E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
3000 reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
3001 ret_val = e1000_write_kmrn_reg(hw,
3002 E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
3003 if (ret_val)
3004 return ret_val;
3005 break;
3006 default:
3007 break;
3008 }
3009
3010 if (hw->phy_type == e1000_phy_igp ||
3011 hw->phy_type == e1000_phy_igp_3 ||
3012 hw->phy_type == e1000_phy_igp_2) {
3013 ret_val = e1000_copper_link_igp_setup(hw);
3014 if (ret_val)
3015 return ret_val;
3016 } else if (hw->phy_type == e1000_phy_m88) {
3017 ret_val = e1000_copper_link_mgp_setup(hw);
3018 if (ret_val)
3019 return ret_val;
3020 } else if (hw->phy_type == e1000_phy_gg82563) {
3021 ret_val = e1000_copper_link_ggp_setup(hw);
3022 if (ret_val)
3023 return ret_val;
3024 }
3025
3026 /* always auto */
3027 /* Setup autoneg and flow control advertisement
3028 * and perform autonegotiation */
3029 ret_val = e1000_copper_link_autoneg(hw);
3030 if (ret_val)
3031 return ret_val;
wdenk682011f2003-06-03 23:54:09 +00003032
3033 /* Check link status. Wait up to 100 microseconds for link to become
3034 * valid.
3035 */
3036 for (i = 0; i < 10; i++) {
Roy Zangaa070782009-07-31 13:34:02 +08003037 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3038 if (ret_val)
3039 return ret_val;
3040 ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3041 if (ret_val)
3042 return ret_val;
3043
wdenk682011f2003-06-03 23:54:09 +00003044 if (phy_data & MII_SR_LINK_STATUS) {
Roy Zangaa070782009-07-31 13:34:02 +08003045 /* Config the MAC and PHY after link is up */
3046 ret_val = e1000_copper_link_postconfig(hw);
3047 if (ret_val)
wdenk682011f2003-06-03 23:54:09 +00003048 return ret_val;
Roy Zangaa070782009-07-31 13:34:02 +08003049
wdenk682011f2003-06-03 23:54:09 +00003050 DEBUGOUT("Valid link established!!!\n");
Roy Zangaa070782009-07-31 13:34:02 +08003051 return E1000_SUCCESS;
wdenk682011f2003-06-03 23:54:09 +00003052 }
3053 udelay(10);
3054 }
3055
3056 DEBUGOUT("Unable to establish link!!!\n");
Roy Zangaa070782009-07-31 13:34:02 +08003057 return E1000_SUCCESS;
wdenk682011f2003-06-03 23:54:09 +00003058}
3059
3060/******************************************************************************
3061* Configures PHY autoneg and flow control advertisement settings
3062*
3063* hw - Struct containing variables accessed by shared code
3064******************************************************************************/
Roy Zangaa070782009-07-31 13:34:02 +08003065int32_t
wdenk682011f2003-06-03 23:54:09 +00003066e1000_phy_setup_autoneg(struct e1000_hw *hw)
3067{
Roy Zangaa070782009-07-31 13:34:02 +08003068 int32_t ret_val;
wdenk682011f2003-06-03 23:54:09 +00003069 uint16_t mii_autoneg_adv_reg;
3070 uint16_t mii_1000t_ctrl_reg;
3071
3072 DEBUGFUNC();
3073
3074 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
Roy Zangaa070782009-07-31 13:34:02 +08003075 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
3076 if (ret_val)
3077 return ret_val;
wdenk682011f2003-06-03 23:54:09 +00003078
Roy Zangaa070782009-07-31 13:34:02 +08003079 if (hw->phy_type != e1000_phy_ife) {
3080 /* Read the MII 1000Base-T Control Register (Address 9). */
3081 ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
3082 &mii_1000t_ctrl_reg);
3083 if (ret_val)
3084 return ret_val;
3085 } else
3086 mii_1000t_ctrl_reg = 0;
wdenk682011f2003-06-03 23:54:09 +00003087
3088 /* Need to parse both autoneg_advertised and fc and set up
3089 * the appropriate PHY registers. First we will parse for
3090 * autoneg_advertised software override. Since we can advertise
3091 * a plethora of combinations, we need to check each bit
3092 * individually.
3093 */
3094
3095 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
3096 * Advertisement Register (Address 4) and the 1000 mb speed bits in
Roy Zangaa070782009-07-31 13:34:02 +08003097 * the 1000Base-T Control Register (Address 9).
wdenk682011f2003-06-03 23:54:09 +00003098 */
3099 mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
3100 mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
3101
3102 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
3103
3104 /* Do we want to advertise 10 Mb Half Duplex? */
3105 if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
3106 DEBUGOUT("Advertise 10mb Half duplex\n");
3107 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
3108 }
3109
3110 /* Do we want to advertise 10 Mb Full Duplex? */
3111 if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
3112 DEBUGOUT("Advertise 10mb Full duplex\n");
3113 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
3114 }
3115
3116 /* Do we want to advertise 100 Mb Half Duplex? */
3117 if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
3118 DEBUGOUT("Advertise 100mb Half duplex\n");
3119 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
3120 }
3121
3122 /* Do we want to advertise 100 Mb Full Duplex? */
3123 if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
3124 DEBUGOUT("Advertise 100mb Full duplex\n");
3125 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
3126 }
3127
3128 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
3129 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
3130 DEBUGOUT
3131 ("Advertise 1000mb Half duplex requested, request denied!\n");
3132 }
3133
3134 /* Do we want to advertise 1000 Mb Full Duplex? */
3135 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
3136 DEBUGOUT("Advertise 1000mb Full duplex\n");
3137 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
3138 }
3139
3140 /* Check for a software override of the flow control settings, and
3141 * setup the PHY advertisement registers accordingly. If
3142 * auto-negotiation is enabled, then software will have to set the
3143 * "PAUSE" bits to the correct value in the Auto-Negotiation
3144 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
3145 *
3146 * The possible values of the "fc" parameter are:
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07003147 * 0: Flow control is completely disabled
3148 * 1: Rx flow control is enabled (we can receive pause frames
3149 * but not send pause frames).
3150 * 2: Tx flow control is enabled (we can send pause frames
3151 * but we do not support receiving pause frames).
3152 * 3: Both Rx and TX flow control (symmetric) are enabled.
wdenk682011f2003-06-03 23:54:09 +00003153 * other: No software override. The flow control configuration
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07003154 * in the EEPROM is used.
wdenk682011f2003-06-03 23:54:09 +00003155 */
3156 switch (hw->fc) {
3157 case e1000_fc_none: /* 0 */
3158 /* Flow control (RX & TX) is completely disabled by a
3159 * software over-ride.
3160 */
3161 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3162 break;
3163 case e1000_fc_rx_pause: /* 1 */
3164 /* RX Flow control is enabled, and TX Flow control is
3165 * disabled, by a software over-ride.
3166 */
3167 /* Since there really isn't a way to advertise that we are
3168 * capable of RX Pause ONLY, we will advertise that we
3169 * support both symmetric and asymmetric RX PAUSE. Later
3170 * (in e1000_config_fc_after_link_up) we will disable the
3171 *hw's ability to send PAUSE frames.
3172 */
3173 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3174 break;
3175 case e1000_fc_tx_pause: /* 2 */
3176 /* TX Flow control is enabled, and RX Flow control is
3177 * disabled, by a software over-ride.
3178 */
3179 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
3180 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
3181 break;
3182 case e1000_fc_full: /* 3 */
3183 /* Flow control (both RX and TX) is enabled by a software
3184 * over-ride.
3185 */
3186 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
3187 break;
3188 default:
3189 DEBUGOUT("Flow control param set incorrectly\n");
3190 return -E1000_ERR_CONFIG;
3191 }
3192
Roy Zangaa070782009-07-31 13:34:02 +08003193 ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
3194 if (ret_val)
3195 return ret_val;
wdenk682011f2003-06-03 23:54:09 +00003196
3197 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
3198
Roy Zangaa070782009-07-31 13:34:02 +08003199 if (hw->phy_type != e1000_phy_ife) {
3200 ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
3201 mii_1000t_ctrl_reg);
3202 if (ret_val)
3203 return ret_val;
wdenk682011f2003-06-03 23:54:09 +00003204 }
Roy Zangaa070782009-07-31 13:34:02 +08003205
3206 return E1000_SUCCESS;
wdenk682011f2003-06-03 23:54:09 +00003207}
3208
3209/******************************************************************************
3210* Sets the collision distance in the Transmit Control register
3211*
3212* hw - Struct containing variables accessed by shared code
3213*
3214* Link should have been established previously. Reads the speed and duplex
3215* information from the Device Status register.
3216******************************************************************************/
3217static void
3218e1000_config_collision_dist(struct e1000_hw *hw)
3219{
Roy Zangaa070782009-07-31 13:34:02 +08003220 uint32_t tctl, coll_dist;
3221
3222 DEBUGFUNC();
3223
3224 if (hw->mac_type < e1000_82543)
3225 coll_dist = E1000_COLLISION_DISTANCE_82542;
3226 else
3227 coll_dist = E1000_COLLISION_DISTANCE;
wdenk682011f2003-06-03 23:54:09 +00003228
3229 tctl = E1000_READ_REG(hw, TCTL);
3230
3231 tctl &= ~E1000_TCTL_COLD;
Roy Zangaa070782009-07-31 13:34:02 +08003232 tctl |= coll_dist << E1000_COLD_SHIFT;
wdenk682011f2003-06-03 23:54:09 +00003233
3234 E1000_WRITE_REG(hw, TCTL, tctl);
3235 E1000_WRITE_FLUSH(hw);
3236}
3237
3238/******************************************************************************
3239* Sets MAC speed and duplex settings to reflect the those in the PHY
3240*
3241* hw - Struct containing variables accessed by shared code
3242* mii_reg - data to write to the MII control register
3243*
3244* The contents of the PHY register containing the needed information need to
3245* be passed in.
3246******************************************************************************/
3247static int
3248e1000_config_mac_to_phy(struct e1000_hw *hw)
3249{
3250 uint32_t ctrl;
3251 uint16_t phy_data;
3252
3253 DEBUGFUNC();
3254
3255 /* Read the Device Control Register and set the bits to Force Speed
3256 * and Duplex.
3257 */
3258 ctrl = E1000_READ_REG(hw, CTRL);
3259 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3260 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
3261
3262 /* Set up duplex in the Device Control and Transmit Control
3263 * registers depending on negotiated values.
3264 */
3265 if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
3266 DEBUGOUT("PHY Read Error\n");
3267 return -E1000_ERR_PHY;
3268 }
3269 if (phy_data & M88E1000_PSSR_DPLX)
3270 ctrl |= E1000_CTRL_FD;
3271 else
3272 ctrl &= ~E1000_CTRL_FD;
3273
3274 e1000_config_collision_dist(hw);
3275
3276 /* Set up speed in the Device Control register depending on
3277 * negotiated values.
3278 */
3279 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
3280 ctrl |= E1000_CTRL_SPD_1000;
3281 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
3282 ctrl |= E1000_CTRL_SPD_100;
3283 /* Write the configured values back to the Device Control Reg. */
3284 E1000_WRITE_REG(hw, CTRL, ctrl);
3285 return 0;
3286}
3287
3288/******************************************************************************
3289 * Forces the MAC's flow control settings.
wdenk8bde7f72003-06-27 21:31:46 +00003290 *
wdenk682011f2003-06-03 23:54:09 +00003291 * hw - Struct containing variables accessed by shared code
3292 *
3293 * Sets the TFCE and RFCE bits in the device control register to reflect
3294 * the adapter settings. TFCE and RFCE need to be explicitly set by
3295 * software when a Copper PHY is used because autonegotiation is managed
3296 * by the PHY rather than the MAC. Software must also configure these
3297 * bits when link is forced on a fiber connection.
3298 *****************************************************************************/
3299static int
3300e1000_force_mac_fc(struct e1000_hw *hw)
3301{
3302 uint32_t ctrl;
3303
3304 DEBUGFUNC();
3305
3306 /* Get the current configuration of the Device Control Register */
3307 ctrl = E1000_READ_REG(hw, CTRL);
3308
3309 /* Because we didn't get link via the internal auto-negotiation
3310 * mechanism (we either forced link or we got link via PHY
3311 * auto-neg), we have to manually enable/disable transmit an
3312 * receive flow control.
3313 *
3314 * The "Case" statement below enables/disable flow control
3315 * according to the "hw->fc" parameter.
3316 *
3317 * The possible values of the "fc" parameter are:
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07003318 * 0: Flow control is completely disabled
3319 * 1: Rx flow control is enabled (we can receive pause
3320 * frames but not send pause frames).
3321 * 2: Tx flow control is enabled (we can send pause frames
3322 * frames but we do not receive pause frames).
3323 * 3: Both Rx and TX flow control (symmetric) is enabled.
wdenk682011f2003-06-03 23:54:09 +00003324 * other: No other values should be possible at this point.
3325 */
3326
3327 switch (hw->fc) {
3328 case e1000_fc_none:
3329 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
3330 break;
3331 case e1000_fc_rx_pause:
3332 ctrl &= (~E1000_CTRL_TFCE);
3333 ctrl |= E1000_CTRL_RFCE;
3334 break;
3335 case e1000_fc_tx_pause:
3336 ctrl &= (~E1000_CTRL_RFCE);
3337 ctrl |= E1000_CTRL_TFCE;
3338 break;
3339 case e1000_fc_full:
3340 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
3341 break;
3342 default:
3343 DEBUGOUT("Flow control param set incorrectly\n");
3344 return -E1000_ERR_CONFIG;
3345 }
3346
3347 /* Disable TX Flow Control for 82542 (rev 2.0) */
3348 if (hw->mac_type == e1000_82542_rev2_0)
3349 ctrl &= (~E1000_CTRL_TFCE);
3350
3351 E1000_WRITE_REG(hw, CTRL, ctrl);
3352 return 0;
3353}
3354
3355/******************************************************************************
3356 * Configures flow control settings after link is established
wdenk8bde7f72003-06-27 21:31:46 +00003357 *
wdenk682011f2003-06-03 23:54:09 +00003358 * hw - Struct containing variables accessed by shared code
3359 *
3360 * Should be called immediately after a valid link has been established.
3361 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3362 * and autonegotiation is enabled, the MAC flow control settings will be set
3363 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3364 * and RFCE bits will be automaticaly set to the negotiated flow control mode.
3365 *****************************************************************************/
Roy Zangaa070782009-07-31 13:34:02 +08003366static int32_t
wdenk682011f2003-06-03 23:54:09 +00003367e1000_config_fc_after_link_up(struct e1000_hw *hw)
3368{
3369 int32_t ret_val;
3370 uint16_t mii_status_reg;
3371 uint16_t mii_nway_adv_reg;
3372 uint16_t mii_nway_lp_ability_reg;
3373 uint16_t speed;
3374 uint16_t duplex;
3375
3376 DEBUGFUNC();
3377
3378 /* Check for the case where we have fiber media and auto-neg failed
3379 * so we had to force link. In this case, we need to force the
3380 * configuration of the MAC to match the "fc" parameter.
3381 */
Roy Zangaa070782009-07-31 13:34:02 +08003382 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
3383 || ((hw->media_type == e1000_media_type_internal_serdes)
3384 && (hw->autoneg_failed))
3385 || ((hw->media_type == e1000_media_type_copper)
3386 && (!hw->autoneg))) {
wdenk682011f2003-06-03 23:54:09 +00003387 ret_val = e1000_force_mac_fc(hw);
3388 if (ret_val < 0) {
3389 DEBUGOUT("Error forcing flow control settings\n");
3390 return ret_val;
3391 }
3392 }
3393
3394 /* Check for the case where we have copper media and auto-neg is
3395 * enabled. In this case, we need to check and see if Auto-Neg
3396 * has completed, and if so, how the PHY and link partner has
3397 * flow control configured.
3398 */
3399 if (hw->media_type == e1000_media_type_copper) {
3400 /* Read the MII Status Register and check to see if AutoNeg
3401 * has completed. We read this twice because this reg has
3402 * some "sticky" (latched) bits.
3403 */
3404 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3405 DEBUGOUT("PHY Read Error \n");
3406 return -E1000_ERR_PHY;
3407 }
3408 if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
3409 DEBUGOUT("PHY Read Error \n");
3410 return -E1000_ERR_PHY;
3411 }
3412
3413 if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
3414 /* The AutoNeg process has completed, so we now need to
3415 * read both the Auto Negotiation Advertisement Register
3416 * (Address 4) and the Auto_Negotiation Base Page Ability
3417 * Register (Address 5) to determine how flow control was
3418 * negotiated.
3419 */
3420 if (e1000_read_phy_reg
3421 (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
3422 DEBUGOUT("PHY Read Error\n");
3423 return -E1000_ERR_PHY;
3424 }
3425 if (e1000_read_phy_reg
3426 (hw, PHY_LP_ABILITY,
3427 &mii_nway_lp_ability_reg) < 0) {
3428 DEBUGOUT("PHY Read Error\n");
3429 return -E1000_ERR_PHY;
3430 }
3431
3432 /* Two bits in the Auto Negotiation Advertisement Register
3433 * (Address 4) and two bits in the Auto Negotiation Base
3434 * Page Ability Register (Address 5) determine flow control
3435 * for both the PHY and the link partner. The following
3436 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
3437 * 1999, describes these PAUSE resolution bits and how flow
3438 * control is determined based upon these settings.
3439 * NOTE: DC = Don't Care
3440 *
3441 * LOCAL DEVICE | LINK PARTNER
3442 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
3443 *-------|---------|-------|---------|--------------------
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07003444 * 0 | 0 | DC | DC | e1000_fc_none
3445 * 0 | 1 | 0 | DC | e1000_fc_none
3446 * 0 | 1 | 1 | 0 | e1000_fc_none
3447 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
3448 * 1 | 0 | 0 | DC | e1000_fc_none
3449 * 1 | DC | 1 | DC | e1000_fc_full
3450 * 1 | 1 | 0 | 0 | e1000_fc_none
3451 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
wdenk682011f2003-06-03 23:54:09 +00003452 *
3453 */
3454 /* Are both PAUSE bits set to 1? If so, this implies
3455 * Symmetric Flow Control is enabled at both ends. The
3456 * ASM_DIR bits are irrelevant per the spec.
3457 *
3458 * For Symmetric Flow Control:
3459 *
3460 * LOCAL DEVICE | LINK PARTNER
3461 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3462 *-------|---------|-------|---------|--------------------
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07003463 * 1 | DC | 1 | DC | e1000_fc_full
wdenk682011f2003-06-03 23:54:09 +00003464 *
3465 */
3466 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3467 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
3468 /* Now we need to check if the user selected RX ONLY
3469 * of pause frames. In this case, we had to advertise
3470 * FULL flow control because we could not advertise RX
3471 * ONLY. Hence, we must now check to see if we need to
3472 * turn OFF the TRANSMISSION of PAUSE frames.
3473 */
3474 if (hw->original_fc == e1000_fc_full) {
3475 hw->fc = e1000_fc_full;
3476 DEBUGOUT("Flow Control = FULL.\r\n");
3477 } else {
3478 hw->fc = e1000_fc_rx_pause;
3479 DEBUGOUT
3480 ("Flow Control = RX PAUSE frames only.\r\n");
3481 }
3482 }
3483 /* For receiving PAUSE frames ONLY.
3484 *
3485 * LOCAL DEVICE | LINK PARTNER
3486 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3487 *-------|---------|-------|---------|--------------------
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07003488 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
wdenk682011f2003-06-03 23:54:09 +00003489 *
3490 */
3491 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3492 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3493 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3494 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3495 {
3496 hw->fc = e1000_fc_tx_pause;
3497 DEBUGOUT
3498 ("Flow Control = TX PAUSE frames only.\r\n");
3499 }
3500 /* For transmitting PAUSE frames ONLY.
3501 *
3502 * LOCAL DEVICE | LINK PARTNER
3503 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
3504 *-------|---------|-------|---------|--------------------
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07003505 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
wdenk682011f2003-06-03 23:54:09 +00003506 *
3507 */
3508 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
3509 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
3510 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
3511 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
3512 {
3513 hw->fc = e1000_fc_rx_pause;
3514 DEBUGOUT
3515 ("Flow Control = RX PAUSE frames only.\r\n");
3516 }
3517 /* Per the IEEE spec, at this point flow control should be
3518 * disabled. However, we want to consider that we could
3519 * be connected to a legacy switch that doesn't advertise
3520 * desired flow control, but can be forced on the link
3521 * partner. So if we advertised no flow control, that is
3522 * what we will resolve to. If we advertised some kind of
3523 * receive capability (Rx Pause Only or Full Flow Control)
3524 * and the link partner advertised none, we will configure
3525 * ourselves to enable Rx Flow Control only. We can do
3526 * this safely for two reasons: If the link partner really
3527 * didn't want flow control enabled, and we enable Rx, no
3528 * harm done since we won't be receiving any PAUSE frames
3529 * anyway. If the intent on the link partner was to have
3530 * flow control enabled, then by us enabling RX only, we
3531 * can at least receive pause frames and process them.
3532 * This is a good idea because in most cases, since we are
3533 * predominantly a server NIC, more times than not we will
3534 * be asked to delay transmission of packets than asking
3535 * our link partner to pause transmission of frames.
3536 */
3537 else if (hw->original_fc == e1000_fc_none ||
3538 hw->original_fc == e1000_fc_tx_pause) {
3539 hw->fc = e1000_fc_none;
3540 DEBUGOUT("Flow Control = NONE.\r\n");
3541 } else {
3542 hw->fc = e1000_fc_rx_pause;
3543 DEBUGOUT
3544 ("Flow Control = RX PAUSE frames only.\r\n");
3545 }
3546
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07003547 /* Now we need to do one last check... If we auto-
wdenk682011f2003-06-03 23:54:09 +00003548 * negotiated to HALF DUPLEX, flow control should not be
3549 * enabled per IEEE 802.3 spec.
3550 */
3551 e1000_get_speed_and_duplex(hw, &speed, &duplex);
3552
3553 if (duplex == HALF_DUPLEX)
3554 hw->fc = e1000_fc_none;
3555
3556 /* Now we call a subroutine to actually force the MAC
3557 * controller to use the correct flow control settings.
3558 */
3559 ret_val = e1000_force_mac_fc(hw);
3560 if (ret_val < 0) {
3561 DEBUGOUT
3562 ("Error forcing flow control settings\n");
3563 return ret_val;
3564 }
3565 } else {
3566 DEBUGOUT
3567 ("Copper PHY and Auto Neg has not completed.\r\n");
3568 }
3569 }
Roy Zangaa070782009-07-31 13:34:02 +08003570 return E1000_SUCCESS;
wdenk682011f2003-06-03 23:54:09 +00003571}
3572
3573/******************************************************************************
3574 * Checks to see if the link status of the hardware has changed.
3575 *
3576 * hw - Struct containing variables accessed by shared code
3577 *
3578 * Called by any function that needs to check the link status of the adapter.
3579 *****************************************************************************/
3580static int
3581e1000_check_for_link(struct eth_device *nic)
3582{
3583 struct e1000_hw *hw = nic->priv;
3584 uint32_t rxcw;
3585 uint32_t ctrl;
3586 uint32_t status;
3587 uint32_t rctl;
3588 uint32_t signal;
3589 int32_t ret_val;
3590 uint16_t phy_data;
3591 uint16_t lp_capability;
3592
3593 DEBUGFUNC();
3594
wdenk8bde7f72003-06-27 21:31:46 +00003595 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
3596 * set when the optics detect a signal. On older adapters, it will be
wdenk682011f2003-06-03 23:54:09 +00003597 * cleared when there is a signal
3598 */
3599 ctrl = E1000_READ_REG(hw, CTRL);
3600 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
3601 signal = E1000_CTRL_SWDPIN1;
3602 else
3603 signal = 0;
3604
3605 status = E1000_READ_REG(hw, STATUS);
3606 rxcw = E1000_READ_REG(hw, RXCW);
3607 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
3608
3609 /* If we have a copper PHY then we only want to go out to the PHY
3610 * registers to see if Auto-Neg has completed and/or if our link
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07003611 * status has changed. The get_link_status flag will be set if we
wdenk682011f2003-06-03 23:54:09 +00003612 * receive a Link Status Change interrupt or we have Rx Sequence
3613 * Errors.
3614 */
3615 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
3616 /* First we want to see if the MII Status Register reports
3617 * link. If so, then we want to get the current speed/duplex
3618 * of the PHY.
3619 * Read the register twice since the link bit is sticky.
3620 */
3621 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3622 DEBUGOUT("PHY Read Error\n");
3623 return -E1000_ERR_PHY;
3624 }
3625 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3626 DEBUGOUT("PHY Read Error\n");
3627 return -E1000_ERR_PHY;
3628 }
3629
3630 if (phy_data & MII_SR_LINK_STATUS) {
3631 hw->get_link_status = FALSE;
3632 } else {
3633 /* No link detected */
3634 return -E1000_ERR_NOLINK;
3635 }
3636
3637 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3638 * have Si on board that is 82544 or newer, Auto
3639 * Speed Detection takes care of MAC speed/duplex
3640 * configuration. So we only need to configure Collision
3641 * Distance in the MAC. Otherwise, we need to force
3642 * speed/duplex on the MAC to the current PHY speed/duplex
3643 * settings.
3644 */
3645 if (hw->mac_type >= e1000_82544)
3646 e1000_config_collision_dist(hw);
3647 else {
3648 ret_val = e1000_config_mac_to_phy(hw);
3649 if (ret_val < 0) {
3650 DEBUGOUT
3651 ("Error configuring MAC to PHY settings\n");
3652 return ret_val;
3653 }
3654 }
3655
wdenk8bde7f72003-06-27 21:31:46 +00003656 /* Configure Flow Control now that Auto-Neg has completed. First, we
wdenk682011f2003-06-03 23:54:09 +00003657 * need to restore the desired flow control settings because we may
3658 * have had to re-autoneg with a different link partner.
3659 */
3660 ret_val = e1000_config_fc_after_link_up(hw);
3661 if (ret_val < 0) {
3662 DEBUGOUT("Error configuring flow control\n");
3663 return ret_val;
3664 }
3665
3666 /* At this point we know that we are on copper and we have
3667 * auto-negotiated link. These are conditions for checking the link
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07003668 * parter capability register. We use the link partner capability to
wdenk682011f2003-06-03 23:54:09 +00003669 * determine if TBI Compatibility needs to be turned on or off. If
3670 * the link partner advertises any speed in addition to Gigabit, then
3671 * we assume that they are GMII-based, and TBI compatibility is not
3672 * needed. If no other speeds are advertised, we assume the link
3673 * partner is TBI-based, and we turn on TBI Compatibility.
3674 */
3675 if (hw->tbi_compatibility_en) {
3676 if (e1000_read_phy_reg
3677 (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
3678 DEBUGOUT("PHY Read Error\n");
3679 return -E1000_ERR_PHY;
3680 }
3681 if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
3682 NWAY_LPAR_10T_FD_CAPS |
3683 NWAY_LPAR_100TX_HD_CAPS |
3684 NWAY_LPAR_100TX_FD_CAPS |
3685 NWAY_LPAR_100T4_CAPS)) {
wdenk8bde7f72003-06-27 21:31:46 +00003686 /* If our link partner advertises anything in addition to
wdenk682011f2003-06-03 23:54:09 +00003687 * gigabit, we do not need to enable TBI compatibility.
3688 */
3689 if (hw->tbi_compatibility_on) {
3690 /* If we previously were in the mode, turn it off. */
3691 rctl = E1000_READ_REG(hw, RCTL);
3692 rctl &= ~E1000_RCTL_SBP;
3693 E1000_WRITE_REG(hw, RCTL, rctl);
3694 hw->tbi_compatibility_on = FALSE;
3695 }
3696 } else {
3697 /* If TBI compatibility is was previously off, turn it on. For
3698 * compatibility with a TBI link partner, we will store bad
3699 * packets. Some frames have an additional byte on the end and
3700 * will look like CRC errors to to the hardware.
3701 */
3702 if (!hw->tbi_compatibility_on) {
3703 hw->tbi_compatibility_on = TRUE;
3704 rctl = E1000_READ_REG(hw, RCTL);
3705 rctl |= E1000_RCTL_SBP;
3706 E1000_WRITE_REG(hw, RCTL, rctl);
3707 }
3708 }
3709 }
3710 }
3711 /* If we don't have link (auto-negotiation failed or link partner cannot
3712 * auto-negotiate), the cable is plugged in (we have signal), and our
3713 * link partner is not trying to auto-negotiate with us (we are receiving
3714 * idles or data), we need to force link up. We also need to give
3715 * auto-negotiation time to complete, in case the cable was just plugged
3716 * in. The autoneg_failed flag does this.
3717 */
3718 else if ((hw->media_type == e1000_media_type_fiber) &&
3719 (!(status & E1000_STATUS_LU)) &&
3720 ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
3721 (!(rxcw & E1000_RXCW_C))) {
3722 if (hw->autoneg_failed == 0) {
3723 hw->autoneg_failed = 1;
3724 return 0;
3725 }
3726 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
3727
3728 /* Disable auto-negotiation in the TXCW register */
3729 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3730
3731 /* Force link-up and also force full-duplex. */
3732 ctrl = E1000_READ_REG(hw, CTRL);
3733 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
3734 E1000_WRITE_REG(hw, CTRL, ctrl);
3735
3736 /* Configure Flow Control after forcing link up. */
3737 ret_val = e1000_config_fc_after_link_up(hw);
3738 if (ret_val < 0) {
3739 DEBUGOUT("Error configuring flow control\n");
3740 return ret_val;
3741 }
3742 }
3743 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3744 * auto-negotiation in the TXCW register and disable forced link in the
3745 * Device Control register in an attempt to auto-negotiate with our link
3746 * partner.
3747 */
3748 else if ((hw->media_type == e1000_media_type_fiber) &&
3749 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3750 DEBUGOUT
3751 ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
3752 E1000_WRITE_REG(hw, TXCW, hw->txcw);
3753 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3754 }
3755 return 0;
3756}
3757
3758/******************************************************************************
Roy Zangaa070782009-07-31 13:34:02 +08003759* Configure the MAC-to-PHY interface for 10/100Mbps
3760*
3761* hw - Struct containing variables accessed by shared code
3762******************************************************************************/
3763static int32_t
3764e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
3765{
3766 int32_t ret_val = E1000_SUCCESS;
3767 uint32_t tipg;
3768 uint16_t reg_data;
3769
3770 DEBUGFUNC();
3771
3772 reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
3773 ret_val = e1000_write_kmrn_reg(hw,
3774 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3775 if (ret_val)
3776 return ret_val;
3777
3778 /* Configure Transmit Inter-Packet Gap */
3779 tipg = E1000_READ_REG(hw, TIPG);
3780 tipg &= ~E1000_TIPG_IPGT_MASK;
3781 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
3782 E1000_WRITE_REG(hw, TIPG, tipg);
3783
3784 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3785
3786 if (ret_val)
3787 return ret_val;
3788
3789 if (duplex == HALF_DUPLEX)
3790 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
3791 else
3792 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3793
3794 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3795
3796 return ret_val;
3797}
3798
3799static int32_t
3800e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
3801{
3802 int32_t ret_val = E1000_SUCCESS;
3803 uint16_t reg_data;
3804 uint32_t tipg;
3805
3806 DEBUGFUNC();
3807
3808 reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
3809 ret_val = e1000_write_kmrn_reg(hw,
3810 E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
3811 if (ret_val)
3812 return ret_val;
3813
3814 /* Configure Transmit Inter-Packet Gap */
3815 tipg = E1000_READ_REG(hw, TIPG);
3816 tipg &= ~E1000_TIPG_IPGT_MASK;
3817 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
3818 E1000_WRITE_REG(hw, TIPG, tipg);
3819
3820 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
3821
3822 if (ret_val)
3823 return ret_val;
3824
3825 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
3826 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
3827
3828 return ret_val;
3829}
3830
3831/******************************************************************************
wdenk682011f2003-06-03 23:54:09 +00003832 * Detects the current speed and duplex settings of the hardware.
3833 *
3834 * hw - Struct containing variables accessed by shared code
3835 * speed - Speed of the connection
3836 * duplex - Duplex setting of the connection
3837 *****************************************************************************/
Roy Zangaa070782009-07-31 13:34:02 +08003838static int
3839e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
3840 uint16_t *duplex)
wdenk682011f2003-06-03 23:54:09 +00003841{
3842 uint32_t status;
Roy Zangaa070782009-07-31 13:34:02 +08003843 int32_t ret_val;
3844 uint16_t phy_data;
wdenk682011f2003-06-03 23:54:09 +00003845
3846 DEBUGFUNC();
3847
3848 if (hw->mac_type >= e1000_82543) {
3849 status = E1000_READ_REG(hw, STATUS);
3850 if (status & E1000_STATUS_SPEED_1000) {
3851 *speed = SPEED_1000;
3852 DEBUGOUT("1000 Mbs, ");
3853 } else if (status & E1000_STATUS_SPEED_100) {
3854 *speed = SPEED_100;
3855 DEBUGOUT("100 Mbs, ");
3856 } else {
3857 *speed = SPEED_10;
3858 DEBUGOUT("10 Mbs, ");
3859 }
3860
3861 if (status & E1000_STATUS_FD) {
3862 *duplex = FULL_DUPLEX;
3863 DEBUGOUT("Full Duplex\r\n");
3864 } else {
3865 *duplex = HALF_DUPLEX;
3866 DEBUGOUT(" Half Duplex\r\n");
3867 }
3868 } else {
3869 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
3870 *speed = SPEED_1000;
3871 *duplex = FULL_DUPLEX;
3872 }
Roy Zangaa070782009-07-31 13:34:02 +08003873
3874 /* IGP01 PHY may advertise full duplex operation after speed downgrade
3875 * even if it is operating at half duplex. Here we set the duplex
3876 * settings to match the duplex in the link partner's capabilities.
3877 */
3878 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3879 ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3880 if (ret_val)
3881 return ret_val;
3882
3883 if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3884 *duplex = HALF_DUPLEX;
3885 else {
3886 ret_val = e1000_read_phy_reg(hw,
3887 PHY_LP_ABILITY, &phy_data);
3888 if (ret_val)
3889 return ret_val;
3890 if ((*speed == SPEED_100 &&
3891 !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
3892 || (*speed == SPEED_10
3893 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3894 *duplex = HALF_DUPLEX;
3895 }
3896 }
3897
3898 if ((hw->mac_type == e1000_80003es2lan) &&
3899 (hw->media_type == e1000_media_type_copper)) {
3900 if (*speed == SPEED_1000)
3901 ret_val = e1000_configure_kmrn_for_1000(hw);
3902 else
3903 ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3904 if (ret_val)
3905 return ret_val;
3906 }
3907 return E1000_SUCCESS;
wdenk682011f2003-06-03 23:54:09 +00003908}
3909
3910/******************************************************************************
3911* Blocks until autoneg completes or times out (~4.5 seconds)
3912*
3913* hw - Struct containing variables accessed by shared code
3914******************************************************************************/
3915static int
3916e1000_wait_autoneg(struct e1000_hw *hw)
3917{
3918 uint16_t i;
3919 uint16_t phy_data;
3920
3921 DEBUGFUNC();
3922 DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3923
3924 /* We will wait for autoneg to complete or 4.5 seconds to expire. */
3925 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3926 /* Read the MII Status Register and wait for Auto-Neg
3927 * Complete bit to be set.
3928 */
3929 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3930 DEBUGOUT("PHY Read Error\n");
3931 return -E1000_ERR_PHY;
3932 }
3933 if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
3934 DEBUGOUT("PHY Read Error\n");
3935 return -E1000_ERR_PHY;
3936 }
3937 if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3938 DEBUGOUT("Auto-Neg complete.\n");
3939 return 0;
3940 }
3941 mdelay(100);
3942 }
3943 DEBUGOUT("Auto-Neg timedout.\n");
3944 return -E1000_ERR_TIMEOUT;
3945}
3946
3947/******************************************************************************
3948* Raises the Management Data Clock
3949*
3950* hw - Struct containing variables accessed by shared code
3951* ctrl - Device control register's current value
3952******************************************************************************/
3953static void
3954e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3955{
3956 /* Raise the clock input to the Management Data Clock (by setting the MDC
3957 * bit), and then delay 2 microseconds.
3958 */
3959 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
3960 E1000_WRITE_FLUSH(hw);
3961 udelay(2);
3962}
3963
3964/******************************************************************************
3965* Lowers the Management Data Clock
3966*
3967* hw - Struct containing variables accessed by shared code
3968* ctrl - Device control register's current value
3969******************************************************************************/
3970static void
3971e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
3972{
3973 /* Lower the clock input to the Management Data Clock (by clearing the MDC
3974 * bit), and then delay 2 microseconds.
3975 */
3976 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3977 E1000_WRITE_FLUSH(hw);
3978 udelay(2);
3979}
3980
3981/******************************************************************************
3982* Shifts data bits out to the PHY
3983*
3984* hw - Struct containing variables accessed by shared code
3985* data - Data to send out to the PHY
3986* count - Number of bits to shift out
3987*
3988* Bits are shifted out in MSB to LSB order.
3989******************************************************************************/
3990static void
3991e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
3992{
3993 uint32_t ctrl;
3994 uint32_t mask;
3995
3996 /* We need to shift "count" number of bits out to the PHY. So, the value
wdenk8bde7f72003-06-27 21:31:46 +00003997 * in the "data" parameter will be shifted out to the PHY one bit at a
wdenk682011f2003-06-03 23:54:09 +00003998 * time. In order to do this, "data" must be broken down into bits.
3999 */
4000 mask = 0x01;
4001 mask <<= (count - 1);
4002
4003 ctrl = E1000_READ_REG(hw, CTRL);
4004
4005 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
4006 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
4007
4008 while (mask) {
4009 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
4010 * then raising and lowering the Management Data Clock. A "0" is
4011 * shifted out to the PHY by setting the MDIO bit to "0" and then
4012 * raising and lowering the clock.
4013 */
4014 if (data & mask)
4015 ctrl |= E1000_CTRL_MDIO;
4016 else
4017 ctrl &= ~E1000_CTRL_MDIO;
4018
4019 E1000_WRITE_REG(hw, CTRL, ctrl);
4020 E1000_WRITE_FLUSH(hw);
4021
4022 udelay(2);
4023
4024 e1000_raise_mdi_clk(hw, &ctrl);
4025 e1000_lower_mdi_clk(hw, &ctrl);
4026
4027 mask = mask >> 1;
4028 }
4029}
4030
4031/******************************************************************************
4032* Shifts data bits in from the PHY
4033*
4034* hw - Struct containing variables accessed by shared code
4035*
wdenk8bde7f72003-06-27 21:31:46 +00004036* Bits are shifted in in MSB to LSB order.
wdenk682011f2003-06-03 23:54:09 +00004037******************************************************************************/
4038static uint16_t
4039e1000_shift_in_mdi_bits(struct e1000_hw *hw)
4040{
4041 uint32_t ctrl;
4042 uint16_t data = 0;
4043 uint8_t i;
4044
4045 /* In order to read a register from the PHY, we need to shift in a total
4046 * of 18 bits from the PHY. The first two bit (turnaround) times are used
4047 * to avoid contention on the MDIO pin when a read operation is performed.
4048 * These two bits are ignored by us and thrown away. Bits are "shifted in"
4049 * by raising the input to the Management Data Clock (setting the MDC bit),
4050 * and then reading the value of the MDIO bit.
4051 */
4052 ctrl = E1000_READ_REG(hw, CTRL);
4053
4054 /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
4055 ctrl &= ~E1000_CTRL_MDIO_DIR;
4056 ctrl &= ~E1000_CTRL_MDIO;
4057
4058 E1000_WRITE_REG(hw, CTRL, ctrl);
4059 E1000_WRITE_FLUSH(hw);
4060
4061 /* Raise and Lower the clock before reading in the data. This accounts for
4062 * the turnaround bits. The first clock occurred when we clocked out the
4063 * last bit of the Register Address.
4064 */
4065 e1000_raise_mdi_clk(hw, &ctrl);
4066 e1000_lower_mdi_clk(hw, &ctrl);
4067
4068 for (data = 0, i = 0; i < 16; i++) {
4069 data = data << 1;
4070 e1000_raise_mdi_clk(hw, &ctrl);
4071 ctrl = E1000_READ_REG(hw, CTRL);
4072 /* Check to see if we shifted in a "1". */
4073 if (ctrl & E1000_CTRL_MDIO)
4074 data |= 1;
4075 e1000_lower_mdi_clk(hw, &ctrl);
4076 }
4077
4078 e1000_raise_mdi_clk(hw, &ctrl);
4079 e1000_lower_mdi_clk(hw, &ctrl);
4080
4081 return data;
4082}
4083
4084/*****************************************************************************
4085* Reads the value from a PHY register
4086*
4087* hw - Struct containing variables accessed by shared code
4088* reg_addr - address of the PHY register to read
4089******************************************************************************/
4090static int
4091e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
4092{
4093 uint32_t i;
4094 uint32_t mdic = 0;
4095 const uint32_t phy_addr = 1;
4096
4097 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4098 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4099 return -E1000_ERR_PARAM;
4100 }
4101
4102 if (hw->mac_type > e1000_82543) {
4103 /* Set up Op-code, Phy Address, and register address in the MDI
4104 * Control register. The MAC will take care of interfacing with the
4105 * PHY to retrieve the desired data.
4106 */
4107 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
4108 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4109 (E1000_MDIC_OP_READ));
4110
4111 E1000_WRITE_REG(hw, MDIC, mdic);
4112
4113 /* Poll the ready bit to see if the MDI read completed */
4114 for (i = 0; i < 64; i++) {
4115 udelay(10);
4116 mdic = E1000_READ_REG(hw, MDIC);
4117 if (mdic & E1000_MDIC_READY)
4118 break;
4119 }
4120 if (!(mdic & E1000_MDIC_READY)) {
4121 DEBUGOUT("MDI Read did not complete\n");
4122 return -E1000_ERR_PHY;
4123 }
4124 if (mdic & E1000_MDIC_ERROR) {
4125 DEBUGOUT("MDI Error\n");
4126 return -E1000_ERR_PHY;
4127 }
4128 *phy_data = (uint16_t) mdic;
4129 } else {
4130 /* We must first send a preamble through the MDIO pin to signal the
4131 * beginning of an MII instruction. This is done by sending 32
4132 * consecutive "1" bits.
4133 */
4134 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4135
4136 /* Now combine the next few fields that are required for a read
4137 * operation. We use this method instead of calling the
4138 * e1000_shift_out_mdi_bits routine five different times. The format of
4139 * a MII read instruction consists of a shift out of 14 bits and is
4140 * defined as follows:
4141 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
4142 * followed by a shift in of 18 bits. This first two bits shifted in
4143 * are TurnAround bits used to avoid contention on the MDIO pin when a
4144 * READ operation is performed. These two bits are thrown away
4145 * followed by a shift in of 16 bits which contains the desired data.
4146 */
4147 mdic = ((reg_addr) | (phy_addr << 5) |
4148 (PHY_OP_READ << 10) | (PHY_SOF << 12));
4149
4150 e1000_shift_out_mdi_bits(hw, mdic, 14);
4151
4152 /* Now that we've shifted out the read command to the MII, we need to
4153 * "shift in" the 16-bit value (18 total bits) of the requested PHY
4154 * register address.
4155 */
4156 *phy_data = e1000_shift_in_mdi_bits(hw);
4157 }
4158 return 0;
4159}
4160
4161/******************************************************************************
4162* Writes a value to a PHY register
4163*
4164* hw - Struct containing variables accessed by shared code
4165* reg_addr - address of the PHY register to write
4166* data - data to write to the PHY
4167******************************************************************************/
4168static int
4169e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
4170{
4171 uint32_t i;
4172 uint32_t mdic = 0;
4173 const uint32_t phy_addr = 1;
4174
4175 if (reg_addr > MAX_PHY_REG_ADDRESS) {
4176 DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
4177 return -E1000_ERR_PARAM;
4178 }
4179
4180 if (hw->mac_type > e1000_82543) {
4181 /* Set up Op-code, Phy Address, register address, and data intended
4182 * for the PHY register in the MDI Control register. The MAC will take
4183 * care of interfacing with the PHY to send the desired data.
4184 */
4185 mdic = (((uint32_t) phy_data) |
4186 (reg_addr << E1000_MDIC_REG_SHIFT) |
4187 (phy_addr << E1000_MDIC_PHY_SHIFT) |
4188 (E1000_MDIC_OP_WRITE));
4189
4190 E1000_WRITE_REG(hw, MDIC, mdic);
4191
4192 /* Poll the ready bit to see if the MDI read completed */
4193 for (i = 0; i < 64; i++) {
4194 udelay(10);
4195 mdic = E1000_READ_REG(hw, MDIC);
4196 if (mdic & E1000_MDIC_READY)
4197 break;
4198 }
4199 if (!(mdic & E1000_MDIC_READY)) {
4200 DEBUGOUT("MDI Write did not complete\n");
4201 return -E1000_ERR_PHY;
4202 }
4203 } else {
4204 /* We'll need to use the SW defined pins to shift the write command
4205 * out to the PHY. We first send a preamble to the PHY to signal the
wdenk8bde7f72003-06-27 21:31:46 +00004206 * beginning of the MII instruction. This is done by sending 32
wdenk682011f2003-06-03 23:54:09 +00004207 * consecutive "1" bits.
4208 */
4209 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
4210
wdenk8bde7f72003-06-27 21:31:46 +00004211 /* Now combine the remaining required fields that will indicate a
wdenk682011f2003-06-03 23:54:09 +00004212 * write operation. We use this method instead of calling the
4213 * e1000_shift_out_mdi_bits routine for each field in the command. The
4214 * format of a MII write instruction is as follows:
4215 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
4216 */
4217 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
4218 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
4219 mdic <<= 16;
4220 mdic |= (uint32_t) phy_data;
4221
4222 e1000_shift_out_mdi_bits(hw, mdic, 32);
4223 }
4224 return 0;
4225}
4226
4227/******************************************************************************
Roy Zangaa070782009-07-31 13:34:02 +08004228 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4229 * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
4230 * the caller to figure out how to deal with it.
4231 *
4232 * hw - Struct containing variables accessed by shared code
4233 *
4234 * returns: - E1000_BLK_PHY_RESET
4235 * E1000_SUCCESS
4236 *
4237 *****************************************************************************/
4238int32_t
4239e1000_check_phy_reset_block(struct e1000_hw *hw)
4240{
4241 uint32_t manc = 0;
4242 uint32_t fwsm = 0;
4243
4244 if (hw->mac_type == e1000_ich8lan) {
4245 fwsm = E1000_READ_REG(hw, FWSM);
4246 return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
4247 : E1000_BLK_PHY_RESET;
4248 }
4249
4250 if (hw->mac_type > e1000_82547_rev_2)
4251 manc = E1000_READ_REG(hw, MANC);
4252 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
4253 E1000_BLK_PHY_RESET : E1000_SUCCESS;
4254}
4255
4256/***************************************************************************
4257 * Checks if the PHY configuration is done
4258 *
4259 * hw: Struct containing variables accessed by shared code
4260 *
4261 * returns: - E1000_ERR_RESET if fail to reset MAC
4262 * E1000_SUCCESS at any other case.
4263 *
4264 ***************************************************************************/
4265static int32_t
4266e1000_get_phy_cfg_done(struct e1000_hw *hw)
4267{
4268 int32_t timeout = PHY_CFG_TIMEOUT;
4269 uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
4270
4271 DEBUGFUNC();
4272
4273 switch (hw->mac_type) {
4274 default:
4275 mdelay(10);
4276 break;
Kyle Moffett987b43a2010-09-13 05:52:22 +00004277
Roy Zangaa070782009-07-31 13:34:02 +08004278 case e1000_80003es2lan:
4279 /* Separate *_CFG_DONE_* bit for each port */
Kyle Moffett987b43a2010-09-13 05:52:22 +00004280 if (e1000_is_second_port(hw))
Roy Zangaa070782009-07-31 13:34:02 +08004281 cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
Kyle Moffett987b43a2010-09-13 05:52:22 +00004282 /* Fall Through */
4283
Roy Zangaa070782009-07-31 13:34:02 +08004284 case e1000_82571:
4285 case e1000_82572:
4286 while (timeout) {
4287 if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
4288 break;
4289 else
4290 mdelay(1);
4291 timeout--;
4292 }
4293 if (!timeout) {
4294 DEBUGOUT("MNG configuration cycle has not "
4295 "completed.\n");
4296 return -E1000_ERR_RESET;
4297 }
4298 break;
4299 }
4300
4301 return E1000_SUCCESS;
4302}
4303
4304/******************************************************************************
wdenk682011f2003-06-03 23:54:09 +00004305* Returns the PHY to the power-on reset state
4306*
4307* hw - Struct containing variables accessed by shared code
4308******************************************************************************/
Roy Zangaa070782009-07-31 13:34:02 +08004309int32_t
wdenk682011f2003-06-03 23:54:09 +00004310e1000_phy_hw_reset(struct e1000_hw *hw)
4311{
Kyle Moffett987b43a2010-09-13 05:52:22 +00004312 uint16_t swfw = E1000_SWFW_PHY0_SM;
Roy Zangaa070782009-07-31 13:34:02 +08004313 uint32_t ctrl, ctrl_ext;
4314 uint32_t led_ctrl;
4315 int32_t ret_val;
wdenk682011f2003-06-03 23:54:09 +00004316
4317 DEBUGFUNC();
4318
Roy Zangaa070782009-07-31 13:34:02 +08004319 /* In the case of the phy reset being blocked, it's not an error, we
4320 * simply return success without performing the reset. */
4321 ret_val = e1000_check_phy_reset_block(hw);
4322 if (ret_val)
4323 return E1000_SUCCESS;
4324
wdenk682011f2003-06-03 23:54:09 +00004325 DEBUGOUT("Resetting Phy...\n");
4326
4327 if (hw->mac_type > e1000_82543) {
Kyle Moffett987b43a2010-09-13 05:52:22 +00004328 if (e1000_is_second_port(hw))
Roy Zangaa070782009-07-31 13:34:02 +08004329 swfw = E1000_SWFW_PHY1_SM;
Kyle Moffett987b43a2010-09-13 05:52:22 +00004330
Roy Zangaa070782009-07-31 13:34:02 +08004331 if (e1000_swfw_sync_acquire(hw, swfw)) {
4332 DEBUGOUT("Unable to acquire swfw sync\n");
4333 return -E1000_ERR_SWFW_SYNC;
4334 }
Kyle Moffett987b43a2010-09-13 05:52:22 +00004335
wdenk682011f2003-06-03 23:54:09 +00004336 /* Read the device control register and assert the E1000_CTRL_PHY_RST
4337 * bit. Then, take it out of reset.
4338 */
4339 ctrl = E1000_READ_REG(hw, CTRL);
4340 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
4341 E1000_WRITE_FLUSH(hw);
Roy Zangaa070782009-07-31 13:34:02 +08004342
4343 if (hw->mac_type < e1000_82571)
4344 udelay(10);
4345 else
4346 udelay(100);
4347
wdenk682011f2003-06-03 23:54:09 +00004348 E1000_WRITE_REG(hw, CTRL, ctrl);
4349 E1000_WRITE_FLUSH(hw);
Roy Zangaa070782009-07-31 13:34:02 +08004350
4351 if (hw->mac_type >= e1000_82571)
4352 mdelay(10);
4353
wdenk682011f2003-06-03 23:54:09 +00004354 } else {
4355 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
4356 * bit to put the PHY into reset. Then, take it out of reset.
4357 */
4358 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4359 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
4360 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
4361 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4362 E1000_WRITE_FLUSH(hw);
4363 mdelay(10);
4364 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
4365 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4366 E1000_WRITE_FLUSH(hw);
4367 }
4368 udelay(150);
Roy Zangaa070782009-07-31 13:34:02 +08004369
4370 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
4371 /* Configure activity LED after PHY reset */
4372 led_ctrl = E1000_READ_REG(hw, LEDCTL);
4373 led_ctrl &= IGP_ACTIVITY_LED_MASK;
4374 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
4375 E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
4376 }
4377
4378 /* Wait for FW to finish PHY configuration. */
4379 ret_val = e1000_get_phy_cfg_done(hw);
4380 if (ret_val != E1000_SUCCESS)
4381 return ret_val;
4382
4383 return ret_val;
4384}
4385
4386/******************************************************************************
4387 * IGP phy init script - initializes the GbE PHY
4388 *
4389 * hw - Struct containing variables accessed by shared code
4390 *****************************************************************************/
4391static void
4392e1000_phy_init_script(struct e1000_hw *hw)
4393{
4394 uint32_t ret_val;
4395 uint16_t phy_saved_data;
4396 DEBUGFUNC();
4397
4398 if (hw->phy_init_script) {
4399 mdelay(20);
4400
4401 /* Save off the current value of register 0x2F5B to be
4402 * restored at the end of this routine. */
4403 ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
4404
4405 /* Disabled the PHY transmitter */
4406 e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
4407
4408 mdelay(20);
4409
4410 e1000_write_phy_reg(hw, 0x0000, 0x0140);
4411
4412 mdelay(5);
4413
4414 switch (hw->mac_type) {
4415 case e1000_82541:
4416 case e1000_82547:
4417 e1000_write_phy_reg(hw, 0x1F95, 0x0001);
4418
4419 e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
4420
4421 e1000_write_phy_reg(hw, 0x1F79, 0x0018);
4422
4423 e1000_write_phy_reg(hw, 0x1F30, 0x1600);
4424
4425 e1000_write_phy_reg(hw, 0x1F31, 0x0014);
4426
4427 e1000_write_phy_reg(hw, 0x1F32, 0x161C);
4428
4429 e1000_write_phy_reg(hw, 0x1F94, 0x0003);
4430
4431 e1000_write_phy_reg(hw, 0x1F96, 0x003F);
4432
4433 e1000_write_phy_reg(hw, 0x2010, 0x0008);
4434 break;
4435
4436 case e1000_82541_rev_2:
4437 case e1000_82547_rev_2:
4438 e1000_write_phy_reg(hw, 0x1F73, 0x0099);
4439 break;
4440 default:
4441 break;
4442 }
4443
4444 e1000_write_phy_reg(hw, 0x0000, 0x3300);
4445
4446 mdelay(20);
4447
4448 /* Now enable the transmitter */
Zang Roy-R6191156b13b12011-11-06 22:22:36 +00004449 if (!ret_val)
4450 e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
Roy Zangaa070782009-07-31 13:34:02 +08004451
4452 if (hw->mac_type == e1000_82547) {
4453 uint16_t fused, fine, coarse;
4454
4455 /* Move to analog registers page */
4456 e1000_read_phy_reg(hw,
4457 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
4458
4459 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
4460 e1000_read_phy_reg(hw,
4461 IGP01E1000_ANALOG_FUSE_STATUS, &fused);
4462
4463 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
4464 coarse = fused
4465 & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
4466
4467 if (coarse >
4468 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
4469 coarse -=
4470 IGP01E1000_ANALOG_FUSE_COARSE_10;
4471 fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
4472 } else if (coarse
4473 == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
4474 fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
4475
4476 fused = (fused
4477 & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
4478 (fine
4479 & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
4480 (coarse
4481 & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
4482
4483 e1000_write_phy_reg(hw,
4484 IGP01E1000_ANALOG_FUSE_CONTROL, fused);
4485 e1000_write_phy_reg(hw,
4486 IGP01E1000_ANALOG_FUSE_BYPASS,
4487 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
4488 }
4489 }
4490 }
wdenk682011f2003-06-03 23:54:09 +00004491}
4492
4493/******************************************************************************
4494* Resets the PHY
4495*
4496* hw - Struct containing variables accessed by shared code
4497*
Roy Zangaa070782009-07-31 13:34:02 +08004498* Sets bit 15 of the MII Control register
wdenk682011f2003-06-03 23:54:09 +00004499******************************************************************************/
Roy Zangaa070782009-07-31 13:34:02 +08004500int32_t
wdenk682011f2003-06-03 23:54:09 +00004501e1000_phy_reset(struct e1000_hw *hw)
4502{
Roy Zangaa070782009-07-31 13:34:02 +08004503 int32_t ret_val;
wdenk682011f2003-06-03 23:54:09 +00004504 uint16_t phy_data;
4505
4506 DEBUGFUNC();
4507
Roy Zangaa070782009-07-31 13:34:02 +08004508 /* In the case of the phy reset being blocked, it's not an error, we
4509 * simply return success without performing the reset. */
4510 ret_val = e1000_check_phy_reset_block(hw);
4511 if (ret_val)
4512 return E1000_SUCCESS;
4513
4514 switch (hw->phy_type) {
4515 case e1000_phy_igp:
4516 case e1000_phy_igp_2:
4517 case e1000_phy_igp_3:
4518 case e1000_phy_ife:
4519 ret_val = e1000_phy_hw_reset(hw);
4520 if (ret_val)
4521 return ret_val;
4522 break;
4523 default:
4524 ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
4525 if (ret_val)
4526 return ret_val;
4527
4528 phy_data |= MII_CR_RESET;
4529 ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
4530 if (ret_val)
4531 return ret_val;
4532
4533 udelay(1);
4534 break;
wdenk682011f2003-06-03 23:54:09 +00004535 }
Roy Zangaa070782009-07-31 13:34:02 +08004536
4537 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
4538 e1000_phy_init_script(hw);
4539
4540 return E1000_SUCCESS;
wdenk682011f2003-06-03 23:54:09 +00004541}
4542
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07004543static int e1000_set_phy_type (struct e1000_hw *hw)
Andre Schwarzac3315c2008-03-06 16:45:44 +01004544{
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07004545 DEBUGFUNC ();
Andre Schwarzac3315c2008-03-06 16:45:44 +01004546
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07004547 if (hw->mac_type == e1000_undefined)
4548 return -E1000_ERR_PHY_TYPE;
Andre Schwarzac3315c2008-03-06 16:45:44 +01004549
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07004550 switch (hw->phy_id) {
4551 case M88E1000_E_PHY_ID:
4552 case M88E1000_I_PHY_ID:
4553 case M88E1011_I_PHY_ID:
Roy Zangaa070782009-07-31 13:34:02 +08004554 case M88E1111_I_PHY_ID:
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07004555 hw->phy_type = e1000_phy_m88;
4556 break;
4557 case IGP01E1000_I_PHY_ID:
4558 if (hw->mac_type == e1000_82541 ||
Roy Zangaa070782009-07-31 13:34:02 +08004559 hw->mac_type == e1000_82541_rev_2 ||
4560 hw->mac_type == e1000_82547 ||
4561 hw->mac_type == e1000_82547_rev_2) {
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07004562 hw->phy_type = e1000_phy_igp;
Roy Zangaa070782009-07-31 13:34:02 +08004563 hw->phy_type = e1000_phy_igp;
4564 break;
4565 }
4566 case IGP03E1000_E_PHY_ID:
4567 hw->phy_type = e1000_phy_igp_3;
4568 break;
4569 case IFE_E_PHY_ID:
4570 case IFE_PLUS_E_PHY_ID:
4571 case IFE_C_E_PHY_ID:
4572 hw->phy_type = e1000_phy_ife;
4573 break;
4574 case GG82563_E_PHY_ID:
4575 if (hw->mac_type == e1000_80003es2lan) {
4576 hw->phy_type = e1000_phy_gg82563;
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07004577 break;
4578 }
Roy Zang2c2668f2011-01-21 11:29:38 +08004579 case BME1000_E_PHY_ID:
4580 hw->phy_type = e1000_phy_bm;
4581 break;
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07004582 /* Fall Through */
4583 default:
4584 /* Should never have loaded on this device */
4585 hw->phy_type = e1000_phy_undefined;
4586 return -E1000_ERR_PHY_TYPE;
4587 }
Andre Schwarzac3315c2008-03-06 16:45:44 +01004588
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07004589 return E1000_SUCCESS;
Andre Schwarzac3315c2008-03-06 16:45:44 +01004590}
4591
wdenk682011f2003-06-03 23:54:09 +00004592/******************************************************************************
4593* Probes the expected PHY address for known PHY IDs
4594*
4595* hw - Struct containing variables accessed by shared code
4596******************************************************************************/
Roy Zangaa070782009-07-31 13:34:02 +08004597static int32_t
wdenk682011f2003-06-03 23:54:09 +00004598e1000_detect_gig_phy(struct e1000_hw *hw)
4599{
Roy Zangaa070782009-07-31 13:34:02 +08004600 int32_t phy_init_status, ret_val;
wdenk682011f2003-06-03 23:54:09 +00004601 uint16_t phy_id_high, phy_id_low;
Roy Zangaa070782009-07-31 13:34:02 +08004602 boolean_t match = FALSE;
wdenk682011f2003-06-03 23:54:09 +00004603
4604 DEBUGFUNC();
4605
Roy Zangaa070782009-07-31 13:34:02 +08004606 /* The 82571 firmware may still be configuring the PHY. In this
4607 * case, we cannot access the PHY until the configuration is done. So
4608 * we explicitly set the PHY values. */
4609 if (hw->mac_type == e1000_82571 ||
4610 hw->mac_type == e1000_82572) {
4611 hw->phy_id = IGP01E1000_I_PHY_ID;
4612 hw->phy_type = e1000_phy_igp_2;
4613 return E1000_SUCCESS;
4614 }
4615
4616 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
4617 * work- around that forces PHY page 0 to be set or the reads fail.
4618 * The rest of the code in this routine uses e1000_read_phy_reg to
4619 * read the PHY ID. So for ESB-2 we need to have this set so our
4620 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
4621 * the routines below will figure this out as well. */
4622 if (hw->mac_type == e1000_80003es2lan)
4623 hw->phy_type = e1000_phy_gg82563;
4624
wdenk682011f2003-06-03 23:54:09 +00004625 /* Read the PHY ID Registers to identify which PHY is onboard. */
Roy Zangaa070782009-07-31 13:34:02 +08004626 ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4627 if (ret_val)
4628 return ret_val;
4629
wdenk682011f2003-06-03 23:54:09 +00004630 hw->phy_id = (uint32_t) (phy_id_high << 16);
Roy Zangaa070782009-07-31 13:34:02 +08004631 udelay(20);
4632 ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4633 if (ret_val)
4634 return ret_val;
4635
wdenk682011f2003-06-03 23:54:09 +00004636 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
Roy Zangaa070782009-07-31 13:34:02 +08004637 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
wdenk682011f2003-06-03 23:54:09 +00004638
4639 switch (hw->mac_type) {
4640 case e1000_82543:
4641 if (hw->phy_id == M88E1000_E_PHY_ID)
4642 match = TRUE;
4643 break;
4644 case e1000_82544:
4645 if (hw->phy_id == M88E1000_I_PHY_ID)
4646 match = TRUE;
4647 break;
4648 case e1000_82540:
4649 case e1000_82545:
Roy Zangaa070782009-07-31 13:34:02 +08004650 case e1000_82545_rev_3:
wdenk682011f2003-06-03 23:54:09 +00004651 case e1000_82546:
Roy Zangaa070782009-07-31 13:34:02 +08004652 case e1000_82546_rev_3:
wdenk682011f2003-06-03 23:54:09 +00004653 if (hw->phy_id == M88E1011_I_PHY_ID)
4654 match = TRUE;
4655 break;
Roy Zangaa070782009-07-31 13:34:02 +08004656 case e1000_82541:
Andre Schwarzac3315c2008-03-06 16:45:44 +01004657 case e1000_82541_rev_2:
Roy Zangaa070782009-07-31 13:34:02 +08004658 case e1000_82547:
4659 case e1000_82547_rev_2:
Andre Schwarzac3315c2008-03-06 16:45:44 +01004660 if(hw->phy_id == IGP01E1000_I_PHY_ID)
4661 match = TRUE;
4662
4663 break;
Roy Zangaa070782009-07-31 13:34:02 +08004664 case e1000_82573:
4665 if (hw->phy_id == M88E1111_I_PHY_ID)
4666 match = TRUE;
4667 break;
Roy Zang2c2668f2011-01-21 11:29:38 +08004668 case e1000_82574:
4669 if (hw->phy_id == BME1000_E_PHY_ID)
4670 match = TRUE;
4671 break;
Roy Zangaa070782009-07-31 13:34:02 +08004672 case e1000_80003es2lan:
4673 if (hw->phy_id == GG82563_E_PHY_ID)
4674 match = TRUE;
4675 break;
4676 case e1000_ich8lan:
4677 if (hw->phy_id == IGP03E1000_E_PHY_ID)
4678 match = TRUE;
4679 if (hw->phy_id == IFE_E_PHY_ID)
4680 match = TRUE;
4681 if (hw->phy_id == IFE_PLUS_E_PHY_ID)
4682 match = TRUE;
4683 if (hw->phy_id == IFE_C_E_PHY_ID)
4684 match = TRUE;
4685 break;
wdenk682011f2003-06-03 23:54:09 +00004686 default:
4687 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
4688 return -E1000_ERR_CONFIG;
4689 }
Andre Schwarzac3315c2008-03-06 16:45:44 +01004690
4691 phy_init_status = e1000_set_phy_type(hw);
4692
4693 if ((match) && (phy_init_status == E1000_SUCCESS)) {
wdenk682011f2003-06-03 23:54:09 +00004694 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
4695 return 0;
4696 }
4697 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
4698 return -E1000_ERR_PHY;
4699}
4700
Roy Zangaa070782009-07-31 13:34:02 +08004701/*****************************************************************************
4702 * Set media type and TBI compatibility.
4703 *
4704 * hw - Struct containing variables accessed by shared code
4705 * **************************************************************************/
4706void
4707e1000_set_media_type(struct e1000_hw *hw)
4708{
4709 uint32_t status;
4710
4711 DEBUGFUNC();
4712
4713 if (hw->mac_type != e1000_82543) {
4714 /* tbi_compatibility is only valid on 82543 */
4715 hw->tbi_compatibility_en = FALSE;
4716 }
4717
4718 switch (hw->device_id) {
4719 case E1000_DEV_ID_82545GM_SERDES:
4720 case E1000_DEV_ID_82546GB_SERDES:
4721 case E1000_DEV_ID_82571EB_SERDES:
4722 case E1000_DEV_ID_82571EB_SERDES_DUAL:
4723 case E1000_DEV_ID_82571EB_SERDES_QUAD:
4724 case E1000_DEV_ID_82572EI_SERDES:
4725 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
4726 hw->media_type = e1000_media_type_internal_serdes;
4727 break;
4728 default:
4729 switch (hw->mac_type) {
4730 case e1000_82542_rev2_0:
4731 case e1000_82542_rev2_1:
4732 hw->media_type = e1000_media_type_fiber;
4733 break;
4734 case e1000_ich8lan:
4735 case e1000_82573:
Roy Zang2c2668f2011-01-21 11:29:38 +08004736 case e1000_82574:
Roy Zangaa070782009-07-31 13:34:02 +08004737 /* The STATUS_TBIMODE bit is reserved or reused
4738 * for the this device.
4739 */
4740 hw->media_type = e1000_media_type_copper;
4741 break;
4742 default:
4743 status = E1000_READ_REG(hw, STATUS);
4744 if (status & E1000_STATUS_TBIMODE) {
4745 hw->media_type = e1000_media_type_fiber;
4746 /* tbi_compatibility not valid on fiber */
4747 hw->tbi_compatibility_en = FALSE;
4748 } else {
4749 hw->media_type = e1000_media_type_copper;
4750 }
4751 break;
4752 }
4753 }
4754}
4755
wdenk682011f2003-06-03 23:54:09 +00004756/**
4757 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4758 *
4759 * e1000_sw_init initializes the Adapter private data structure.
4760 * Fields are initialized based on PCI device information and
4761 * OS network device settings (MTU size).
4762 **/
4763
4764static int
Kyle Moffettd60626f82011-10-18 11:05:26 +00004765e1000_sw_init(struct eth_device *nic)
wdenk682011f2003-06-03 23:54:09 +00004766{
4767 struct e1000_hw *hw = (typeof(hw)) nic->priv;
4768 int result;
4769
4770 /* PCI config space info */
4771 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
4772 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
4773 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
4774 &hw->subsystem_vendor_id);
4775 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
4776
4777 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
4778 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
4779
4780 /* identify the MAC */
4781 result = e1000_set_mac_type(hw);
4782 if (result) {
Kyle Moffettd60626f82011-10-18 11:05:26 +00004783 E1000_ERR(hw->nic, "Unknown MAC Type\n");
wdenk682011f2003-06-03 23:54:09 +00004784 return result;
4785 }
4786
Roy Zangaa070782009-07-31 13:34:02 +08004787 switch (hw->mac_type) {
4788 default:
4789 break;
4790 case e1000_82541:
4791 case e1000_82547:
4792 case e1000_82541_rev_2:
4793 case e1000_82547_rev_2:
4794 hw->phy_init_script = 1;
4795 break;
4796 }
4797
wdenk682011f2003-06-03 23:54:09 +00004798 /* flow control settings */
4799 hw->fc_high_water = E1000_FC_HIGH_THRESH;
4800 hw->fc_low_water = E1000_FC_LOW_THRESH;
4801 hw->fc_pause_time = E1000_FC_PAUSE_TIME;
4802 hw->fc_send_xon = 1;
4803
4804 /* Media type - copper or fiber */
Roy Zangaa070782009-07-31 13:34:02 +08004805 e1000_set_media_type(hw);
wdenk682011f2003-06-03 23:54:09 +00004806
4807 if (hw->mac_type >= e1000_82543) {
4808 uint32_t status = E1000_READ_REG(hw, STATUS);
4809
4810 if (status & E1000_STATUS_TBIMODE) {
4811 DEBUGOUT("fiber interface\n");
4812 hw->media_type = e1000_media_type_fiber;
4813 } else {
4814 DEBUGOUT("copper interface\n");
4815 hw->media_type = e1000_media_type_copper;
4816 }
4817 } else {
4818 hw->media_type = e1000_media_type_fiber;
4819 }
4820
Roy Zangaa070782009-07-31 13:34:02 +08004821 hw->tbi_compatibility_en = TRUE;
4822 hw->wait_autoneg_complete = TRUE;
wdenk682011f2003-06-03 23:54:09 +00004823 if (hw->mac_type < e1000_82543)
4824 hw->report_tx_early = 0;
4825 else
4826 hw->report_tx_early = 1;
4827
wdenk682011f2003-06-03 23:54:09 +00004828 return E1000_SUCCESS;
4829}
4830
4831void
4832fill_rx(struct e1000_hw *hw)
4833{
4834 struct e1000_rx_desc *rd;
4835
4836 rx_last = rx_tail;
4837 rd = rx_base + rx_tail;
4838 rx_tail = (rx_tail + 1) % 8;
4839 memset(rd, 0, 16);
4840 rd->buffer_addr = cpu_to_le64((u32) & packet);
4841 E1000_WRITE_REG(hw, RDT, rx_tail);
4842}
4843
4844/**
4845 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
4846 * @adapter: board private structure
4847 *
4848 * Configure the Tx unit of the MAC after a reset.
4849 **/
4850
4851static void
4852e1000_configure_tx(struct e1000_hw *hw)
4853{
4854 unsigned long ptr;
4855 unsigned long tctl;
Roy Zangaa070782009-07-31 13:34:02 +08004856 unsigned long tipg, tarc;
4857 uint32_t ipgr1, ipgr2;
wdenk682011f2003-06-03 23:54:09 +00004858
4859 ptr = (u32) tx_pool;
4860 if (ptr & 0xf)
4861 ptr = (ptr + 0x10) & (~0xf);
4862
4863 tx_base = (typeof(tx_base)) ptr;
4864
4865 E1000_WRITE_REG(hw, TDBAL, (u32) tx_base);
4866 E1000_WRITE_REG(hw, TDBAH, 0);
4867
4868 E1000_WRITE_REG(hw, TDLEN, 128);
4869
4870 /* Setup the HW Tx Head and Tail descriptor pointers */
4871 E1000_WRITE_REG(hw, TDH, 0);
4872 E1000_WRITE_REG(hw, TDT, 0);
4873 tx_tail = 0;
4874
4875 /* Set the default values for the Tx Inter Packet Gap timer */
Roy Zangaa070782009-07-31 13:34:02 +08004876 if (hw->mac_type <= e1000_82547_rev_2 &&
4877 (hw->media_type == e1000_media_type_fiber ||
4878 hw->media_type == e1000_media_type_internal_serdes))
4879 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
4880 else
4881 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
4882
4883 /* Set the default values for the Tx Inter Packet Gap timer */
wdenk682011f2003-06-03 23:54:09 +00004884 switch (hw->mac_type) {
4885 case e1000_82542_rev2_0:
4886 case e1000_82542_rev2_1:
4887 tipg = DEFAULT_82542_TIPG_IPGT;
Roy Zangaa070782009-07-31 13:34:02 +08004888 ipgr1 = DEFAULT_82542_TIPG_IPGR1;
4889 ipgr2 = DEFAULT_82542_TIPG_IPGR2;
4890 break;
4891 case e1000_80003es2lan:
4892 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4893 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
wdenk682011f2003-06-03 23:54:09 +00004894 break;
4895 default:
Roy Zangaa070782009-07-31 13:34:02 +08004896 ipgr1 = DEFAULT_82543_TIPG_IPGR1;
4897 ipgr2 = DEFAULT_82543_TIPG_IPGR2;
4898 break;
wdenk682011f2003-06-03 23:54:09 +00004899 }
Roy Zangaa070782009-07-31 13:34:02 +08004900 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
4901 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
wdenk682011f2003-06-03 23:54:09 +00004902 E1000_WRITE_REG(hw, TIPG, tipg);
wdenk682011f2003-06-03 23:54:09 +00004903 /* Program the Transmit Control Register */
4904 tctl = E1000_READ_REG(hw, TCTL);
4905 tctl &= ~E1000_TCTL_CT;
4906 tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
4907 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
Roy Zangaa070782009-07-31 13:34:02 +08004908
4909 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
4910 tarc = E1000_READ_REG(hw, TARC0);
4911 /* set the speed mode bit, we'll clear it if we're not at
4912 * gigabit link later */
4913 /* git bit can be set to 1*/
4914 } else if (hw->mac_type == e1000_80003es2lan) {
4915 tarc = E1000_READ_REG(hw, TARC0);
4916 tarc |= 1;
4917 E1000_WRITE_REG(hw, TARC0, tarc);
4918 tarc = E1000_READ_REG(hw, TARC1);
4919 tarc |= 1;
4920 E1000_WRITE_REG(hw, TARC1, tarc);
4921 }
4922
wdenk682011f2003-06-03 23:54:09 +00004923
4924 e1000_config_collision_dist(hw);
Roy Zangaa070782009-07-31 13:34:02 +08004925 /* Setup Transmit Descriptor Settings for eop descriptor */
4926 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
wdenk682011f2003-06-03 23:54:09 +00004927
Roy Zangaa070782009-07-31 13:34:02 +08004928 /* Need to set up RS bit */
4929 if (hw->mac_type < e1000_82543)
4930 hw->txd_cmd |= E1000_TXD_CMD_RPS;
wdenk682011f2003-06-03 23:54:09 +00004931 else
Roy Zangaa070782009-07-31 13:34:02 +08004932 hw->txd_cmd |= E1000_TXD_CMD_RS;
4933 E1000_WRITE_REG(hw, TCTL, tctl);
wdenk682011f2003-06-03 23:54:09 +00004934}
4935
4936/**
4937 * e1000_setup_rctl - configure the receive control register
4938 * @adapter: Board private structure
4939 **/
4940static void
4941e1000_setup_rctl(struct e1000_hw *hw)
4942{
4943 uint32_t rctl;
4944
4945 rctl = E1000_READ_REG(hw, RCTL);
4946
4947 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
4948
Roy Zangaa070782009-07-31 13:34:02 +08004949 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
4950 | E1000_RCTL_RDMTS_HALF; /* |
4951 (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
wdenk682011f2003-06-03 23:54:09 +00004952
4953 if (hw->tbi_compatibility_on == 1)
4954 rctl |= E1000_RCTL_SBP;
4955 else
4956 rctl &= ~E1000_RCTL_SBP;
4957
4958 rctl &= ~(E1000_RCTL_SZ_4096);
wdenk682011f2003-06-03 23:54:09 +00004959 rctl |= E1000_RCTL_SZ_2048;
4960 rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
wdenk682011f2003-06-03 23:54:09 +00004961 E1000_WRITE_REG(hw, RCTL, rctl);
4962}
4963
4964/**
4965 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
4966 * @adapter: board private structure
4967 *
4968 * Configure the Rx unit of the MAC after a reset.
4969 **/
4970static void
4971e1000_configure_rx(struct e1000_hw *hw)
4972{
4973 unsigned long ptr;
Roy Zangaa070782009-07-31 13:34:02 +08004974 unsigned long rctl, ctrl_ext;
wdenk682011f2003-06-03 23:54:09 +00004975 rx_tail = 0;
4976 /* make sure receives are disabled while setting up the descriptors */
4977 rctl = E1000_READ_REG(hw, RCTL);
4978 E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
wdenk682011f2003-06-03 23:54:09 +00004979 if (hw->mac_type >= e1000_82540) {
wdenk682011f2003-06-03 23:54:09 +00004980 /* Set the interrupt throttling rate. Value is calculated
4981 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -07004982#define MAX_INTS_PER_SEC 8000
4983#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
wdenk682011f2003-06-03 23:54:09 +00004984 E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
4985 }
4986
Roy Zangaa070782009-07-31 13:34:02 +08004987 if (hw->mac_type >= e1000_82571) {
4988 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
4989 /* Reset delay timers after every interrupt */
4990 ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
4991 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
4992 E1000_WRITE_FLUSH(hw);
4993 }
wdenk682011f2003-06-03 23:54:09 +00004994 /* Setup the Base and Length of the Rx Descriptor Ring */
4995 ptr = (u32) rx_pool;
4996 if (ptr & 0xf)
4997 ptr = (ptr + 0x10) & (~0xf);
4998 rx_base = (typeof(rx_base)) ptr;
4999 E1000_WRITE_REG(hw, RDBAL, (u32) rx_base);
5000 E1000_WRITE_REG(hw, RDBAH, 0);
5001
5002 E1000_WRITE_REG(hw, RDLEN, 128);
5003
5004 /* Setup the HW Rx Head and Tail Descriptor Pointers */
5005 E1000_WRITE_REG(hw, RDH, 0);
5006 E1000_WRITE_REG(hw, RDT, 0);
wdenk682011f2003-06-03 23:54:09 +00005007 /* Enable Receives */
5008
5009 E1000_WRITE_REG(hw, RCTL, rctl);
5010 fill_rx(hw);
5011}
5012
5013/**************************************************************************
5014POLL - Wait for a frame
5015***************************************************************************/
5016static int
5017e1000_poll(struct eth_device *nic)
5018{
5019 struct e1000_hw *hw = nic->priv;
5020 struct e1000_rx_desc *rd;
5021 /* return true if there's an ethernet packet ready to read */
5022 rd = rx_base + rx_last;
5023 if (!(le32_to_cpu(rd->status)) & E1000_RXD_STAT_DD)
5024 return 0;
5025 /*DEBUGOUT("recv: packet len=%d \n", rd->length); */
Wolfgang Denk77ddac92005-10-13 16:45:02 +02005026 NetReceive((uchar *)packet, le32_to_cpu(rd->length));
wdenk682011f2003-06-03 23:54:09 +00005027 fill_rx(hw);
5028 return 1;
5029}
5030
5031/**************************************************************************
5032TRANSMIT - Transmit a frame
5033***************************************************************************/
Joe Hershberger97796f72012-05-22 07:56:14 +00005034static int e1000_transmit(struct eth_device *nic, void *packet, int length)
wdenk682011f2003-06-03 23:54:09 +00005035{
Joe Hershberger97796f72012-05-22 07:56:14 +00005036 void *nv_packet = (void *)packet;
wdenk682011f2003-06-03 23:54:09 +00005037 struct e1000_hw *hw = nic->priv;
5038 struct e1000_tx_desc *txp;
5039 int i = 0;
5040
5041 txp = tx_base + tx_tail;
5042 tx_tail = (tx_tail + 1) % 8;
5043
Wolfgang Denk8aa858c2010-11-22 09:48:45 +01005044 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
Roy Zangaa070782009-07-31 13:34:02 +08005045 txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
wdenk682011f2003-06-03 23:54:09 +00005046 txp->upper.data = 0;
5047 E1000_WRITE_REG(hw, TDT, tx_tail);
5048
Roy Zangaa070782009-07-31 13:34:02 +08005049 E1000_WRITE_FLUSH(hw);
wdenk682011f2003-06-03 23:54:09 +00005050 while (!(le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)) {
5051 if (i++ > TOUT_LOOP) {
5052 DEBUGOUT("e1000: tx timeout\n");
5053 return 0;
5054 }
5055 udelay(10); /* give the nic a chance to write to the register */
5056 }
5057 return 1;
5058}
5059
5060/*reset function*/
5061static inline int
5062e1000_reset(struct eth_device *nic)
5063{
5064 struct e1000_hw *hw = nic->priv;
5065
5066 e1000_reset_hw(hw);
5067 if (hw->mac_type >= e1000_82544) {
5068 E1000_WRITE_REG(hw, WUC, 0);
5069 }
5070 return e1000_init_hw(nic);
5071}
5072
5073/**************************************************************************
5074DISABLE - Turn off ethernet interface
5075***************************************************************************/
5076static void
5077e1000_disable(struct eth_device *nic)
5078{
5079 struct e1000_hw *hw = nic->priv;
5080
5081 /* Turn off the ethernet interface */
5082 E1000_WRITE_REG(hw, RCTL, 0);
5083 E1000_WRITE_REG(hw, TCTL, 0);
5084
5085 /* Clear the transmit ring */
5086 E1000_WRITE_REG(hw, TDH, 0);
5087 E1000_WRITE_REG(hw, TDT, 0);
5088
5089 /* Clear the receive ring */
5090 E1000_WRITE_REG(hw, RDH, 0);
5091 E1000_WRITE_REG(hw, RDT, 0);
5092
5093 /* put the card in its initial state */
5094#if 0
5095 E1000_WRITE_REG(hw, CTRL, E1000_CTRL_RST);
5096#endif
5097 mdelay(10);
5098
5099}
5100
5101/**************************************************************************
5102INIT - set up ethernet interface(s)
5103***************************************************************************/
5104static int
5105e1000_init(struct eth_device *nic, bd_t * bis)
5106{
5107 struct e1000_hw *hw = nic->priv;
5108 int ret_val = 0;
5109
5110 ret_val = e1000_reset(nic);
5111 if (ret_val < 0) {
5112 if ((ret_val == -E1000_ERR_NOLINK) ||
5113 (ret_val == -E1000_ERR_TIMEOUT)) {
Kyle Moffettd60626f82011-10-18 11:05:26 +00005114 E1000_ERR(hw->nic, "Valid Link not detected\n");
wdenk682011f2003-06-03 23:54:09 +00005115 } else {
Kyle Moffettd60626f82011-10-18 11:05:26 +00005116 E1000_ERR(hw->nic, "Hardware Initialization Failed\n");
wdenk682011f2003-06-03 23:54:09 +00005117 }
5118 return 0;
5119 }
5120 e1000_configure_tx(hw);
5121 e1000_setup_rctl(hw);
5122 e1000_configure_rx(hw);
5123 return 1;
5124}
5125
Roy Zangaa070782009-07-31 13:34:02 +08005126/******************************************************************************
5127 * Gets the current PCI bus type of hardware
5128 *
5129 * hw - Struct containing variables accessed by shared code
5130 *****************************************************************************/
5131void e1000_get_bus_type(struct e1000_hw *hw)
5132{
5133 uint32_t status;
5134
5135 switch (hw->mac_type) {
5136 case e1000_82542_rev2_0:
5137 case e1000_82542_rev2_1:
5138 hw->bus_type = e1000_bus_type_pci;
5139 break;
5140 case e1000_82571:
5141 case e1000_82572:
5142 case e1000_82573:
Roy Zang2c2668f2011-01-21 11:29:38 +08005143 case e1000_82574:
Roy Zangaa070782009-07-31 13:34:02 +08005144 case e1000_80003es2lan:
5145 hw->bus_type = e1000_bus_type_pci_express;
5146 break;
5147 case e1000_ich8lan:
5148 hw->bus_type = e1000_bus_type_pci_express;
5149 break;
5150 default:
5151 status = E1000_READ_REG(hw, STATUS);
5152 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
5153 e1000_bus_type_pcix : e1000_bus_type_pci;
5154 break;
5155 }
5156}
5157
Kyle Moffettce5207e2011-10-18 11:05:29 +00005158/* A list of all registered e1000 devices */
5159static LIST_HEAD(e1000_hw_list);
5160
wdenk682011f2003-06-03 23:54:09 +00005161/**************************************************************************
5162PROBE - Look for an adapter, this routine's visible to the outside
5163You should omit the last argument struct pci_device * for a non-PCI NIC
5164***************************************************************************/
5165int
5166e1000_initialize(bd_t * bis)
5167{
Kyle Moffettd60626f82011-10-18 11:05:26 +00005168 unsigned int i;
wdenk682011f2003-06-03 23:54:09 +00005169 pci_dev_t devno;
wdenk682011f2003-06-03 23:54:09 +00005170
Timur Tabif81ecb52009-08-17 15:55:38 -05005171 DEBUGFUNC();
5172
Kyle Moffettd60626f82011-10-18 11:05:26 +00005173 /* Find and probe all the matching PCI devices */
5174 for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
5175 u32 val;
wdenk682011f2003-06-03 23:54:09 +00005176
Kyle Moffettd60626f82011-10-18 11:05:26 +00005177 /*
5178 * These will never get freed due to errors, this allows us to
5179 * perform SPI EEPROM programming from U-boot, for example.
5180 */
5181 struct eth_device *nic = malloc(sizeof(*nic));
5182 struct e1000_hw *hw = malloc(sizeof(*hw));
5183 if (!nic || !hw) {
5184 printf("e1000#%u: Out of Memory!\n", i);
Kumar Gala4b29bdb2010-11-12 04:13:06 -06005185 free(nic);
Kyle Moffettd60626f82011-10-18 11:05:26 +00005186 free(hw);
5187 continue;
Kumar Gala4b29bdb2010-11-12 04:13:06 -06005188 }
5189
Kyle Moffettd60626f82011-10-18 11:05:26 +00005190 /* Make sure all of the fields are initially zeroed */
Matthew McClintockf7ac99f2010-11-15 18:02:53 -06005191 memset(nic, 0, sizeof(*nic));
Kumar Gala4b29bdb2010-11-12 04:13:06 -06005192 memset(hw, 0, sizeof(*hw));
5193
Kyle Moffettd60626f82011-10-18 11:05:26 +00005194 /* Assign the passed-in values */
5195 hw->cardnum = i;
wdenk682011f2003-06-03 23:54:09 +00005196 hw->pdev = devno;
Kyle Moffettd60626f82011-10-18 11:05:26 +00005197 hw->nic = nic;
wdenk682011f2003-06-03 23:54:09 +00005198 nic->priv = hw;
wdenk682011f2003-06-03 23:54:09 +00005199
Kyle Moffettd60626f82011-10-18 11:05:26 +00005200 /* Generate a card name */
5201 sprintf(nic->name, "e1000#%u", hw->cardnum);
5202
5203 /* Print a debug message with the IO base address */
5204 pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
5205 E1000_DBG(nic, "iobase 0x%08x\n", val & 0xfffffff0);
5206
5207 /* Try to enable I/O accesses and bus-mastering */
5208 val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
5209 pci_write_config_dword(devno, PCI_COMMAND, val);
5210
5211 /* Make sure it worked */
5212 pci_read_config_dword(devno, PCI_COMMAND, &val);
5213 if (!(val & PCI_COMMAND_MEMORY)) {
5214 E1000_ERR(nic, "Can't enable I/O memory\n");
5215 continue;
5216 }
5217 if (!(val & PCI_COMMAND_MASTER)) {
5218 E1000_ERR(nic, "Can't enable bus-mastering\n");
5219 continue;
5220 }
wdenk682011f2003-06-03 23:54:09 +00005221
5222 /* Are these variables needed? */
wdenk682011f2003-06-03 23:54:09 +00005223 hw->fc = e1000_fc_default;
5224 hw->original_fc = e1000_fc_default;
wdenk682011f2003-06-03 23:54:09 +00005225 hw->autoneg_failed = 0;
Roy Zangaa070782009-07-31 13:34:02 +08005226 hw->autoneg = 1;
wdenk682011f2003-06-03 23:54:09 +00005227 hw->get_link_status = TRUE;
Kyle Moffettd60626f82011-10-18 11:05:26 +00005228 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
5229 PCI_REGION_MEM);
wdenk682011f2003-06-03 23:54:09 +00005230 hw->mac_type = e1000_undefined;
5231
5232 /* MAC and Phy settings */
Kyle Moffettd60626f82011-10-18 11:05:26 +00005233 if (e1000_sw_init(nic) < 0) {
5234 E1000_ERR(nic, "Software init failed\n");
5235 continue;
wdenk682011f2003-06-03 23:54:09 +00005236 }
Roy Zangaa070782009-07-31 13:34:02 +08005237 if (e1000_check_phy_reset_block(hw))
Kyle Moffettd60626f82011-10-18 11:05:26 +00005238 E1000_ERR(nic, "PHY Reset is blocked!\n");
5239
Kyle Moffettce5207e2011-10-18 11:05:29 +00005240 /* Basic init was OK, reset the hardware and allow SPI access */
Roy Zangaa070782009-07-31 13:34:02 +08005241 e1000_reset_hw(hw);
Kyle Moffettce5207e2011-10-18 11:05:29 +00005242 list_add_tail(&hw->list_node, &e1000_hw_list);
Kyle Moffettd60626f82011-10-18 11:05:26 +00005243
5244 /* Validate the EEPROM and get chipset information */
Andre Schwarzac3315c2008-03-06 16:45:44 +01005245#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
Roy Zangaa070782009-07-31 13:34:02 +08005246 if (e1000_init_eeprom_params(hw)) {
Kyle Moffettd60626f82011-10-18 11:05:26 +00005247 E1000_ERR(nic, "EEPROM is invalid!\n");
5248 continue;
Roy Zangaa070782009-07-31 13:34:02 +08005249 }
Kyle Moffett114d7fc2011-10-18 11:05:27 +00005250 if (e1000_validate_eeprom_checksum(hw))
Kyle Moffettd60626f82011-10-18 11:05:26 +00005251 continue;
Wolfgang Denk7521af12005-10-09 01:04:33 +02005252#endif
wdenk682011f2003-06-03 23:54:09 +00005253 e1000_read_mac_addr(nic);
Roy Zangaa070782009-07-31 13:34:02 +08005254 e1000_get_bus_type(hw);
wdenk682011f2003-06-03 23:54:09 +00005255
Kyle Moffettd60626f82011-10-18 11:05:26 +00005256 printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
wdenk682011f2003-06-03 23:54:09 +00005257 nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2],
5258 nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]);
5259
Kyle Moffettd60626f82011-10-18 11:05:26 +00005260 /* Set up the function pointers and register the device */
wdenk682011f2003-06-03 23:54:09 +00005261 nic->init = e1000_init;
5262 nic->recv = e1000_poll;
5263 nic->send = e1000_transmit;
5264 nic->halt = e1000_disable;
wdenk682011f2003-06-03 23:54:09 +00005265 eth_register(nic);
wdenk682011f2003-06-03 23:54:09 +00005266 }
Kyle Moffettd60626f82011-10-18 11:05:26 +00005267
5268 return i;
wdenk682011f2003-06-03 23:54:09 +00005269}
Kyle Moffettce5207e2011-10-18 11:05:29 +00005270
5271struct e1000_hw *e1000_find_card(unsigned int cardnum)
5272{
5273 struct e1000_hw *hw;
5274
5275 list_for_each_entry(hw, &e1000_hw_list, list_node)
5276 if (hw->cardnum == cardnum)
5277 return hw;
5278
5279 return NULL;
5280}
5281
5282#ifdef CONFIG_CMD_E1000
5283static int do_e1000(cmd_tbl_t *cmdtp, int flag,
5284 int argc, char * const argv[])
5285{
5286 struct e1000_hw *hw;
5287
5288 if (argc < 3) {
5289 cmd_usage(cmdtp);
5290 return 1;
5291 }
5292
5293 /* Make sure we can find the requested e1000 card */
5294 hw = e1000_find_card(simple_strtoul(argv[1], NULL, 10));
5295 if (!hw) {
5296 printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
5297 return 1;
5298 }
5299
5300 if (!strcmp(argv[2], "print-mac-address")) {
5301 unsigned char *mac = hw->nic->enetaddr;
5302 printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
5303 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
5304 return 0;
5305 }
5306
5307#ifdef CONFIG_E1000_SPI
5308 /* Handle the "SPI" subcommand */
5309 if (!strcmp(argv[2], "spi"))
5310 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
5311#endif
5312
5313 cmd_usage(cmdtp);
5314 return 1;
5315}
5316
5317U_BOOT_CMD(
5318 e1000, 7, 0, do_e1000,
5319 "Intel e1000 controller management",
5320 /* */"<card#> print-mac-address\n"
5321#ifdef CONFIG_E1000_SPI
5322 "e1000 <card#> spi show [<offset> [<length>]]\n"
5323 "e1000 <card#> spi dump <addr> <offset> <length>\n"
5324 "e1000 <card#> spi program <addr> <offset> <length>\n"
5325 "e1000 <card#> spi checksum [update]\n"
5326#endif
5327 " - Manage the Intel E1000 PCI device"
5328);
5329#endif /* not CONFIG_CMD_E1000 */