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wdenk7a8e9bed2003-05-31 18:35:21 +00001/*
2 * (C) Copyright 2002
Graeme Russdbf71152011-04-13 19:43:26 +10003 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk7a8e9bed2003-05-31 18:35:21 +00004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
wdenk8bde7f72003-06-27 21:31:46 +000024#include <common.h>
25#include <pci.h>
26#include <asm/io.h>
27#include <asm/pci.h>
wdenk7a8e9bed2003-05-31 18:35:21 +000028
wdenk7a8e9bed2003-05-31 18:35:21 +000029#undef PCI_ROM_SCAN_VERBOSE
30
wdenk8bde7f72003-06-27 21:31:46 +000031int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
wdenk7a8e9bed2003-05-31 18:35:21 +000032{
33 struct pci_controller *hose;
34 int res = -1;
35 int i;
wdenk8bde7f72003-06-27 21:31:46 +000036
wdenk7a8e9bed2003-05-31 18:35:21 +000037 u32 rom_addr;
38 u32 addr_reg;
39 u32 size;
wdenk8bde7f72003-06-27 21:31:46 +000040
wdenk7a8e9bed2003-05-31 18:35:21 +000041 u16 vendor;
42 u16 device;
43 u32 class_code;
44
45 hose = pci_bus_to_hose(PCI_BUS(dev));
46#if 0
47 printf("pci_shadow_rom() asked to shadow device %x to %x\n",
48 dev, (u32)dest);
wdenk8bde7f72003-06-27 21:31:46 +000049#endif
wdenk7a8e9bed2003-05-31 18:35:21 +000050 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
51 pci_read_config_word(dev, PCI_DEVICE_ID, &device);
52 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_code);
wdenk8bde7f72003-06-27 21:31:46 +000053
Wolfgang Denk53677ef2008-05-20 16:00:29 +020054 class_code &= 0xffffff00;
wdenk7a8e9bed2003-05-31 18:35:21 +000055 class_code >>= 8;
56
Graeme Russdbf71152011-04-13 19:43:26 +100057 debug("PCI Header Vendor %04x device %04x class %06x\n",
wdenk7a8e9bed2003-05-31 18:35:21 +000058 vendor, device, class_code);
Graeme Russdbf71152011-04-13 19:43:26 +100059
wdenk7a8e9bed2003-05-31 18:35:21 +000060 /* Enable the rom addess decoder */
Graeme Russd7549022009-08-23 12:59:50 +100061 pci_write_config_dword(dev, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
wdenk7a8e9bed2003-05-31 18:35:21 +000062 pci_read_config_dword(dev, PCI_ROM_ADDRESS, &addr_reg);
63
64 if (!addr_reg) {
65 /* register unimplemented */
66 printf("pci_chadow_rom: device do not seem to have a rom\n");
67 return -1;
68 }
wdenk8bde7f72003-06-27 21:31:46 +000069
70 size = (~(addr_reg&PCI_ROM_ADDRESS_MASK))+1;
71
Graeme Russdbf71152011-04-13 19:43:26 +100072 debug("ROM is %d bytes\n", size);
73
wdenk7a8e9bed2003-05-31 18:35:21 +000074 rom_addr = pci_get_rom_window(hose, size);
Graeme Russdbf71152011-04-13 19:43:26 +100075
76 debug("ROM mapped at %x\n", rom_addr);
77
wdenk8bde7f72003-06-27 21:31:46 +000078 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
wdenk7a8e9bed2003-05-31 18:35:21 +000079 pci_phys_to_mem(dev, rom_addr)
80 |PCI_ROM_ADDRESS_ENABLE);
81
82
wdenk7a8e9bed2003-05-31 18:35:21 +000083 for (i=rom_addr;i<rom_addr+size; i+=512) {
wdenk8bde7f72003-06-27 21:31:46 +000084
85
wdenk7a8e9bed2003-05-31 18:35:21 +000086 if (readw(i) == 0xaa55) {
87 u32 pci_data;
88#ifdef PCI_ROM_SCAN_VERBOSE
89 printf("ROM signature found\n");
wdenk8bde7f72003-06-27 21:31:46 +000090#endif
wdenk7a8e9bed2003-05-31 18:35:21 +000091 pci_data = readw(0x18+i);
92 pci_data += i;
wdenk8bde7f72003-06-27 21:31:46 +000093
wdenk7a8e9bed2003-05-31 18:35:21 +000094 if (0==memcmp((void*)pci_data, "PCIR", 4)) {
wdenk8bde7f72003-06-27 21:31:46 +000095#ifdef PCI_ROM_SCAN_VERBOSE
wdenk7a8e9bed2003-05-31 18:35:21 +000096 printf("Fount PCI rom image at offset %d\n", i-rom_addr);
97 printf("Vendor %04x device %04x class %06x\n",
98 readw(pci_data+4), readw(pci_data+6),
99 readl(pci_data+0x0d)&0xffffff);
wdenk8bde7f72003-06-27 21:31:46 +0000100 printf("%s\n",
wdenk7a8e9bed2003-05-31 18:35:21 +0000101 (readw(pci_data+0x15) &0x80)?
102 "Last image":"More images follow");
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200103 switch (readb(pci_data+0x14)) {
wdenk7a8e9bed2003-05-31 18:35:21 +0000104 case 0:
105 printf("X86 code\n");
106 break;
107 case 1:
108 printf("Openfirmware code\n");
109 break;
110 case 2:
111 printf("PARISC code\n");
112 break;
113 }
114 printf("Image size %d\n", readw(pci_data+0x10) * 512);
wdenk8bde7f72003-06-27 21:31:46 +0000115#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000116 /* FixMe: I think we should compare the class code
117 * bytes as well but I have no reference on the
118 * exact order of these bytes in the PCI ROM header */
wdenk8bde7f72003-06-27 21:31:46 +0000119 if (readw(pci_data+4) == vendor &&
wdenk7a8e9bed2003-05-31 18:35:21 +0000120 readw(pci_data+6) == device &&
121 /* (readl(pci_data+0x0d)&0xffffff) == class_code && */
122 readb(pci_data+0x14) == 0 /* x86 code image */ ) {
wdenk8bde7f72003-06-27 21:31:46 +0000123#ifdef PCI_ROM_SCAN_VERBOSE
wdenk7a8e9bed2003-05-31 18:35:21 +0000124 printf("Suitable ROM image found, copying\n");
wdenk8bde7f72003-06-27 21:31:46 +0000125#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000126 memmove(dest, (void*)rom_addr, readw(pci_data+0x10) * 512);
127 res = 0;
128 break;
wdenk8bde7f72003-06-27 21:31:46 +0000129
wdenk7a8e9bed2003-05-31 18:35:21 +0000130 }
131 if (readw(pci_data+0x15) &0x80) {
132 break;
133 }
134 }
135 }
wdenk8bde7f72003-06-27 21:31:46 +0000136
wdenk7a8e9bed2003-05-31 18:35:21 +0000137 }
wdenk8bde7f72003-06-27 21:31:46 +0000138
wdenk7a8e9bed2003-05-31 18:35:21 +0000139#ifdef PCI_ROM_SCAN_VERBOSE
140 if (res) {
141 printf("No suitable image found\n");
142 }
wdenk8bde7f72003-06-27 21:31:46 +0000143#endif
wdenk7a8e9bed2003-05-31 18:35:21 +0000144 /* disable PAR register and PCI device ROM address devocer */
145 pci_remove_rom_window(hose, rom_addr);
wdenk8bde7f72003-06-27 21:31:46 +0000146
wdenk7a8e9bed2003-05-31 18:35:21 +0000147 pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0);
148
149 return res;
150}